//
// Copyright (c) 2019 NVIDIA Corporation.
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARCLK_RST_H_INC
#define ARCLK_RST_H_INC
#define NV_MOBILE_ARCLK_RST_H_UNIT_OF_OFFSET 1B


// Register CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0                    MK_ADDR_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0                        MK_ADDR_CONST(0x4)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0                        MK_ADDR_CONST(0x8)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_KFUSE_0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0                      MK_ADDR_CONST(0xc)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0                  MK_ADDR_CONST(0x10)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0                  MK_ADDR_CONST(0x14)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPU_0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0                        MK_ADDR_CONST(0x18)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0                    MK_ADDR_CONST(0x1c)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0                    MK_ADDR_CONST(0x20)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0                   MK_ADDR_CONST(0x1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0                       MK_ADDR_CONST(0x1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0                       MK_ADDR_CONST(0x1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0                    MK_ADDR_CONST(0x100c)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SCR                        0
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_RESET_VAL                  MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_DEFAULT                    MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0_SWD_CLK_DIVISOR__PROD                      MK_MASK_CONST(0xe)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0                    MK_ADDR_CONST(0x1010)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0_CLK_ENB_SWD_SCAN_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0                        MK_ADDR_CONST(0x1014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0_SET_CLK_ENB_SWD_SCAN_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0                        MK_ADDR_CONST(0x1018)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0_CLR_CLK_ENB_SWD_SCAN_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0                    MK_ADDR_CONST(0x101c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_RESET_VAL                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0                        MK_ADDR_CONST(0x1020)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_RESET_VAL                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0                        MK_ADDR_CONST(0x1024)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_RESET_VAL                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0                   MK_ADDR_CONST(0x2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0                    MK_ADDR_CONST(0x2004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_RANGE                    1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0                       MK_ADDR_CONST(0x2008)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SCR                   0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_RESET_MASK                    MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_READ_MASK                     MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_WRITE_MASK                    MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_RANGE                 14:14
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_INIT_ENUM                     TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_TSOSC_CLK                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CV0_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_RANGE                        13:13
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_PLLX_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_RANGE                        12:12
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU4_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_RANGE                        11:11
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU3_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_RANGE                        10:10
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU2_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_RANGE                        9:9
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU1_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_RANGE                        8:8
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_GPU0_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_RANGE                        7:7
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU7_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_RANGE                        6:6
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU6_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_RANGE                        5:5
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU5_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_RANGE                        4:4
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU4_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_RANGE                        3:3
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU3_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_RANGE                        2:2
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU2_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_RANGE                        1:1
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU1_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_RANGE                        0:0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_INIT_ENUM                    TSOSC_CLK
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_TSOSC_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0_SOC_THERM_CPU0_TSOSC_FTM_MUX_SEL_ALT_FTM_CLK                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SPARE0_0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0                 MK_ADDR_CONST(0x3000)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_RANGE                  31:0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE1_0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0                 MK_ADDR_CONST(0x3004)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_RANGE                  31:0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE2_0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0                 MK_ADDR_CONST(0x3008)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_RANGE                   31:0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0                      MK_ADDR_CONST(0x300c)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_SHIFT)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_RANGE                    0:0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_ENABLE                   MK_ENUM_CONST(1)


// Reserved address 0x3010

// Reserved address 0x3014

// Reserved address 0x3018

// Reserved address 0x301c

// Reserved address 0x3020

// Register CLK_RST_CONTROLLER_LOCK_BOND_OUT_0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0                      MK_ADDR_CONST(0x3024)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SCR                  0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_RANGE                 1:1
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SHIFT)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_RANGE                      0:0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x3028

// Reserved address 0x302c

// Reserved address 0x3030

// Reserved address 0x3034

// Reserved address 0x3038

// Reserved address 0x303c

// Reserved address 0x3040

// Reserved address 0x3044

// Reserved address 0x3048

// Reserved address 0x304c

// Reserved address 0x3050

// Reserved address 0x3054

// Reserved address 0x3058

// Reserved address 0x305c

// Reserved address 0x3060

// Reserved address 0x3064

// Reserved address 0x3068

// Reserved address 0x306c

// Reserved address 0x3070

// Reserved address 0x3074

// Reserved address 0x3078

// Reserved address 0x307c

// Reserved address 0x3080

// Reserved address 0x3084

// Reserved address 0x3088

// Reserved address 0x308c

// Reserved address 0x3090

// Reserved address 0x3094

// Reserved address 0x3098

// Reserved address 0x309c

// Reserved address 0x30a0

// Register CLK_RST_CONTROLLER_INTSTATUS_0
#define CLK_RST_CONTROLLER_INTSTATUS_0                  MK_ADDR_CONST(0x30a4)
#define CLK_RST_CONTROLLER_INTSTATUS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_INTSTATUS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_INTSTATUS_0_SCR                      0
#define CLK_RST_CONTROLLER_INTSTATUS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_INTSTATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_RESET_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTSTATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_READ_MASK                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTSTATUS_0_WRITE_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_FIELD                    MK_FIELD_CONST(0xfffff, CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_SHIFT)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_RANGE                    19:0
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_DEFAULT_MASK                     MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SPARE_REG0_0
#define CLK_RST_CONTROLLER_SPARE_REG0_0                 MK_ADDR_CONST(0x30a8)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_SCR                     0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SPARE_REG0_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_RESET_MASK                      MK_MASK_CONST(0xfffffff1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_READ_MASK                       MK_MASK_CONST(0xfffffff1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_WRITE_MASK                      MK_MASK_CONST(0xfffffff1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_FIELD                       MK_FIELD_CONST(0x3ffffff, CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_SHIFT)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_RANGE                       31:6
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_DEFAULT_MASK                        MK_MASK_CONST(0x3ffffff)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_SHIFT)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_RANGE                   5:5
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_RANGE                      4:4
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_RANGE                      0:0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE__PROD                      MK_MASK_CONST(0x1)


// Reserved address 0x30ac

// Reserved address 0x30b0

// Reserved address 0x30b4

// Register CLK_RST_CONTROLLER_CLK_MASK_ARM_0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0                       MK_ADDR_CONST(0x30b8)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_MASK                    MK_MASK_CONST(0x30000)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_READ_MASK                     MK_MASK_CONST(0x30000)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WRITE_MASK                    MK_MASK_CONST(0x30000)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_RANGE                      17:17
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_RANGE                       16:16
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_MISC_CLK_ENB_0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0                       MK_ADDR_CONST(0x30bc)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SCR                   0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_MASK                    MK_MASK_CONST(0x10f00000)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_READ_MASK                     MK_MASK_CONST(0x10f00000)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WRITE_MASK                    MK_MASK_CONST(0x10f00000)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_RANGE                 28:28
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SHIFT)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_RANGE                        23:22
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SHIFT)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_RANGE                        21:20
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0                  MK_ADDR_CONST(0x30c0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SCR                      0
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_READ_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_FIELD                  MK_FIELD_CONST(0x7f, CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_RANGE                  6:0
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0_SOC2CCPLEX_CLKOBS_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0                   MK_ADDR_CONST(0x30c4)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SCR                       0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_RESET_MASK                        MK_MASK_CONST(0x9fffc60f)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_READ_MASK                         MK_MASK_CONST(0x9fffc60f)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_WRITE_MASK                        MK_MASK_CONST(0x9fffc60f)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_RANGE                     31:31
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_FIELD                  MK_FIELD_CONST(0x7fff, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_RANGE                  28:14
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADSP_CLK_T                     MK_ENUM_CONST(256)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADSP_DIV2_FUNC_AND_FTM_CLK                     MK_ENUM_CONST(257)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADSP_MUXED_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(258)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLA1_PTO_OBS                  MK_ENUM_CONST(260)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLA_PTO_OBS                   MK_ENUM_CONST(261)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADC_SOC_VMON_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(512)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AO_TSOSC2PMC_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(513)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_APB_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(514)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_I2C_SLOW_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(515)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_TOUCH_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(516)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_UART_FST_MIPI_CAL_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(517)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CLK_M_SYS_AO_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(518)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CLK_S_AO_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(519)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC5_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(520)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C10_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(521)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C2_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(522)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C8_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(523)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MSS_ENCRYPT_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(524)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_OSC_FREQ_DET_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(525)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM4_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(526)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPI2_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(527)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSC_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(528)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSC_HS_REF_CLK                 MK_ENUM_CONST(529)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSC_OSC_REF_CLK                        MK_ENUM_CONST(530)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSC_REF_CLK_T                  MK_ENUM_CONST(531)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTC_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(532)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTG_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(533)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VREF_RO_OUT_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(534)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLAON_PTO_OBS                 MK_ENUM_CONST(544)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VREFRO_PTO_OBS                 MK_ENUM_CONST(545)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_CPU_CLK_T                  MK_ENUM_CONST(768)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_CPU_NIC_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(769)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_NIC_CLK_T                  MK_ENUM_CONST(770)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN1_CORE_CLK_T                        MK_ENUM_CONST(771)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(772)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN1_HOST_CLK_T                        MK_ENUM_CONST(773)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN2_CORE_CLK_T                        MK_ENUM_CONST(774)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN2_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(775)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN2_HOST_CLK_T                        MK_ENUM_CONST(776)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AHUB_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(1280)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_APE_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(1281)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC1_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(1282)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC2_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(1283)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC3_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(1284)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC4_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(1285)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSPK1_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(1286)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSPK1_INTF_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(1287)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSPK2_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(1288)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSPK2_INTF_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(1289)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(1290)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S2_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(1291)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S3_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(1292)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S4_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(1293)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S5_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(1294)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S6_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(1295)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPDIF_IN_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(1296)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPDIF_OUT_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(1297)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_1_GATED_CLK                    MK_ENUM_CONST(1536)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_1_GATED_FUNC_AND_OCC_CLK_PREDLY                        MK_ENUM_CONST(1537)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_2_GATED_CLK                    MK_ENUM_CONST(1538)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_2_GATED_FUNC_AND_OCC_CLK_PREDLY                        MK_ENUM_CONST(1539)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_3_GATED_CLK                    MK_ENUM_CONST(1540)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_3_GATED_FUNC_AND_OCC_CLK_PREDLY                        MK_ENUM_CONST(1541)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_CENTRAL_GATED_CLK                      MK_ENUM_CONST(1542)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_CENTRAL_GATED_FUNC_AND_OCC_CLK_PREDLY                  MK_ENUM_CONST(1543)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_CLK_T                  MK_ENUM_CONST(1544)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(1545)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLAXICBB_PTO_OBS                    MK_ENUM_CONST(1552)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ACTMON_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(2048)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_BPMP_APB_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2049)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_BPMP_CPU_NIC_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(2050)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_BPMP_NIC_CLK_T                 MK_ENUM_CONST(2051)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SIMON_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(2052)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU0_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2053)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU1_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2054)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU2_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2055)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU3_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2056)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU4_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2057)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU5_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2058)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU6_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2059)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU7_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2060)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(2061)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_GPU0_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2062)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_GPU1_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2063)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_GPU2_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2064)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_GPU3_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2065)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_GPU4_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2066)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_PLLX_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2067)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSENSOR_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(2068)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLBPMP_PTO_OBS                      MK_ENUM_CONST(2080)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLBPMPCAM_PTO_OBS                     MK_ENUM_CONST(2081)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_JTAG_INTFC_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(2304)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_JTAG_REG_CLK                   MK_ENUM_CONST(2305)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADC_SOC_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(2306)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ARM_JTAG_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2307)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DIRECTDC_PIPE_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(2308)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_FUSE_SERIAL_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(2309)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HOST1X_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(2310)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C_SLOW_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2311)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_IST_CLK_T                      MK_ENUM_CONST(2312)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_IST_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(2313)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_LA_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(2314)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLP_DIV8_CLK_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(2315)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC_LEGACY_TM_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(2316)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SERDES1F_CLK_STAGGER_CAR                       MK_ENUM_CONST(2317)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CV1_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(2318)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR_SAFE_CLK_NG_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(2319)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UART_FST_MIPI_CAL_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(2320)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_USB2SCAN_CLK_OUT                       MK_ENUM_CONST(2321)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC2_PTO_OBS                  MK_ENUM_CONST(2336)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC3_PTO_OBS                  MK_ENUM_CONST(2337)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC_PTO_OBS                   MK_ENUM_CONST(2338)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLP_PTO_OBS                   MK_ENUM_CONST(2339)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADC_CV_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(2560)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CVNAS_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(2561)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DLA0_CORE_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(2562)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DLA0_FALCON_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(2563)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DLA1_CORE_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(2564)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DLA1_FALCON_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(2565)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA1_APB_CLK_T                 MK_ENUM_CONST(2566)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA1_AXI_CLK_GATED                     MK_ENUM_CONST(2567)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA1_CPU_AXI_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(2568)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA1_CPU_CLK_GATED                     MK_ENUM_CONST(2569)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA1_VPS_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(2570)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CV0_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(2571)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLCVNAS_PTO_OBS                     MK_ENUM_CONST(2576)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLDLA_FALCON_PTO_OBS                        MK_ENUM_CONST(2577)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLDLA_PTO_OBS                       MK_ENUM_CONST(2578)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLPVA_CORE_PTO_OBS                  MK_ENUM_CONST(2579)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLPVA_VPS_PTO_OBS                   MK_ENUM_CONST(2580)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLCV2_PTO_OBS                 MK_ENUM_CONST(2581)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLCV3_PTO_OBS                 MK_ENUM_CONST(2582)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLCV_PTO_OBS                  MK_ENUM_CONST(2583)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAYHUB_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(2816)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAYHUB_GATED_CLK                 MK_ENUM_CONST(2817)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVDISPLAYHUB_PTO_OBS                      MK_ENUM_CONST(2818)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLDISPHUB_PTO_OBS                     MK_ENUM_CONST(2819)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_DISP_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(3072)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P0_CLK_T_OBS_OUT                     MK_ENUM_CONST(3073)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(3074)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(3075)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD3_PTO_OBS                  MK_ENUM_CONST(3076)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLDP_PTO_OBS                  MK_ENUM_CONST(3077)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P1_CLK_T_OBS_OUT                     MK_ENUM_CONST(3328)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(3329)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(3330)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD2_PTO_OBS                  MK_ENUM_CONST(3332)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD_PTO_OBS                   MK_ENUM_CONST(3333)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P2_CLK_T_OBS_OUT                     MK_ENUM_CONST(3584)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P2_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(3585)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P3_CLK_T_OBS_OUT                     MK_ENUM_CONST(3586)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P3_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(3587)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_5_GATED_CLK                    MK_ENUM_CONST(5888)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_5_GATED_FUNC_AND_OCC_CLK_PREDLY                        MK_ENUM_CONST(5889)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_6_GATED_CLK                    MK_ENUM_CONST(5890)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_6_GATED_FUNC_AND_OCC_CLK_PREDLY                        MK_ENUM_CONST(5891)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EQOS_AXI_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(5892)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EQOS_PTP_REF_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(5893)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EQOS_RX_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(5894)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EQOS_TX_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(5895)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(5896)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM5_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(5897)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM6_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(5898)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM7_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(5899)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_QSPI0_2X_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(5900)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_QSPI0_CLK_T                    MK_ENUM_CONST(5901)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_QSPI1_2X_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(5902)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_QSPI1_CLK_T                    MK_ENUM_CONST(5903)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC4_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(5904)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC4_SHAPER_OBS_CLK                  MK_ENUM_CONST(5905)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTD_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(5906)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLREFE_PTO_OBS                        MK_ENUM_CONST(5920)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_GPU_GATED_FUNC_AND_OCC_CLK_PREDLY                      MK_ENUM_CONST(6144)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SYSCLK_PRE_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(6145)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX_PAD_TCLKOUT_IN                     MK_ENUM_CONST(6146)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA0_APB_CLK_T                 MK_ENUM_CONST(6656)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA0_AXI_CLK_GATED                     MK_ENUM_CONST(6657)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA0_CPU_AXI_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(6658)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA0_CPU_CLK_GATED                     MK_ENUM_CONST(6659)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PVA0_VPS_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(6660)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CCPLEX2SOC_CLKOBS_CLK                  MK_ENUM_CONST(6912)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDEC1_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(7424)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDEC_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(7425)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVENC1_CLK_T                   MK_ENUM_CONST(7426)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVENC1_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(7427)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVENC_CLK_T                    MK_ENUM_CONST(7428)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVENC_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(7429)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVDEC1_PTO_OBS                    MK_ENUM_CONST(7432)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVDEC_PTO_OBS                     MK_ENUM_CONST(7433)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVENC1_PTO_OBS                    MK_ENUM_CONST(7434)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVENC_PTO_OBS                     MK_ENUM_CONST(7435)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_4_GATED_CLK                    MK_ENUM_CONST(7680)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_4_GATED_FUNC_AND_OCC_CLK_PREDLY                        MK_ENUM_CONST(7681)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EXTPERIPH1_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(7682)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EXTPERIPH2_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(7683)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EXTPERIPH3_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(7684)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EXTPERIPH4_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(7685)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL1_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(7686)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL2_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(7687)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C3_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7688)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C4_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7689)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C5_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7690)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C6_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7691)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C7_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7692)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C9_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7693)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7694)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM2_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7695)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM3_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7696)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM8_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7697)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPI1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7698)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPI3_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7699)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TACH_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(7700)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTA_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(7701)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTB_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(7702)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTE_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(7703)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTF_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(7704)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTH_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(7705)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL4_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(7936)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC4_PTO_OBS                  MK_ENUM_CONST(7937)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MC_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(8192)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCSB_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(8193)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCSC_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(8194)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCSD_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(8195)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSC_DLL_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(8448)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSC_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(8449)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSC_LATENCY_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(8450)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSC_PTO_OBS                 MK_ENUM_CONST(8452)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSCB_PTO_OBS                        MK_ENUM_CONST(8453)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSD_DLL_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(8704)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSD_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(8705)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSD_LATENCY_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(8706)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSD_PTO_OBS                 MK_ENUM_CONST(8708)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSDB_PTO_OBS                        MK_ENUM_CONST(8709)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMC_DLL_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(8960)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMC_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(8961)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMC_LATENCY_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(8962)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLM_PTO_OBS                   MK_ENUM_CONST(8964)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMB_PTO_OBS                  MK_ENUM_CONST(8965)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSB_DLL_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(9216)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSB_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(9217)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSB_LATENCY_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(9218)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSB_PTO_OBS                 MK_ENUM_CONST(9220)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSBB_PTO_OBS                        MK_ENUM_CONST(9221)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL3_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(9472)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L0_RX_CLK_T                  MK_ENUM_CONST(9473)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L0_TX_CLK_T                  MK_ENUM_CONST(9474)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L10_RX_CLK_T                 MK_ENUM_CONST(9475)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L10_TX_CLK_T                 MK_ENUM_CONST(9476)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L11_RX_CLK_T                 MK_ENUM_CONST(9477)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L11_TX_CLK_T                 MK_ENUM_CONST(9478)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L1_RX_CLK_T                  MK_ENUM_CONST(9479)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L1_TX_CLK_T                  MK_ENUM_CONST(9480)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L2_RX_CLK_T                  MK_ENUM_CONST(9481)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L2_TX_CLK_T                  MK_ENUM_CONST(9482)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L3_RX_CLK_T                  MK_ENUM_CONST(9483)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L3_TX_CLK_T                  MK_ENUM_CONST(9484)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L4_RX_CLK_T                  MK_ENUM_CONST(9485)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L4_TX_CLK_T                  MK_ENUM_CONST(9486)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L5_RX_CLK_T                  MK_ENUM_CONST(9487)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L5_TX_CLK_T                  MK_ENUM_CONST(9488)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L6_RX_CLK_T                  MK_ENUM_CONST(9489)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L6_TX_CLK_T                  MK_ENUM_CONST(9490)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L7_RX_CLK_T                  MK_ENUM_CONST(9491)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L7_TX_CLK_T                  MK_ENUM_CONST(9492)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L8_RX_CLK_T                  MK_ENUM_CONST(9493)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L8_TX_CLK_T                  MK_ENUM_CONST(9494)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L9_RX_CLK_T                  MK_ENUM_CONST(9495)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_L9_TX_CLK_T                  MK_ENUM_CONST(9496)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_PLL0_TXCLKREF_FTM_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(9497)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_PLL1_TXCLKREF_FTM_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(9498)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_PLL2_TXCLKREF_FTM_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(9499)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HSIO_UPHY_PLL3_TXCLKREF_FTM_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(9500)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_CORE_PLL_FIXED_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(9501)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_IOBIST_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(9502)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_L0_RX_LS_BIT_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(9503)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_L0_RX_SYMB_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(9504)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_L0_TX_LS_3XBIT_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(9505)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_RX_PWM_BIT_CLK_FOR_FTM_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(9506)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_TX_1MHZ_REF_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(9507)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSITE_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(9984)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DBGAPB_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(9985)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TPIU_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(9986)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ISP_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(10496)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ISP_GATED_CLK                  MK_ENUM_CONST(10497)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLISP_PTO_OBS                       MK_ENUM_CONST(10498)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCHUBB_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(12544)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCHUBBB_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(12800)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_CPU_GATED_FUNC_AND_OCC_CLK_PREDLY                      MK_ENUM_CONST(13312)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCHUB_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(13313)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVJPG_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(15616)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVJPG_GATED_CLK                        MK_ENUM_CONST(15617)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVJPG_PTO_OBS                     MK_ENUM_CONST(15618)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL0_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(15872)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_L0_RX_CLK_T                  MK_ENUM_CONST(15873)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_L1_RX_CLK_T                  MK_ENUM_CONST(15874)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_L2_RX_CLK_T                  MK_ENUM_CONST(15875)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_L3_RX_CLK_T                  MK_ENUM_CONST(15876)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_L4_RX_CLK_T                  MK_ENUM_CONST(15877)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_L5_RX_CLK_T                  MK_ENUM_CONST(15878)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_L6_RX_CLK_T                  MK_ENUM_CONST(15879)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_L7_RX_CLK_T                  MK_ENUM_CONST(15880)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_NVL_RX_CLK_T                 MK_ENUM_CONST(15881)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_PLL0_TXCLKREF_FTM_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(15882)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVHS_UPHY_TX_CLK_T                     MK_ENUM_CONST(15883)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVLINK_SYSCLK_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(15884)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVLINK_TX_DIV_CLK                      MK_ENUM_CONST(15885)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLNVHS_PTO_OBS                        MK_ENUM_CONST(15888)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_PCIE_VSOC_GATED_FUNC_AND_OCC_CLK_PREDLY                        MK_ENUM_CONST(16128)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C0_P2U_MUXED_PCLK_T                       MK_ENUM_CONST(16129)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C1_AUX_CLK_T                      MK_ENUM_CONST(16130)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C1_CORE_CLK_T                     MK_ENUM_CONST(16131)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C1_P2U_MUXED_PCLK_T                       MK_ENUM_CONST(16132)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C2_AUX_CLK_T                      MK_ENUM_CONST(16133)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C2_CORE_CLK_T                     MK_ENUM_CONST(16134)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C2_P2U_MUXED_PCLK_T                       MK_ENUM_CONST(16135)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C3_AUX_CLK_T                      MK_ENUM_CONST(16136)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C3_CORE_CLK_T                     MK_ENUM_CONST(16137)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C3_P2U_MUXED_PCLK_T                       MK_ENUM_CONST(16138)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_C4_P2U_MUXED_PCLK_T                       MK_ENUM_CONST(16139)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L0_P2U_PCLK_T                     MK_ENUM_CONST(16140)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L10_P2U_PCLK_T                    MK_ENUM_CONST(16141)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L11_P2U_PCLK_T                    MK_ENUM_CONST(16142)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L1_P2U_PCLK_T                     MK_ENUM_CONST(16143)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L2_P2U_PCLK_T                     MK_ENUM_CONST(16144)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L3_P2U_PCLK_T                     MK_ENUM_CONST(16145)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L4_P2U_PCLK_T                     MK_ENUM_CONST(16146)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L5_P2U_PCLK_T                     MK_ENUM_CONST(16147)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L6_P2U_PCLK_T                     MK_ENUM_CONST(16148)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L7_P2U_PCLK_T                     MK_ENUM_CONST(16149)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L8_P2U_PCLK_T                     MK_ENUM_CONST(16150)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX0_L9_P2U_PCLK_T                     MK_ENUM_CONST(16151)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UPHY_STAGGER_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(16152)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLE_PTO_OBS                   MK_ENUM_CONST(16160)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_PCIE_VIO_GATED_FUNC_AND_OCC_CLK_PREDLY                 MK_ENUM_CONST(16640)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX1_C5_AUX_CLK_T                      MK_ENUM_CONST(16641)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX1_C5_P2U_MUXED_PCLK_T                       MK_ENUM_CONST(16642)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_RCE_CPU_NIC_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(17408)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLRCE_PTO_OBS                       MK_ENUM_CONST(17409)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SATA_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(17664)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SATA_OOB_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(17665)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL5_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(17920)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SCE_CPU_NIC_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(17921)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SCE_NIC_CLK_T                  MK_ENUM_CONST(17922)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLSCE_PTO_OBS                       MK_ENUM_CONST(17924)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ENTROPY_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(18176)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SE_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(18177)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SE_GATED_CLK                   MK_ENUM_CONST(18178)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSEC_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18179)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSEC_GATED_CLK                 MK_ENUM_CONST(18180)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSECB_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(18181)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSECB_GATED_CLK                        MK_ENUM_CONST(18182)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLSE_PTO_OBS                        MK_ENUM_CONST(18184)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLTSEC_PTO_OBS                      MK_ENUM_CONST(18185)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLTSECB_PTO_OBS                     MK_ENUM_CONST(18186)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HDA2CODEC_2X_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18432)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HDA2CODEC_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(18433)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HDA_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(18434)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_INT_HDA2CODEC_2X_CLK_OBS_OUT                   MK_ENUM_CONST(18435)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MAUD_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18436)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR0_REF_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(18437)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR1_REF_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(18438)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR2_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18439)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR2_REF_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(18440)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR3_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18441)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR3_REF_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(18442)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD4_PTO_OBS                  MK_ENUM_CONST(18448)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AUD_MCLK_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(18688)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC1_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(18689)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC3_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(18690)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UFSDEV_REF_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(18691)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UFSHC_CG_SYS_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18692)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSI_PADOUT_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(18944)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIAB_LANEA0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18945)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIAB_LANEA1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18946)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIAB_LANEB0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18947)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIAB_LANEB1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18948)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSICD_LANEA0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18949)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSICD_LANEA1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18950)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSICD_LANEB0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18951)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSICD_LANEB1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18952)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIEF_LANEA0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18953)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIEF_LANEA1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18954)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIEF_LANEB0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18955)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIEF_LANEB1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18956)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIGH_LANEA0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18957)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIGH_LANEA1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18958)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIGH_LANEB0_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18959)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIGH_LANEB1_FUNC_AND_FTM_CLK_OUT                      MK_ENUM_CONST(18960)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C12_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(18961)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C13_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(18962)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C14_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(18963)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVCSI_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(18964)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVCSILP_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(18965)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SLVSCIL_IOBIST_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(18966)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SLVSEC_PADCTRL_FUNC_AND_FTM_CLK_OUT                    MK_ENUM_CONST(18967)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VI_CONST_FUNC_AND_FTM_CLK_OUT                  MK_ENUM_CONST(18968)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VI_FUNC_AND_FTM_CLK_OUT                        MK_ENUM_CONST(18969)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VI_GATED_CLK                   MK_ENUM_CONST(18970)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLVI_PTO_OBS                        MK_ENUM_CONST(18976)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLNVCSI_PTO_OBS                       MK_ENUM_CONST(18977)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VIC_CLK_T                      MK_ENUM_CONST(19200)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VIC_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(19201)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLVIC_PTO_OBS                       MK_ENUM_CONST(19202)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CV2_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(20224)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_USB2_HSIC_TRK_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(20225)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_CLK480M_NVWRAP_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(20226)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_CORE_DEV_FUNC_AND_FTM_CLK_OUT                     MK_ENUM_CONST(20227)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_CORE_FUNC_AND_FTM_CLK_OUT                 MK_ENUM_CONST(20228)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_FALCON_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(20229)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMICLK480PLL                  MK_ENUM_CONST(20232)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMICLK48PLL                   MK_ENUM_CONST(20233)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMICLK60PLL                   MK_ENUM_CONST(20234)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMICLK60PLLMUX                        MK_ENUM_CONST(20235)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMIPLLVCOCLK                  MK_ENUM_CONST(20236)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMIPLL_PTO_OBS                        MK_ENUM_CONST(20237)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_INT_XUSB_HS_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(20736)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_INT_XUSB_SS_FUNC_AND_FTM_CLK_OUT                       MK_ENUM_CONST(20737)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_120M_CLK_T_OBS_OUT                        MK_ENUM_CONST(20738)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_FS_FUNC_AND_FTM_CLK_OUT                   MK_ENUM_CONST(20739)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_RANGE                 10:10
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_RANGE                  9:9
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_RANGE                 3:0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0                 MK_ADDR_CONST(0x30c8)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SCR                     0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x80ffffff)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_READ_MASK                       MK_MASK_CONST(0x80ffffff)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_RANGE                  31:31
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_FIELD                       MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_RANGE                       23:0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_INTMASK_0
#define CLK_RST_CONTROLLER_INTMASK_0                    MK_ADDR_CONST(0x30cc)
#define CLK_RST_CONTROLLER_INTMASK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_INTMASK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_INTMASK_0_SCR                        0
#define CLK_RST_CONTROLLER_INTMASK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_INTMASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_RESET_MASK                         MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTMASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_READ_MASK                  MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTMASK_0_WRITE_MASK                         MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_FIELD                  MK_FIELD_CONST(0xfffff, CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_SHIFT)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_RANGE                  19:0
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x30d0

// Reserved address 0x30d4

// Register CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0                   MK_ADDR_CONST(0x30d8)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_SCR                       0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_RANGE                     1:1
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_RANGE                      0:0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0                    MK_ADDR_CONST(0x30dc)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_RANGE                      0:0
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0_IST_SERDES4F_CLK_CG_EN_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x10000

// Reserved address 0x20000

// Reserved address 0x30000

// Register CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0                       MK_ADDR_CONST(0x40000)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_RESET_MASK                    MK_MASK_CONST(0x3ffe0e1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_READ_MASK                     MK_MASK_CONST(0x3ffe0e1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_WRITE_MASK                    MK_MASK_CONST(0x3ffe0e1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_RANGE                        25:25
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L11_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_RANGE                        24:24
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L10_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_RANGE                 23:23
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L9_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_RANGE                 22:22
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L8_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_RANGE                 21:21
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L7_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_RANGE                 20:20
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L6_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_RANGE                 19:19
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_RANGE                 18:18
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_RANGE                 17:17
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_RANGE                 16:16
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_RANGE                 15:15
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_RANGE                 14:14
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_RANGE                       13:13
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_RANGE                       7:7
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_RANGE                       6:6
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL2_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_RANGE                       5:5
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL3_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0                   MK_ADDR_CONST(0x40004)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_RESET_MASK                        MK_MASK_CONST(0x3ffe0e1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_READ_MASK                         MK_MASK_CONST(0x3ffe0e1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_WRITE_MASK                        MK_MASK_CONST(0x3ffe0e1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_RANGE                        25:25
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L11_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_RANGE                        24:24
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L10_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_RANGE                 23:23
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L9_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_RANGE                 22:22
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L8_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_RANGE                 21:21
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L7_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_RANGE                 20:20
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L6_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_RANGE                 19:19
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_RANGE                 18:18
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_RANGE                 17:17
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_RANGE                 16:16
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_RANGE                 15:15
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_RANGE                 14:14
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_RANGE                       13:13
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_RANGE                       7:7
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_RANGE                       6:6
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL2_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_RANGE                       5:5
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL3_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0                   MK_ADDR_CONST(0x40008)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_RESET_MASK                        MK_MASK_CONST(0x3ffe0e1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_READ_MASK                         MK_MASK_CONST(0x3ffe0e1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x3ffe0e1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_RANGE                        25:25
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L11_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_RANGE                        24:24
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L10_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_RANGE                 23:23
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L9_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_RANGE                 22:22
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L8_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_RANGE                 21:21
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L7_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_RANGE                 20:20
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L6_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_RANGE                 19:19
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_RANGE                 18:18
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_RANGE                 17:17
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_RANGE                 16:16
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_RANGE                 15:15
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_RANGE                 14:14
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_RANGE                       13:13
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_RANGE                       7:7
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_RANGE                       6:6
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL2_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_RANGE                       5:5
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL3_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UPHY_0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0                       MK_ADDR_CONST(0x4000c)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0                   MK_ADDR_CONST(0x40010)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0                   MK_ADDR_CONST(0x40014)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLE_SS_CNTL_0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0                       MK_ADDR_CONST(0x41000)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_RESET_VAL                     MK_MASK_CONST(0x20010025)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_RESET_MASK                    MK_MASK_CONST(0xfffffdff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_READ_MASK                     MK_MASK_CONST(0xfffffdff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_WRITE_MASK                    MK_MASK_CONST(0xfffffdff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_RANGE                        31:30
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_RANGE                        29:24
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_DEFAULT                      MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_RANGE                     23:16
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_RANGE                  15:15
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_RANGE                  14:14
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_RANGE                  13:13
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_RANGE                     12:12
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_RANGE                       11:11
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_RANGE                  10:10
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_RANGE                     8:0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_DEFAULT                   MK_MASK_CONST(0x25)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLE_MISC1_0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0                 MK_ADDR_CONST(0x41004)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_RESET_VAL                       MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_WRITE_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_RANGE                     31:31
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_INIT_ENUM                 PLLE_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_PLLE_CLK_OUT_PTO_OBS                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_PTO_ROOT_CLK_SEL_PLLE_CLK_OUT_PTO_DIV2                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_RANGE                 7:5
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_RANGE                    4:4
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_RANGE                   3:3
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_RANGE                    2:2
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLE_BASE_0
#define CLK_RST_CONTROLLER_PLLE_BASE_0                  MK_ADDR_CONST(0x41008)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLE_BASE_0_RESET_VAL                        MK_MASK_CONST(0x7d02)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_RESET_MASK                       MK_MASK_CONST(0xefffffff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_READ_MASK                        MK_MASK_CONST(0xefffffff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_WRITE_MASK                       MK_MASK_CONST(0xefffffff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SHIFT                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_RANGE                 30:30
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_MSB                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_LSB                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_FIELD                       MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_RANGE                       27:16
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_DEFAULT_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_27_16_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_DEFAULT                        MK_MASK_CONST(0x7d)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLE_BASE1_0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0                 MK_ADDR_CONST(0x4100c)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_RESET_VAL                       MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x18)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_FIELD                    MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_RANGE                    5:0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_DEFAULT                  MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_SW_DEFAULT                       MK_MASK_CONST(0x18)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_SW_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PLDIV_CML__PROD                    MK_MASK_CONST(0x18)


// Register CLK_RST_CONTROLLER_PLLE_MISC_0
#define CLK_RST_CONTROLLER_PLLE_MISC_0                  MK_ADDR_CONST(0x41010)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLE_MISC_0_RESET_VAL                        MK_MASK_CONST(0x6200)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x4000)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_WRITE_MASK                       MK_MASK_CONST(0xffffe7ff)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_RANGE                 31:16
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_RANGE                        15:15
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_RANGE                    14:14
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_ON                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL__PROD                    MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_RANGE                   13:13
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_OFF                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_ON                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_RANGE                      12:12
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_RANGE                  11:11
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_RANGE                       10:10
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_REF_ENABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_REF_DISABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_RANGE                   9:9
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_RANGE                   8:8
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_RANGE                   7:6
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_RANGE                  5:4
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_RANGE                  3:2
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_RANGE                  0:0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0                      MK_ADDR_CONST(0x41014)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_RANGE                   31:16
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_RANGE                      15:0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0                      MK_ADDR_CONST(0x41018)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_RANGE                       31:16
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLE_AUX_0
#define CLK_RST_CONTROLLER_PLLE_AUX_0                   MK_ADDR_CONST(0x4101c)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLE_AUX_0_RESET_VAL                         MK_MASK_CONST(0x6002070)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_RESET_MASK                        MK_MASK_CONST(0x9fffffff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x81000008)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x81000058)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_READ_MASK                         MK_MASK_CONST(0x9fffffff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_WRITE_MASK                        MK_MASK_CONST(0x93ffffff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_RANGE                 31:31
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SW_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_INIT_ENUM                     SKIP
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SKIP                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_INCLUDE                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE__PROD                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_RANGE                      27:26
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_INIT_ENUM                  SEQ_ON
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SEQ_OFF                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SEQ_ON                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SEQ_BUSY                   MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_RANGE                        25:25
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_INIT_ENUM                    SEQ_ON
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SEQ_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SEQ_ON                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_RANGE                     24:24
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_MSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_ENABLE                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE__PROD                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_RANGE                 23:16
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_RANGE                       15:8
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_DEFAULT                     MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_RANGE                        7:7
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_RANGE                       6:6
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL__PROD                       MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_RANGE                   5:5
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_RANGE                   4:4
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL__PROD                   MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_RANGE                    3:3
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_SW_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET__PROD                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_RANGE                        2:2
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_INIT_ENUM                    OSC_DIV
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_OSC_DIV                      MK_ENUM_CONST(0)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLE_AUX1_0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0                  MK_ADDR_CONST(0x41020)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_RESET_VAL                        MK_MASK_CONST(0x105)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_RANGE                    7:0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_DEFAULT                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0                   MK_ADDR_CONST(0x50000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_RANGE                        2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0                       MK_ADDR_CONST(0x50004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_WRITE_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_RANGE                        2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0                       MK_ADDR_CONST(0x50008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_RANGE                        2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLC_BASE_0
#define CLK_RST_CONTROLLER_PLLC_BASE_0                  MK_ADDR_CONST(0x5000c)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_VAL                        MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_MASK                       MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_READ_MASK                        MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_WRITE_MASK                       MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_ENABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_DISABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_RANGE                     27:27
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_RANGE                  26:26
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_LSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_RANGE                  24:20
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_RANGE                  17:10
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT                        MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC_MISC_0_0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0                        MK_ADDR_CONST(0x50010)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_RESET_VAL                      MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_RESET_MASK                     MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_READ_MASK                      MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_WRITE_MASK                     MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_INIT_ENUM                        PLLC_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_PLLC_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTO_ROOT_CLK_SEL_PLLC_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_SHIFT                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_RANGE                       30:30
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_MSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_LSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_RANGE                     19:4
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_DEFAULT                   MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_SW_DEFAULT                        MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_SW_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU__PROD                     MK_MASK_CONST(0x8000)

#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_RANGE                 3:3
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_FO                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_RANGE                   1:0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC_MISC_1_0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0                        MK_ADDR_CONST(0x50014)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_RESET_VAL                      MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_RESET_MASK                     MK_MASK_CONST(0x800ffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_READ_MASK                      MK_MASK_CONST(0x800ffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_WRITE_MASK                     MK_MASK_CONST(0x800ffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_OFF                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_ON                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC_MISC_2_0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0                        MK_ADDR_CONST(0x50018)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_RESET_VAL                      MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_RESET_MASK                     MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_READ_MASK                      MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_WRITE_MASK                     MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_RANGE                  31:24
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_DEFAULT                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_RANGE                    23:16
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_DEFAULT                  MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_SW_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_SW_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM__PROD                  MK_MASK_CONST(0xf)

#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_RANGE                     4:4
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_RANGE                    2:0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_DEFAULT                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC_MISC_3_0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0                        MK_ADDR_CONST(0x5001c)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_RESET_VAL                      MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_RESET_MASK                     MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_READ_MASK                      MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_WRITE_MASK                     MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_RANGE                        25:24
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_RANGE                       23:8
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_RANGE                        5:4
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_RANGE                  3:0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_DEFAULT                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC_MISC_4_0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0                        MK_ADDR_CONST(0x50020)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_RESET_VAL                      MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_RESET_MASK                     MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_READ_MASK                      MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_WRITE_MASK                     MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF__PROD                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_SHIFT                       MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_RANGE                       27:25
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_LSB                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_RANGE                       24:22
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_RANGE                       21:19
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_DEFAULT                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_RANGE                     18:16
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_DEFAULT                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_DEFAULT                 MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC_MISC_5_0
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0                        MK_ADDR_CONST(0x50024)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_RESET_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_READ_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_WRITE_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_5_0_PLLC_HPLL_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0                        MK_ADDR_CONST(0x50028)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_RESET_MASK                     MK_MASK_CONST(0xffffff81)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_READ_MASK                      MK_MASK_CONST(0xffffff81)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_WRITE_MASK                     MK_MASK_CONST(0xffffff80)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_EN_SSC_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_RANGE                    30:15
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_MODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_RANGE                     14:11
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_LO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_RANGE                     10:7
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSUG_HI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CFG_0_PLLC_SSC_READY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0                      MK_ADDR_CONST(0x5002c)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_RANGE                 31:16
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MAX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0_PLLC_DIVN_FRAC_SSC_MIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0                      MK_ADDR_CONST(0x50030)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_RANGE                  31:24
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_STEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_RANGE                   23:8
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DLF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_RANGE                   7:0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0_PLLC_SSC_DIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0                   MK_ADDR_CONST(0x51000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_RANGE                       2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_RANGE                        1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLM_BASE_0
#define CLK_RST_CONTROLLER_PLLM_BASE_0                  MK_ADDR_CONST(0x60000)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_VAL                        MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_MASK                       MK_MASK_CONST(0xec10ffff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_READ_MASK                        MK_MASK_CONST(0xec10ffff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_WRITE_MASK                       MK_MASK_CONST(0xe010ffff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_RANGE                     31:31
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_ENABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_DISABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_RANGE                  27:27
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_SHIFT                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_RANGE                     26:26
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_LSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_RANGE                  20:20
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT                        MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLM_MISC1_0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0                 MK_ADDR_CONST(0x60004)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_RESET_MASK                      MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_READ_MASK                       MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_WRITE_MASK                      MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_RANGE                   31:31
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_SW_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_SW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_CLAMP_PH90__PROD                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_FIELD                        MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_RANGE                        27:0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLM_MISC2_0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0                 MK_ADDR_CONST(0x60008)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_RESET_VAL                       MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_RESET_MASK                      MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_READ_MASK                       MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_WRITE_MASK                      MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_RANGE                     31:31
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_INIT_ENUM                 PLLM_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_PLLM_CLK_OUT_PTO_OBS                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTO_ROOT_CLK_SEL_PLLM_CLK_OUT_PTO_DIV2                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_RANGE                 17:16
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_RANGE                 15:14
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_RANGE                     13:13
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_RANGE                      12:12
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_RANGE                        11:11
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_RANGE                   10:10
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_RANGE                  9:8
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_FO                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_RANGE                 5:5
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_RANGE                    4:4
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_RANGE                        3:3
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_RANGE                  2:1
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMB_BASE_0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0                 MK_ADDR_CONST(0x6000c)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_RESET_VAL                       MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_RESET_MASK                      MK_MASK_CONST(0x4c10ffff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_READ_MASK                       MK_MASK_CONST(0x4c10ffff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_WRITE_MASK                      MK_MASK_CONST(0x4010ffff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_SHIFT                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_RANGE                   26:26
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_LSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_RANGE                        20:20
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_DEFAULT                      MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMB_MISC1_0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0                        MK_ADDR_CONST(0x60010)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_RESET_VAL                      MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_RANGE                   31:31
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_INIT_ENUM                       PLLMB_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_PLLMB_CLK_OUT_PTO_OBS                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_PTO_ROOT_CLK_SEL_PLLMB_CLK_OUT_PTO_DIV2                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_FIELD                      MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_RANGE                      27:0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLM_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0                        MK_ADDR_CONST(0x60014)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_RESET_VAL                      MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_RESET_MASK                     MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_READ_MASK                      MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_WRITE_MASK                     MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_RANGE                  29:29
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_RANGE                   28:28
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_RANGE                        25:23
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0                      MK_ADDR_CONST(0x60018)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_RANGE                       31:16
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0                      MK_ADDR_CONST(0x6001c)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_RANGE                      31:16
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMB_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0                       MK_ADDR_CONST(0x60020)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_RESET_VAL                     MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_RESET_MASK                    MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_READ_MASK                     MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0                     MK_ADDR_CONST(0x60024)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0                     MK_ADDR_CONST(0x60028)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0                   MK_ADDR_CONST(0x70000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_RESET_VAL                         MK_MASK_CONST(0xefdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_RESET_MASK                        MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_READ_MASK                         MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_WRITE_MASK                        MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_RANGE                     31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CV_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_SHIFT                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_RANGE                       30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_MSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_LSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_RANGE                    29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_RANGE                   27:27
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_SHIFT                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_LSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_RANGE                   24:24
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_MSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_RANGE                    23:23
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_SCE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_RANGE                        22:22
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_RANGE                        20:20
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHA_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_RANGE                   19:19
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_RANGE                   18:18
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOBB_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_RANGE                       17:17
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_RANGE                      14:14
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXUPHY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_RANGE                   13:13
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_EQOS_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_RANGE                       12:12
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXIOR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_RANGE                   11:11
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVHS_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_RANGE                   10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_RANGE                    9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXMEMIOR_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_RANGE                        8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTVXHB_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_RANGE                 7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC1_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_RANGE                  6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_RANGE                 5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC1_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_RANGE                    3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_RANGE                     2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVJPG_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0                       MK_ADDR_CONST(0x70004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_RESET_VAL                     MK_MASK_CONST(0xefdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_RESET_MASK                    MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_READ_MASK                     MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_RANGE                     31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CV_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_SHIFT                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_RANGE                       30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_MSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_LSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_RANGE                    29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_RANGE                   27:27
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_SHIFT                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_LSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_RANGE                   24:24
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_MSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_RANGE                    23:23
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_SCE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_RANGE                        22:22
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_RANGE                        20:20
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHA_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_RANGE                   19:19
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_RANGE                   18:18
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOBB_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_RANGE                       17:17
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_RANGE                      14:14
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXUPHY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_RANGE                   13:13
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_EQOS_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_RANGE                       12:12
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXIOR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_RANGE                   11:11
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVHS_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_RANGE                   10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_RANGE                    9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXMEMIOR_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_RANGE                        8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTVXHB_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_RANGE                 7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC1_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_RANGE                  6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_RANGE                 5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC1_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_RANGE                    3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_RANGE                     2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVJPG_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0                       MK_ADDR_CONST(0x70008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_RESET_VAL                     MK_MASK_CONST(0xefdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_READ_MASK                     MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_RANGE                     31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CV_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_SHIFT                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_RANGE                       30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_MSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_LSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_RANGE                    29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_RANGE                   27:27
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_SHIFT                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_LSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_RANGE                   24:24
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_MSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_RANGE                    23:23
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_SCE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_RANGE                        22:22
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_RANGE                        20:20
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHA_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_RANGE                   19:19
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_RANGE                   18:18
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOBB_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_RANGE                       17:17
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_RANGE                      14:14
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXUPHY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_RANGE                   13:13
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_EQOS_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_RANGE                       12:12
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXIOR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_RANGE                   11:11
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVHS_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_RANGE                   10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_RANGE                    9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXMEMIOR_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_RANGE                        8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTVXHB_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_RANGE                 7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC1_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_RANGE                  6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_RANGE                 5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC1_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_RANGE                    3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_RANGE                     2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVJPG_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLP_BASE_0
#define CLK_RST_CONTROLLER_PLLP_BASE_0                  MK_ADDR_CONST(0x7000c)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_VAL                        MK_MASK_CONST(0x115408)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_MASK                       MK_MASK_CONST(0xf9f3fcff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_READ_MASK                        MK_MASK_CONST(0xf9f3fcff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_WRITE_MASK                       MK_MASK_CONST(0xf1f3fcff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_ENABLE                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE__PROD                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_ENABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_DISABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_RANGE                  27:27
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_RANGE                  24:20
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_RANGE                  17:10
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT                        MK_MASK_CONST(0x55)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLP_OUTA_0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0                  MK_ADDR_CONST(0x70010)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_VAL                        MK_MASK_CONST(0x9)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_MASK                       MK_MASK_CONST(0xff0b)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_READ_MASK                        MK_MASK_CONST(0xff0b)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WRITE_MASK                       MK_MASK_CONST(0xff0b)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_RANGE                     15:8
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_RANGE                   3:3
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_RANGE                      0:0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_INIT_ENUM                  RESET_DISABLE
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_RESET_ENABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_RESET_DISABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLP_MISC_0
#define CLK_RST_CONTROLLER_PLLP_MISC_0                  MK_ADDR_CONST(0x70014)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_VAL                        MK_MASK_CONST(0x40000)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_MASK                       MK_MASK_CONST(0x80c6001f)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_READ_MASK                        MK_MASK_CONST(0x80c6001f)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_WRITE_MASK                       MK_MASK_CONST(0x80c6000f)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_INIT_ENUM                  PLLP_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_PLLP_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTO_ROOT_CLK_SEL_PLLP_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_RANGE                   23:22
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_FO                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_VCO                     MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_RANGE                     18:18
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_RANGE                 17:17
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_RANGE                      4:4
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_RANGE                  3:3
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_RANGE                  2:2
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_RANGE                   1:0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLP_RESHIFT_0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0                       MK_ADDR_CONST(0x70018)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_RESET_VAL                     MK_MASK_CONST(0x51)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_RESET_MASK                    MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_READ_MASK                     MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_WRITE_MASK                    MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_RANGE                 9:2
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_DEFAULT                       MK_MASK_CONST(0x14)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_RANGE                  0:0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_INIT_ENUM                      RESET_DISABLE
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_RESET_ENABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_RESET_DISABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLP_OUTC_0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0                  MK_ADDR_CONST(0x7001c)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_RESET_VAL                        MK_MASK_CONST(0x10000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_RESET_MASK                       MK_MASK_CONST(0xff0f0000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x2040000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0xff040000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_READ_MASK                        MK_MASK_CONST(0xff0f0000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_WRITE_MASK                       MK_MASK_CONST(0xff0f0000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_RANGE                    31:24
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_SW_DEFAULT                       MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_SW_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO__PROD                    MK_MASK_CONST(0x2)

#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_RANGE                  19:19
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_RANGE                  18:18
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_SW_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_ENABLE                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE__PROD                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_RANGE                    17:17
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_RANGE                     16:16
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_INIT_ENUM                 RESET_DISABLE
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_RESET_ENABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_RESET_DISABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLP_MISC1_0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0                 MK_ADDR_CONST(0x70020)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_RESET_MASK                      MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_READ_MASK                       MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_WRITE_MASK                      MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_FIELD                        MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_RANGE                        27:0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLP_MISC2_0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0                 MK_ADDR_CONST(0x70024)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_RESET_VAL                       MK_MASK_CONST(0x400)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_RESET_MASK                      MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_READ_MASK                       MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_WRITE_MASK                      MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_RANGE                 14:13
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_RANGE                 12:11
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_RANGE                        10:10
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0                   MK_ADDR_CONST(0x71000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_RESET_MASK                        MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_READ_MASK                         MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_WRITE_MASK                        MK_MASK_CONST(0xffdf7fff)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_RANGE                    31:31
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_RANGE                      30:30
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_DIRECTDC_PIPE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_RANGE                   29:29
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_RANGE                   28:28
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_RANGE                  27:27
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_SHIFT                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_RANGE                   26:26
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_LSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_RANGE                 25:25
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_MSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_RANGE                  24:24
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_RANGE                   23:23
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_SCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_RANGE                       22:22
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_RANGE                       20:20
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_RANGE                  19:19
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_RANGE                  18:18
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOBB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_RANGE                      17:17
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_RANGE                   16:16
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_RANGE                     14:14
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXUPHY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_RANGE                  13:13
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_EQOS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_RANGE                      12:12
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXIOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_RANGE                  11:11
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVHS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_RANGE                  10:10
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISPA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_RANGE                   9:9
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXMEMIOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_RANGE                       8:8
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTVXHB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_RANGE                        7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_RANGE                 6:6
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_RANGE                        5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_RANGE                 4:4
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_RANGE                   3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_RANGE                    2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_RANGE                 1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVJPG_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA_BASE_0
#define CLK_RST_CONTROLLER_PLLA_BASE_0                  MK_ADDR_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_VAL                        MK_MASK_CONST(0x80c003)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_MASK                       MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_READ_MASK                        MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_WRITE_MASK                       MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_ENABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_DISABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_RANGE                  26:26
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_LSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_RANGE                  24:20
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_RANGE                  17:10
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT                        MK_MASK_CONST(0x30)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA_MISC_0_0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0                        MK_ADDR_CONST(0x80004)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_RESET_VAL                      MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_RESET_MASK                     MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_READ_MASK                      MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_WRITE_MASK                     MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_INIT_ENUM                        PLLA_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_PLLA_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTO_ROOT_CLK_SEL_PLLA_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_SHIFT                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_RANGE                       30:30
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_MSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_LSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_RANGE                     19:4
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_DEFAULT                   MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_RANGE                 3:3
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_FO                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_RANGE                   1:0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA_MISC_1_0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0                        MK_ADDR_CONST(0x80008)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_RESET_VAL                      MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_RESET_MASK                     MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_READ_MASK                      MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_WRITE_MASK                     MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_OFF                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_ON                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_RANGE                  19:16
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA_MISC_2_0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0                        MK_ADDR_CONST(0x8000c)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_RESET_VAL                      MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_RESET_MASK                     MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_READ_MASK                      MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_WRITE_MASK                     MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_RANGE                  31:24
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_DEFAULT                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_RANGE                    23:16
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_DEFAULT                  MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_RANGE                     4:4
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_RANGE                    2:0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_DEFAULT                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA_MISC_3_0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0                        MK_ADDR_CONST(0x80010)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_RESET_VAL                      MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_RESET_MASK                     MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_READ_MASK                      MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_WRITE_MASK                     MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_RANGE                        25:24
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_RANGE                       23:8
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_RANGE                        5:4
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_RANGE                  3:0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_DEFAULT                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA_MISC_4_0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0                        MK_ADDR_CONST(0x80014)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_RESET_VAL                      MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_RESET_MASK                     MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_READ_MASK                      MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_WRITE_MASK                     MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF__PROD                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_SHIFT                       MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_RANGE                       27:25
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_LSB                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_RANGE                       24:22
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_RANGE                       21:19
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_DEFAULT                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_RANGE                     18:16
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_DEFAULT                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_DEFAULT                 MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA_OUT_0
#define CLK_RST_CONTROLLER_PLLA_OUT_0                   MK_ADDR_CONST(0x80018)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_VAL                         MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_MASK                        MK_MASK_CONST(0x4000ff03)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_READ_MASK                         MK_MASK_CONST(0x4000ff03)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_WRITE_MASK                        MK_MASK_CONST(0x4000ff03)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_RANGE                     15:8
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RANGE                      0:0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_INIT_ENUM                  RESET_ENABLE
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_ENABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE                      MK_ENUM_CONST(1)


// Reserved address 0x90000

// Reserved address 0x90004

// Reserved address 0x90008

// Reserved address 0x9000c

// Register CLK_RST_CONTROLLER_PLLD_BASE_0
#define CLK_RST_CONTROLLER_PLLD_BASE_0                  MK_ADDR_CONST(0xa0000)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_VAL                        MK_MASK_CONST(0x423e01)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_MASK                       MK_MASK_CONST(0xf3ffffff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_READ_MASK                        MK_MASK_CONST(0xf3ffffff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_WRITE_MASK                       MK_MASK_CONST(0xe3ffffff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_ENABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_DISABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_RANGE                 25:21
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_MSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_DEFAULT                       MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_RANGE                 20:16
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_DEFAULT                       MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT                        MK_MASK_CONST(0x3e)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xa0004

// Register CLK_RST_CONTROLLER_PLLD_MISC_0
#define CLK_RST_CONTROLLER_PLLD_MISC_0                  MK_ADDR_CONST(0xa0008)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_VAL                        MK_MASK_CONST(0x40000)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_MASK                       MK_MASK_CONST(0x87de0003)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_READ_MASK                        MK_MASK_CONST(0x87de0003)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_WRITE_MASK                       MK_MASK_CONST(0x87d60003)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_INIT_ENUM                  PLLD_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_PLLD_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTO_ROOT_CLK_SEL_PLLD_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_RANGE                   26:25
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_FO                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_RANGE                   24:23
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_MSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_RANGE                  22:22
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_RANGE                  20:20
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_RANGE                      19:19
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_RANGE                     18:18
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_RANGE                 17:17
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD_MISC1_0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0                 MK_ADDR_CONST(0xa000c)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_RESET_MASK                      MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_READ_MASK                       MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_WRITE_MASK                      MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_RANGE                       28:28
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_CLAMPA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_FIELD                        MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_RANGE                        27:0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD_MISC2_0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0                 MK_ADDR_CONST(0xa0010)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_RESET_MASK                      MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_READ_MASK                       MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_WRITE_MASK                      MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_RANGE                 14:13
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_RANGE                 12:11
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_RANGE                        10:10
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0                        MK_ADDR_CONST(0xa0014)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_RESET_VAL                      MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_RESET_MASK                     MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_READ_MASK                      MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_WRITE_MASK                     MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_RANGE                  29:29
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_RANGE                   28:28
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_RANGE                        25:23
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0                      MK_ADDR_CONST(0xa0018)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_RANGE                       31:16
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0                      MK_ADDR_CONST(0xa001c)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_RANGE                      31:16
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Reserved address 0xa1000

// Reserved address 0xb0000

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0                   MK_ADDR_CONST(0xc0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0                       MK_ADDR_CONST(0xc0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0                       MK_ADDR_CONST(0xc0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0                   MK_ADDR_CONST(0xc1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0                    MK_ADDR_CONST(0xc2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_VAL                  MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_READ_MASK                  MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WRITE_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLA1_OUT1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SYNC_CLK                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0                        MK_ADDR_CONST(0xc2004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SPDIFIN                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S1                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S3                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S4                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S5                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_PLLA_OUT0                        MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S6                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0                   MK_ADDR_CONST(0xd0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0                       MK_ADDR_CONST(0xd0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0                       MK_ADDR_CONST(0xd0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0                   MK_ADDR_CONST(0xd1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0                    MK_ADDR_CONST(0xd2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_RESET_VAL                  MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_RESET_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_READ_MASK                  MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_WRITE_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_PLLA1_OUT1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SYNC_CLK                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0                        MK_ADDR_CONST(0xd2004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SPDIFIN                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S1                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S3                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S4                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S5                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_PLLA_OUT0                        MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S6                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0                  MK_ADDR_CONST(0xe0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_RESET_VAL                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0                      MK_ADDR_CONST(0xe0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_RESET_VAL                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0                      MK_ADDR_CONST(0xe0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_RESET_VAL                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0                  MK_ADDR_CONST(0xe1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_RANGE                     1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0                       MK_ADDR_CONST(0xe2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_RESET_VAL                     MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_PLLA_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_PLLA1_OUT1                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SYNC_CLK                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0                        MK_ADDR_CONST(0xe2004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_RESET_VAL                      MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0                    MK_ADDR_CONST(0xe3000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xf0000

// Reserved address 0xf0004

// Reserved address 0x100000

// Register CLK_RST_CONTROLLER_RST_DEV_SPI3_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0                       MK_ADDR_CONST(0x110000)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0                   MK_ADDR_CONST(0x110004)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0                   MK_ADDR_CONST(0x110008)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0                   MK_ADDR_CONST(0x111000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0                       MK_ADDR_CONST(0x111004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0                       MK_ADDR_CONST(0x111008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0                   MK_ADDR_CONST(0x112000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0                    MK_ADDR_CONST(0x113000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x113004

// Register CLK_RST_CONTROLLER_RST_DEV_I2C1_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0                       MK_ADDR_CONST(0x120000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SCR                   I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0                   MK_ADDR_CONST(0x120004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SCR                       I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0                   MK_ADDR_CONST(0x120008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_SCR                       I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0                   MK_ADDR_CONST(0x121000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_SCR                       I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0                       MK_ADDR_CONST(0x121004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SCR                   I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0                       MK_ADDR_CONST(0x121008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_SCR                   I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0                   MK_ADDR_CONST(0x122000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_SCR                       I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0                    MK_ADDR_CONST(0x123000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SCR                        I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_READ_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WRITE_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0                   MK_ADDR_CONST(0x128000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_SCR                       I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0_I2C1_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0                    MK_ADDR_CONST(0x128004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_SCR                        I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0_I2C1_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0                 MK_ADDR_CONST(0x128008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_SCR                     I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0                        MK_ADDR_CONST(0x12800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_SCR                    I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0_I2C1_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0                     MK_ADDR_CONST(0x128010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_SCR                         I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0_I2C1_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0                   MK_ADDR_CONST(0x128014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_SCR                       I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0_I2C1_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0                    MK_ADDR_CONST(0x128018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_SCR                        I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0_I2C1_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0                     MK_ADDR_CONST(0x12801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_SCR                         I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0_I2C1_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0                   MK_ADDR_CONST(0x128020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_SCR                       I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0                       MK_ADDR_CONST(0x128024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_SCR                   I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0_I2C1_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0                       MK_ADDR_CONST(0x128028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_SCR                   I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0_I2C1_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0                       MK_ADDR_CONST(0x12802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_SCR                   I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0_I2C1_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0                    MK_ADDR_CONST(0x128030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_SCR                        I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0_I2C1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0                     MK_ADDR_CONST(0x128034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_SCR                         I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0_I2C1_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0                      MK_ADDR_CONST(0x12f000)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0                      MK_ADDR_CONST(0x12f004)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C1_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C5_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0                       MK_ADDR_CONST(0x130000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SCR                   I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0                   MK_ADDR_CONST(0x130004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SCR                       I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0                   MK_ADDR_CONST(0x130008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_SCR                       I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0                   MK_ADDR_CONST(0x131000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_SCR                       I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0                       MK_ADDR_CONST(0x131004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SCR                   I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0                       MK_ADDR_CONST(0x131008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_SCR                   I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0                   MK_ADDR_CONST(0x132000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_SCR                       I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0                    MK_ADDR_CONST(0x133000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_SCR                        I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_RESET_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_READ_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_WRITE_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0                   MK_ADDR_CONST(0x138000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_SCR                       I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0_I2C5_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0                    MK_ADDR_CONST(0x138004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_SCR                        I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0_I2C5_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0                 MK_ADDR_CONST(0x138008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_SCR                     I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0                        MK_ADDR_CONST(0x13800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_SCR                    I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0_I2C5_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0                     MK_ADDR_CONST(0x138010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_SCR                         I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0_I2C5_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0                   MK_ADDR_CONST(0x138014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_SCR                       I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0_I2C5_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0                    MK_ADDR_CONST(0x138018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_SCR                        I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0_I2C5_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0                     MK_ADDR_CONST(0x13801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_SCR                         I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0_I2C5_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0                   MK_ADDR_CONST(0x138020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_SCR                       I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0                       MK_ADDR_CONST(0x138024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_SCR                   I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0_I2C5_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0                       MK_ADDR_CONST(0x138028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_SCR                   I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0_I2C5_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0                       MK_ADDR_CONST(0x13802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_SCR                   I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0_I2C5_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0                    MK_ADDR_CONST(0x138030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_SCR                        I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0_I2C5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0                     MK_ADDR_CONST(0x138034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_SCR                         I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0_I2C5_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0                      MK_ADDR_CONST(0x13f000)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0                      MK_ADDR_CONST(0x13f004)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C5_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0x13f008

// Reserved address 0x13f00c

// Register CLK_RST_CONTROLLER_RST_DEV_SPI1_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0                       MK_ADDR_CONST(0x140000)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0                   MK_ADDR_CONST(0x140004)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0                   MK_ADDR_CONST(0x140008)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0                   MK_ADDR_CONST(0x141000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0                       MK_ADDR_CONST(0x141004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0                       MK_ADDR_CONST(0x141008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0                   MK_ADDR_CONST(0x142000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0                    MK_ADDR_CONST(0x143000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_ISP_0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0                        MK_ADDR_CONST(0x170000)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SCR                    ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0                    MK_ADDR_CONST(0x170004)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SCR                        ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0                    MK_ADDR_CONST(0x170008)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_SCR                        ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0                    MK_ADDR_CONST(0x171000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_SCR                        ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0                        MK_ADDR_CONST(0x171004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SCR                    ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0                        MK_ADDR_CONST(0x171008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_SCR                    ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0                    MK_ADDR_CONST(0x172000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_SCR                        ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0                     MK_ADDR_CONST(0x173000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_SCR                         ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_RESET_VAL                   MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_DFLL_ISP                        MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_PLLC2_OUT0                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_PLLC3_OUT0                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_CLK_M                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0                      MK_ADDR_CONST(0x173004)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SCR                  ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_RESET_VAL                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_RESET_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_READ_MASK                    MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_WRITE_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_ISP_0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0                      MK_ADDR_CONST(0x174000)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_SCR                  ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0                    MK_ADDR_CONST(0x178000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_SCR                        ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0_ISP_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0                     MK_ADDR_CONST(0x178004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_SCR                         ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0_ISP_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0                  MK_ADDR_CONST(0x178008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_SCR                      ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0_ISP_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0                 MK_ADDR_CONST(0x17800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_SCR                     ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0_ISP_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0                      MK_ADDR_CONST(0x178010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_SCR                  ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0_ISP_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0                    MK_ADDR_CONST(0x178014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_SCR                        ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0_ISP_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0                     MK_ADDR_CONST(0x178018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_SCR                         ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0_ISP_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0                      MK_ADDR_CONST(0x17801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_SCR                  ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0_ISP_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0                    MK_ADDR_CONST(0x178020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_SCR                        ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0_ISP_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0                        MK_ADDR_CONST(0x178024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_SCR                    ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0_ISP_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0                        MK_ADDR_CONST(0x178028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_SCR                    ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0_ISP_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0                        MK_ADDR_CONST(0x17802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_SCR                    ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0_ISP_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0                     MK_ADDR_CONST(0x178030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_SCR                         ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0_ISP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0                      MK_ADDR_CONST(0x178034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_SCR                  ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0_ISP_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0                       MK_ADDR_CONST(0x17f000)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SCR                   0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0                       MK_ADDR_CONST(0x17f004)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SCR                   0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_VI_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0                 MK_ADDR_CONST(0x180000)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SCR                     VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0                     MK_ADDR_CONST(0x180004)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SCR                         VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0                     MK_ADDR_CONST(0x180008)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_SCR                         VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0                    MK_ADDR_CONST(0x18000c)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SCR                        VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0                        MK_ADDR_CONST(0x180010)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SCR                    VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0                        MK_ADDR_CONST(0x180014)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_SCR                    VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0                     MK_ADDR_CONST(0x181000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_SCR                         VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_CONST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0                 MK_ADDR_CONST(0x181004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SCR                     VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_CONST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0                 MK_ADDR_CONST(0x181008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_SCR                     VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_CONST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0                     MK_ADDR_CONST(0x182000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_SCR                         VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_RANGE                     1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_CONST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0                      MK_ADDR_CONST(0x183000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SCR                  VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_MASK                   MK_MASK_CONST(0xe30000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_READ_MASK                    MK_MASK_CONST(0xe30000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WRITE_MASK                   MK_MASK_CONST(0xe30000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLC2_OUT0                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLC3_OUT0                        MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DFLL_VI                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_RANGE                     24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_MSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INIT_ENUM                 INTERNAL
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INTERNAL                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_EXTERNAL                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0                       MK_ADDR_CONST(0x183004)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SCR                   VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_RESET_VAL                     MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_RESET_MASK                    MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_READ_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_WRITE_MASK                    MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_RANGE                   15:8
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0                        MK_ADDR_CONST(0x183008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_SCR                    VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_RESET_VAL                      MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_SRC_CLK_M                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0_VI_CONST_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0                     MK_ADDR_CONST(0x188000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_SCR                         VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0_VI_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0                      MK_ADDR_CONST(0x188004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_SCR                  VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0_VI_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0                   MK_ADDR_CONST(0x188008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_SCR                       VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0_VI_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0                  MK_ADDR_CONST(0x18800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_SCR                      VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0_VI_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0                       MK_ADDR_CONST(0x188010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_SCR                   VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_FAULT_REPORT_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0_VI_FMON_ACTION_RESET_REQ_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_VI_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0                     MK_ADDR_CONST(0x188014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_SCR                         VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_RANGE                  6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_DC_FAULT_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                       5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REPORT_OVERFLOW_ERROR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_REF_CLK_WINDOW_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FMON_COUNTER_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VI_0_VI_FMON_ENABLE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0                      MK_ADDR_CONST(0x188018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_SCR                  VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                     0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0_VI_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0                       MK_ADDR_CONST(0x18801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_SCR                   VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_RESET_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_READ_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_WRITE_MASK                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_CLEAR_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_FAULT_OUT_STATUS_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_RANGE                  3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_OVERFLOW_ERROR_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                  2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0_VI_FMON_DC_FAULT_TRUE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0                     MK_ADDR_CONST(0x188020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_SCR                         VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_RESET_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_READ_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_WRITE_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_RANGE                 2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0_VI_FMON_LOAD_DATA_SEL_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0                 MK_ADDR_CONST(0x188024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_SCR                     VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0_VI_FMON_LOAD_DATA_DONE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0                 MK_ADDR_CONST(0x188028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_SCR                     VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_RANGE                      2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0_VI_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0                 MK_ADDR_CONST(0x18802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_SCR                     VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0_VI_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0                      MK_ADDR_CONST(0x188030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_SCR                  VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0_VI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0                       MK_ADDR_CONST(0x188034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_SCR                   VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_RANGE                      1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_REF_WINDOW_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0_VI_FMON_ENABLE_DEBUG_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0                        MK_ADDR_CONST(0x18f000)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SCR                    0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_SCR_FMON_0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0                        MK_ADDR_CONST(0x18f004)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SCR                    0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0                     MK_ADDR_CONST(0x190000)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0                 MK_ADDR_CONST(0x190004)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0                 MK_ADDR_CONST(0x190008)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0                 MK_ADDR_CONST(0x191000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0                     MK_ADDR_CONST(0x191004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0                     MK_ADDR_CONST(0x191008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0                 MK_ADDR_CONST(0x192000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0                  MK_ADDR_CONST(0x193000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_RESET_VAL                        MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLC4_MUXED                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_CLK_M                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Reserved address 0x193004

// Reserved address 0x193008

// Reserved address 0x19300c

// Reserved address 0x193010

// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0                     MK_ADDR_CONST(0x1b0000)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0                 MK_ADDR_CONST(0x1b0004)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0                 MK_ADDR_CONST(0x1b0008)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0                 MK_ADDR_CONST(0x1b1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0                     MK_ADDR_CONST(0x1b1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0                     MK_ADDR_CONST(0x1b1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0                 MK_ADDR_CONST(0x1b2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0                  MK_ADDR_CONST(0x1b3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_RESET_VAL                        MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_RESET_MASK                       MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_READ_MASK                        MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_WRITE_MASK                       MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT2_LJ                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT0_LJ                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT2                        MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT1                        MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT1_LJ                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_CLK_M                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_VCO                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_SHIFT                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_RANGE                  26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_LSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0                      MK_ADDR_CONST(0x1b3004)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_RESET_VAL                    MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_RESET_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_READ_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_ACTIVE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_BYPASS                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0                      MK_ADDR_CONST(0x1b3008)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_RESET_VAL                    MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_RESET_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_READ_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_ACTIVE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_BYPASS                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0                      MK_ADDR_CONST(0x1b300c)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_RESET_VAL                    MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_RESET_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_READ_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_ACTIVE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_BYPASS                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0                 MK_ADDR_CONST(0x1b3010)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SCR                     0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_RESET_VAL                       MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_RESET_MASK                      MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_READ_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_WRITE_MASK                      MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_RANGE                      31:31
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_RANGE                  11:11
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_RANGE                  10:10
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_RANGE                  9:9
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_RANGE                  8:8
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_RANGE                    7:7
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                        DEFAULT_SETTING
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_PROG                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_RANGE                      6:6
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                  ACTIVE
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_ACTIVE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_BYPASS                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_RANGE                     5:5
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_RANGE                     4:3
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_RANGE                     2:2
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_RANGE                     1:0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x1b3014

// Reserved address 0x1b3018

// Reserved address 0x1b301c

// Reserved address 0x1b3020

// Register CLK_RST_CONTROLLER_RST_DEV_UARTA_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0                      MK_ADDR_CONST(0x1c0000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0                  MK_ADDR_CONST(0x1c0004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0                  MK_ADDR_CONST(0x1c0008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0                  MK_ADDR_CONST(0x1c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0                      MK_ADDR_CONST(0x1c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0                      MK_ADDR_CONST(0x1c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0                  MK_ADDR_CONST(0x1c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0                   MK_ADDR_CONST(0x1c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_VAL                         MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_READ_MASK                         MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WRITE_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTB_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0                      MK_ADDR_CONST(0x1d0000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0                  MK_ADDR_CONST(0x1d0004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0                  MK_ADDR_CONST(0x1d0008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0                  MK_ADDR_CONST(0x1d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0                      MK_ADDR_CONST(0x1d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0                      MK_ADDR_CONST(0x1d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0                  MK_ADDR_CONST(0x1d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0                   MK_ADDR_CONST(0x1d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_VAL                         MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_READ_MASK                         MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WRITE_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_HOST1X_0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0                     MK_ADDR_CONST(0x1e0000)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SCR                         HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0                 MK_ADDR_CONST(0x1e0004)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SCR                     HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0                 MK_ADDR_CONST(0x1e0008)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_SCR                     HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0                 MK_ADDR_CONST(0x1e1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_SCR                     HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0                     MK_ADDR_CONST(0x1e1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SCR                         HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0                     MK_ADDR_CONST(0x1e1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_SCR                         HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0                 MK_ADDR_CONST(0x1e2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_SCR                     HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0                  MK_ADDR_CONST(0x1e3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SCR                      HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_VAL                        MK_MASK_CONST(0xa0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLC2_OUT0                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_CLK_M                     MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0                 MK_ADDR_CONST(0x1e8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_SCR                     HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0_HOST1X_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0                  MK_ADDR_CONST(0x1e8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_SCR                      HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0_HOST1X_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0                       MK_ADDR_CONST(0x1e8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_SCR                   HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_RESET_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_READ_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_WRITE_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0                      MK_ADDR_CONST(0x1e800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_SCR                  HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0_HOST1X_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0                   MK_ADDR_CONST(0x1e8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_SCR                       HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_FAULT_REPORT_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0_HOST1X_FMON_ACTION_RESET_REQ_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0                 MK_ADDR_CONST(0x1e8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_SCR                     HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_RESET_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_READ_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_WRITE_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_RANGE                  6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_DC_FAULT_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                       5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REPORT_OVERFLOW_ERROR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_REF_CLK_WINDOW_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FMON_COUNTER_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0                  MK_ADDR_CONST(0x1e8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_SCR                      HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                     0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0_HOST1X_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0                   MK_ADDR_CONST(0x1e801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_SCR                       HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_RESET_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_READ_MASK                         MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_WRITE_MASK                        MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_CLEAR_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_FAULT_OUT_STATUS_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_RANGE                  3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_OVERFLOW_ERROR_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                  2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0_HOST1X_FMON_DC_FAULT_TRUE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0                 MK_ADDR_CONST(0x1e8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_SCR                     HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_RESET_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_READ_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_WRITE_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_RANGE                 2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0                     MK_ADDR_CONST(0x1e8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_SCR                         HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0_HOST1X_FMON_LOAD_DATA_DONE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0                     MK_ADDR_CONST(0x1e8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_SCR                         HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_RANGE                      2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0_HOST1X_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0                     MK_ADDR_CONST(0x1e802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_SCR                         HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0_HOST1X_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0                  MK_ADDR_CONST(0x1e8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_SCR                      HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_READ_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_WRITE_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0_HOST1X_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0                   MK_ADDR_CONST(0x1e8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_SCR                       HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_RANGE                      1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_REF_WINDOW_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0_HOST1X_FMON_ENABLE_DEBUG_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0                    MK_ADDR_CONST(0x1ef000)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SCR                        0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0                    MK_ADDR_CONST(0x1ef004)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SCR                        0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x1ef008

// Reserved address 0x1ef00c

// Reserved address 0x1ef010

// Reserved address 0x1ef014

// Reserved address 0x1ef018

// Reserved address 0x1f0000

// Register CLK_RST_CONTROLLER_RST_DEV_EMC_0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0                        MK_ADDR_CONST(0x200000)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SCR                    EMC_SCR_EMC_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0                    MK_ADDR_CONST(0x200004)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SCR                        EMC_SCR_EMC_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0                    MK_ADDR_CONST(0x200008)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_SCR                        EMC_SCR_EMC_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_RESET_VAL                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0                    MK_ADDR_CONST(0x201000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_SCR                        EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_RESET_VAL                  MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_RESET_MASK                         MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_READ_MASK                  MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_WRITE_MASK                         MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_RANGE                      10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_RANGE                  9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_RANGE                   8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_RANGE                  7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_RANGE                       6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_RANGE                       5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_RANGE                      2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0                        MK_ADDR_CONST(0x201004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SCR                    EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_RESET_VAL                      MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_RESET_MASK                     MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_READ_MASK                      MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_WRITE_MASK                     MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_RANGE                      10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_RANGE                  9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_RANGE                   8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_RANGE                  7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_RANGE                       6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_RANGE                       5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_RANGE                      2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0                        MK_ADDR_CONST(0x201008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_SCR                    EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_RESET_VAL                      MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_RESET_MASK                     MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_READ_MASK                      MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_RANGE                      10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_RANGE                  9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_RANGE                   8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_RANGE                  7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_RANGE                       6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_RANGE                       5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_RANGE                      2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0                    MK_ADDR_CONST(0x202000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_SCR                        EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_RESET_MASK                         MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_READ_MASK                  MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_WRITE_MASK                         MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_RANGE                     10:10
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_RANGE                 9:9
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_RANGE                  8:8
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_RANGE                 7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_RANGE                      6:6
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_RANGE                      5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_RANGE                     2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_RANGE                 1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0                     MK_ADDR_CONST(0x203000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SCR                         EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_VAL                   MK_MASK_CONST(0x60900000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_MASK                  MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x108000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_READ_MASK                   MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WRITE_MASK                  MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_RANGE                        31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_INIT_ENUM                    OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLC_OUT0                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLP_OUT0                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_OSC_UNDIV                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_UD                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLMB_UD                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLMB_OUT0                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLP_UD                      MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_RANGE                      27:27
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_SHIFT                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_RANGE                        26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_LSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_RANGE                    25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_RANGE                   23:23
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_SWITCH_COMPLETE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_RANGE                   20:20
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_ENABLE                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN__PROD                   MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_RANGE                       15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_SW_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN__PROD                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0                     MK_ADDR_CONST(0x203004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_SCR                         EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_RESET_VAL                   MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_CLK_M                   MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0                 MK_ADDR_CONST(0x203008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_SCR                     EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_RESET_VAL                       MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_RESET_MASK                      MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_READ_MASK                       MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_WRITE_MASK                      MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_INIT_ENUM                       OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLM_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_OSC_UNDIV                       MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLM_UD                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLMB_UD                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLMB_OUT0                      MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLP_UD                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_RANGE                      11:10
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_PLLM_VCOA                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_PLLM_VCOB                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_EMC_DLL_SWITCH_OUT                 MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0                    MK_ADDR_CONST(0x20300c)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_SCR                        EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_RESET_VAL                  MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_RESET_MASK                         MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_READ_MASK                  MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_RANGE                        11:11
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_RANGE                        10:10
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_RANGE                        9:9
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_RANGE                        8:8
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_RANGE                  7:7
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                      DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_PROG                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_RANGE                    6:6
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                        ACTIVE
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_ACTIVE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_BYPASS                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_RANGE                   5:5
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_RANGE                   4:3
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_RANGE                   2:2
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_RANGE                   1:0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0                       MK_ADDR_CONST(0x203010)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_SCR                   EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_RESET_VAL                     MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_RESET_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_READ_MASK                     MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_RANGE                  31:31
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_RANGE                      11:11
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_RANGE                      10:10
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_RANGE                      9:9
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_RANGE                      8:8
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_RANGE                        7:7
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                    DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_PROG                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_RANGE                  6:6
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                      ACTIVE
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_ACTIVE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_BYPASS                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_RANGE                 4:3
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_RANGE                 1:0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0                        MK_ADDR_CONST(0x203014)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_SCR                    EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_RESET_VAL                      MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_RESET_MASK                     MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_READ_MASK                      MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_WRITE_MASK                     MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_RANGE                      31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_INIT_ENUM                  CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_OUT0                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLC_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_OUT0                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_CLK_M                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_UD                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_UD                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_OUT0                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_UD                    MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_RANGE                      26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_EMC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0                      MK_ADDR_CONST(0x204000)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_SCR                  EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0                        MK_ADDR_CONST(0x208000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_SCR                    EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0                 MK_ADDR_CONST(0x208004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_SCR                     EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0_EMC_CDB_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0                      MK_ADDR_CONST(0x208008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_SCR                  EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0                     MK_ADDR_CONST(0x20800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_SCR                         EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0                  MK_ADDR_CONST(0x208010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_SCR                      EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0_EMC_CDB_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0                        MK_ADDR_CONST(0x208014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_SCR                    EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0                 MK_ADDR_CONST(0x208018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_SCR                     EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0_EMC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0                  MK_ADDR_CONST(0x20801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_SCR                      EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0_EMC_CDB_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0                        MK_ADDR_CONST(0x208020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_SCR                    EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_RESET_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_READ_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0                    MK_ADDR_CONST(0x208024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_SCR                        EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0                    MK_ADDR_CONST(0x208028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_SCR                        EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0                    MK_ADDR_CONST(0x20802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_SCR                        EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0_EMC_CDB_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0                 MK_ADDR_CONST(0x208030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_SCR                     EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0_EMC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0                  MK_ADDR_CONST(0x208034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_SCR                      EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0_EMC_CDB_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0                       MK_ADDR_CONST(0x20f000)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SCR                   0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0                   MK_ADDR_CONST(0x20f004)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SCR                       0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0                       MK_ADDR_CONST(0x20f008)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SCR                   0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x210000

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0                     MK_ADDR_CONST(0x220000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0                 MK_ADDR_CONST(0x220004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0                 MK_ADDR_CONST(0x220008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0                     MK_ADDR_CONST(0x221000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0                      MK_ADDR_CONST(0x222000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Reserved address 0x222004

// Reserved address 0x222008

// Register CLK_RST_CONTROLLER_RST_DEV_I2C3_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0                       MK_ADDR_CONST(0x240000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SCR                   I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0                   MK_ADDR_CONST(0x240004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SCR                       I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0                   MK_ADDR_CONST(0x240008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_SCR                       I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0                   MK_ADDR_CONST(0x241000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_SCR                       I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0                       MK_ADDR_CONST(0x241004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SCR                   I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0                       MK_ADDR_CONST(0x241008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_SCR                   I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0                   MK_ADDR_CONST(0x242000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_SCR                       I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0                    MK_ADDR_CONST(0x243000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SCR                        I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_RESET_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_READ_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_WRITE_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0                   MK_ADDR_CONST(0x248000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_SCR                       I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0_I2C3_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0                    MK_ADDR_CONST(0x248004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_SCR                        I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0_I2C3_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0                 MK_ADDR_CONST(0x248008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_SCR                     I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0                        MK_ADDR_CONST(0x24800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_SCR                    I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0_I2C3_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0                     MK_ADDR_CONST(0x248010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_SCR                         I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0_I2C3_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0                   MK_ADDR_CONST(0x248014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_SCR                       I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0_I2C3_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0                    MK_ADDR_CONST(0x248018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_SCR                        I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0_I2C3_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0                     MK_ADDR_CONST(0x24801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_SCR                         I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0_I2C3_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0                   MK_ADDR_CONST(0x248020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_SCR                       I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0                       MK_ADDR_CONST(0x248024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_SCR                   I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0_I2C3_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0                       MK_ADDR_CONST(0x248028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_SCR                   I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0_I2C3_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0                       MK_ADDR_CONST(0x24802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_SCR                   I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0_I2C3_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0                    MK_ADDR_CONST(0x248030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_SCR                        I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0_I2C3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0                     MK_ADDR_CONST(0x248034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_SCR                         I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0_I2C3_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0                      MK_ADDR_CONST(0x24f000)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0                      MK_ADDR_CONST(0x24f004)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C3_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0                     MK_ADDR_CONST(0x250000)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0                 MK_ADDR_CONST(0x250004)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0                 MK_ADDR_CONST(0x250008)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0                 MK_ADDR_CONST(0x251000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0                     MK_ADDR_CONST(0x251004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0                     MK_ADDR_CONST(0x251008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0                 MK_ADDR_CONST(0x252000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0                  MK_ADDR_CONST(0x253000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_RESET_VAL                        MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLC4_MUXED                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_CLK_M                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTD_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0                      MK_ADDR_CONST(0x260000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0                  MK_ADDR_CONST(0x260004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0                  MK_ADDR_CONST(0x260008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0                  MK_ADDR_CONST(0x261000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0                      MK_ADDR_CONST(0x261004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0                      MK_ADDR_CONST(0x261008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0                  MK_ADDR_CONST(0x262000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0                   MK_ADDR_CONST(0x263000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_RESET_VAL                         MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_RESET_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_READ_MASK                         MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_WRITE_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Reserved address 0x263004

// Reserved address 0x263008

// Reserved address 0x270000

// Register CLK_RST_CONTROLLER_RST_DEV_CSITE_0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0                      MK_ADDR_CONST(0x280000)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0                  MK_ADDR_CONST(0x280004)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0                  MK_ADDR_CONST(0x280008)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0                  MK_ADDR_CONST(0x281000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0                      MK_ADDR_CONST(0x281004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0                      MK_ADDR_CONST(0x281008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0                  MK_ADDR_CONST(0x282000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0                   MK_ADDR_CONST(0x283000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLC2_OUT0                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLC3_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLREFE_VCOCLK                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_CLK_S                       MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLC4_MUXED                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0                   MK_ADDR_CONST(0x290000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0                       MK_ADDR_CONST(0x290004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0                       MK_ADDR_CONST(0x290008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0                   MK_ADDR_CONST(0x291000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0                    MK_ADDR_CONST(0x292000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_VAL                  MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_READ_MASK                  MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WRITE_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLA1_OUT1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SYNC_CLK                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0                        MK_ADDR_CONST(0x292004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SPDIFIN                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S1                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S3                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S4                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S5                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_PLLA_OUT0                        MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S6                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_RST_DEV_TSEC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0                       MK_ADDR_CONST(0x2b0000)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0                   MK_ADDR_CONST(0x2b0004)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0                   MK_ADDR_CONST(0x2b0008)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0                   MK_ADDR_CONST(0x2b1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0                       MK_ADDR_CONST(0x2b1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0                       MK_ADDR_CONST(0x2b1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0                   MK_ADDR_CONST(0x2b2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0                    MK_ADDR_CONST(0x2b3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLLC2_OUT0                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLLC3_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_DFLL_TSEC                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0                     MK_ADDR_CONST(0x2b3004)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SCR                         0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_RESET_VAL                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_RESET_MASK                  MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_READ_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_WRITE_MASK                  MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_LA_0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0                 MK_ADDR_CONST(0x2c0000)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_LA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0                     MK_ADDR_CONST(0x2c0004)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0                     MK_ADDR_CONST(0x2c0008)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0                     MK_ADDR_CONST(0x2c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0                 MK_ADDR_CONST(0x2c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0                 MK_ADDR_CONST(0x2c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0                     MK_ADDR_CONST(0x2c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_LA_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0                      MK_ADDR_CONST(0x2c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_RESET_VAL                    MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLC2_OUT0                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLC3_OUT0                        MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLREFE_VCOCLK                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_CLK_S                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_CLK_M                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLC4_MUXED                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Reserved address 0x2c3004

// Reserved address 0x2c3008

// Reserved address 0x2c300c

// Reserved address 0x2c3010

// Reserved address 0x2c3014

// Reserved address 0x2c3018

// Reserved address 0x2c301c

// Reserved address 0x2c3020

// Reserved address 0x2c3024

// Reserved address 0x2c3028

// Reserved address 0x2c302c

// Reserved address 0x2c3030

// Reserved address 0x2c3034

// Reserved address 0x2c3038

// Reserved address 0x2c303c

// Reserved address 0x2c3040

// Reserved address 0x2c3044

// Reserved address 0x2d0000

// Reserved address 0x2d0004

// Reserved address 0x2d0008

// Reserved address 0x2d000c

// Reserved address 0x2e0000

// Reserved address 0x2f0000

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0                   MK_ADDR_CONST(0x300000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0                       MK_ADDR_CONST(0x300004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0                       MK_ADDR_CONST(0x300008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0                   MK_ADDR_CONST(0x301000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0                    MK_ADDR_CONST(0x302000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_RESET_VAL                  MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_RESET_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_READ_MASK                  MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_WRITE_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_PLLA1_OUT1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SYNC_CLK                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0                        MK_ADDR_CONST(0x302004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SPDIFIN                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S1                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S3                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S4                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S5                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_PLLA_OUT0                        MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S6                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0                   MK_ADDR_CONST(0x310000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0                       MK_ADDR_CONST(0x310004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0                       MK_ADDR_CONST(0x310008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0                   MK_ADDR_CONST(0x311000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0                    MK_ADDR_CONST(0x312000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_RESET_VAL                  MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_RESET_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_READ_MASK                  MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_WRITE_MASK                         MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_PLLA1_OUT1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SYNC_CLK                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0                        MK_ADDR_CONST(0x312004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SPDIFIN                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S1                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S3                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S4                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S5                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_PLLA_OUT0                        MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S6                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C4_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0                       MK_ADDR_CONST(0x320000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SCR                   I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0                   MK_ADDR_CONST(0x320004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SCR                       I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0                   MK_ADDR_CONST(0x320008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_SCR                       I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0                   MK_ADDR_CONST(0x321000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_SCR                       I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0                       MK_ADDR_CONST(0x321004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SCR                   I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0                       MK_ADDR_CONST(0x321008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_SCR                   I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0                   MK_ADDR_CONST(0x322000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_SCR                       I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0                    MK_ADDR_CONST(0x323000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_SCR                        I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_RESET_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_READ_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_WRITE_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0                   MK_ADDR_CONST(0x328000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_SCR                       I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0_I2C4_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0                    MK_ADDR_CONST(0x328004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_SCR                        I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0_I2C4_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0                 MK_ADDR_CONST(0x328008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_SCR                     I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0                        MK_ADDR_CONST(0x32800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_SCR                    I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0_I2C4_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0                     MK_ADDR_CONST(0x328010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_SCR                         I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0_I2C4_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0                   MK_ADDR_CONST(0x328014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_SCR                       I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0_I2C4_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0                    MK_ADDR_CONST(0x328018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_SCR                        I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0_I2C4_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0                     MK_ADDR_CONST(0x32801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_SCR                         I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0_I2C4_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0                   MK_ADDR_CONST(0x328020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_SCR                       I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0                       MK_ADDR_CONST(0x328024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_SCR                   I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0_I2C4_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0                       MK_ADDR_CONST(0x328028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_SCR                   I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0_I2C4_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0                       MK_ADDR_CONST(0x32802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_SCR                   I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0_I2C4_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0                    MK_ADDR_CONST(0x328030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_SCR                        I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0_I2C4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0                     MK_ADDR_CONST(0x328034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_SCR                         I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0_I2C4_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0                      MK_ADDR_CONST(0x32f000)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0                      MK_ADDR_CONST(0x32f004)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C4_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0                   MK_ADDR_CONST(0x330000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0                       MK_ADDR_CONST(0x330004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0                       MK_ADDR_CONST(0x330008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0                   MK_ADDR_CONST(0x331000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0                    MK_ADDR_CONST(0x332000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_RESET_VAL                  MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_RESET_MASK                         MK_MASK_CONST(0xf01f00ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_READ_MASK                  MK_MASK_CONST(0xf01f00ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_WRITE_MASK                         MK_MASK_CONST(0xf01f00ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_PLLA1_OUT1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_CLK_SRC_ALT                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_RANGE                     20:20
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_ENABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_DISABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_RANGE                    19:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_INIT_ENUM                        SPDIFIN
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SPDIFIN                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S1                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S3                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S4                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S5                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_PLLA_OUT0                        MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S6                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x332004

// Reserved address 0x332008

// Reserved address 0x33200c

// Reserved address 0x332010

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0                   MK_ADDR_CONST(0x340000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0                       MK_ADDR_CONST(0x340004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0                       MK_ADDR_CONST(0x340008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0                   MK_ADDR_CONST(0x341000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0                    MK_ADDR_CONST(0x342000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_RESET_VAL                  MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_CLK_S                 MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x350000

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0                     MK_ADDR_CONST(0x360000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0                 MK_ADDR_CONST(0x360004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0                 MK_ADDR_CONST(0x360008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0                     MK_ADDR_CONST(0x361000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0                      MK_ADDR_CONST(0x362000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0                     MK_ADDR_CONST(0x370000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0                 MK_ADDR_CONST(0x370004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0                 MK_ADDR_CONST(0x370008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0                     MK_ADDR_CONST(0x371000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0                      MK_ADDR_CONST(0x372000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0                     MK_ADDR_CONST(0x380000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0                 MK_ADDR_CONST(0x380004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0                 MK_ADDR_CONST(0x380008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0                     MK_ADDR_CONST(0x381000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0                      MK_ADDR_CONST(0x382000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Reserved address 0x382004

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0                       MK_ADDR_CONST(0x390000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_SCR                   I2C_SLOW_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0                   MK_ADDR_CONST(0x390004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SCR                       I2C_SLOW_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0                   MK_ADDR_CONST(0x390008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_SCR                       I2C_SLOW_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0                       MK_ADDR_CONST(0x391000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_SCR                   I2C_SLOW_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0                        MK_ADDR_CONST(0x392000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_SCR                    I2C_SLOW_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0                       MK_ADDR_CONST(0x398000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_SCR                   I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0                        MK_ADDR_CONST(0x398004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_SCR                    I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0                     MK_ADDR_CONST(0x398008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_SCR                         I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0                    MK_ADDR_CONST(0x39800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_SCR                        I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0                 MK_ADDR_CONST(0x398010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_SCR                     I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0_I2C_SLOW_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0                       MK_ADDR_CONST(0x398014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_SCR                   I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0                        MK_ADDR_CONST(0x398018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_SCR                    I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0                 MK_ADDR_CONST(0x39801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_SCR                     I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_RESET_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_READ_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_WRITE_MASK                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0_I2C_SLOW_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0                       MK_ADDR_CONST(0x398020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_SCR                   I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_READ_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0                   MK_ADDR_CONST(0x398024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_SCR                       I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0                   MK_ADDR_CONST(0x398028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_SCR                       I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0                   MK_ADDR_CONST(0x39802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_SCR                       I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0_I2C_SLOW_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0                        MK_ADDR_CONST(0x398030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_SCR                    I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0                 MK_ADDR_CONST(0x398034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_SCR                     I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0_I2C_SLOW_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0                  MK_ADDR_CONST(0x39f000)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SCR                      0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0                  MK_ADDR_CONST(0x39f004)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x39f008

// Reserved address 0x39f00c

// Reserved address 0x39f010

// Register CLK_RST_CONTROLLER_RST_DEV_SOR1_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0                       MK_ADDR_CONST(0x3a0000)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SCR                   SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0                   MK_ADDR_CONST(0x3a0004)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SCR                       SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0                   MK_ADDR_CONST(0x3a0008)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_SCR                       SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0                   MK_ADDR_CONST(0x3a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_SCR                       SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0                       MK_ADDR_CONST(0x3a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SCR                   SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0                       MK_ADDR_CONST(0x3a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_SCR                   SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0                   MK_ADDR_CONST(0x3a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_SCR                       SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0                    MK_ADDR_CONST(0x3a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SCR                        SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_RESET_VAL                  MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_RESET_MASK                         MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_READ_MASK                  MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_WRITE_MASK                         MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLLD_OUT2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLLD2_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLLD3_OUT0                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLLD4_OUT0                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_RANGE                        15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_RANGE                        14:14
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0                   MK_ADDR_CONST(0x3a8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SCR                       SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0_SOR1_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0                    MK_ADDR_CONST(0x3a8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SCR                        SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0_SOR1_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0                 MK_ADDR_CONST(0x3a8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SCR                     SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0                        MK_ADDR_CONST(0x3a800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SCR                    SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0_SOR1_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0                     MK_ADDR_CONST(0x3a8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SCR                         SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0_SOR1_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0                   MK_ADDR_CONST(0x3a8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SCR                       SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0_SOR1_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0                    MK_ADDR_CONST(0x3a8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SCR                        SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0_SOR1_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0                     MK_ADDR_CONST(0x3a801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SCR                         SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0_SOR1_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0                   MK_ADDR_CONST(0x3a8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SCR                       SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0                       MK_ADDR_CONST(0x3a8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SCR                   SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0_SOR1_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0                       MK_ADDR_CONST(0x3a8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SCR                   SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0_SOR1_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0                       MK_ADDR_CONST(0x3a802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SCR                   SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0_SOR1_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0                    MK_ADDR_CONST(0x3a8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SCR                        SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0_SOR1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0                     MK_ADDR_CONST(0x3a8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SCR                         SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0_SOR1_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0                      MK_ADDR_CONST(0x3af000)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0                      MK_ADDR_CONST(0x3af004)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR1_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR2_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0                       MK_ADDR_CONST(0x1210000)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SCR                   SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_0_SWR_SOR2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0                   MK_ADDR_CONST(0x1210004)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SCR                       SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0_SET_SWR_SOR2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0                   MK_ADDR_CONST(0x1210008)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_SCR                       SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0_CLR_SWR_SOR2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0                   MK_ADDR_CONST(0x1211000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_SCR                       SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0_CLK_ENB_SOR2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0                       MK_ADDR_CONST(0x1211004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SCR                   SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0_SET_CLK_ENB_SOR2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0                       MK_ADDR_CONST(0x1211008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_SCR                   SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0_CLR_CLK_ENB_SOR2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0                   MK_ADDR_CONST(0x1212000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_SCR                       SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0_BOND_OUT_SOR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0                    MK_ADDR_CONST(0x1213000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SCR                        SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_RESET_VAL                  MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_RESET_MASK                         MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_READ_MASK                  MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_WRITE_MASK                         MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_PLLD_OUT2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_PLLD2_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_PLLD3_OUT0                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_PLLD4_OUT0                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_RANGE                        15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_RANGE                        14:14
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_SEL0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0_SOR2_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0                   MK_ADDR_CONST(0x1218000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SCR                       SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0_SOR2_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0                    MK_ADDR_CONST(0x1218004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SCR                        SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0_SOR2_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0                 MK_ADDR_CONST(0x1218008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SCR                     SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0                        MK_ADDR_CONST(0x121800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SCR                    SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0_SOR2_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0                     MK_ADDR_CONST(0x1218010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SCR                         SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0_SOR2_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0                   MK_ADDR_CONST(0x1218014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SCR                       SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0_SOR2_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0                    MK_ADDR_CONST(0x1218018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SCR                        SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0_SOR2_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0                     MK_ADDR_CONST(0x121801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SCR                         SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0_SOR2_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0                   MK_ADDR_CONST(0x1218020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SCR                       SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0                       MK_ADDR_CONST(0x1218024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SCR                   SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0_SOR2_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0                       MK_ADDR_CONST(0x1218028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SCR                   SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0_SOR2_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0                       MK_ADDR_CONST(0x121802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SCR                   SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0_SOR2_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0                    MK_ADDR_CONST(0x1218030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SCR                        SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0_SOR2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0                     MK_ADDR_CONST(0x1218034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SCR                         SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0_SOR2_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0                      MK_ADDR_CONST(0x121f000)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0                      MK_ADDR_CONST(0x121f004)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR2_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR3_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0                       MK_ADDR_CONST(0x1220000)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SCR                   SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_0_SWR_SOR3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0                   MK_ADDR_CONST(0x1220004)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SCR                       SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0_SET_SWR_SOR3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0                   MK_ADDR_CONST(0x1220008)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_SCR                       SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0_CLR_SWR_SOR3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0                   MK_ADDR_CONST(0x1221000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_SCR                       SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0_CLK_ENB_SOR3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0                       MK_ADDR_CONST(0x1221004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SCR                   SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0_SET_CLK_ENB_SOR3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0                       MK_ADDR_CONST(0x1221008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_SCR                   SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0_CLR_CLK_ENB_SOR3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0                   MK_ADDR_CONST(0x1222000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_SCR                       SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0_BOND_OUT_SOR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0                    MK_ADDR_CONST(0x1223000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SCR                        SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_RESET_VAL                  MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_RESET_MASK                         MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_READ_MASK                  MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_WRITE_MASK                         MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_PLLD_OUT2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_PLLD2_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_PLLD3_OUT0                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_PLLD4_OUT0                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_RANGE                        15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_RANGE                        14:14
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_SEL0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0_SOR3_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0                   MK_ADDR_CONST(0x1228000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SCR                       SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0_SOR3_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0                    MK_ADDR_CONST(0x1228004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SCR                        SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0_SOR3_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0                 MK_ADDR_CONST(0x1228008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SCR                     SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0                        MK_ADDR_CONST(0x122800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SCR                    SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0_SOR3_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0                     MK_ADDR_CONST(0x1228010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SCR                         SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0_SOR3_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0                   MK_ADDR_CONST(0x1228014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SCR                       SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0_SOR3_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0                    MK_ADDR_CONST(0x1228018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SCR                        SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0_SOR3_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0                     MK_ADDR_CONST(0x122801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SCR                         SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0_SOR3_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0                   MK_ADDR_CONST(0x1228020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SCR                       SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0                       MK_ADDR_CONST(0x1228024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SCR                   SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0_SOR3_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0                       MK_ADDR_CONST(0x1228028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SCR                   SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0_SOR3_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0                       MK_ADDR_CONST(0x122802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SCR                   SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0_SOR3_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0                    MK_ADDR_CONST(0x1228030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SCR                        SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0_SOR3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0                     MK_ADDR_CONST(0x1228034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SCR                         SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0_SOR3_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0                      MK_ADDR_CONST(0x122f000)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0                      MK_ADDR_CONST(0x122f004)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR3_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR0_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0                       MK_ADDR_CONST(0x3b0000)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SCR                   SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_RESET_VAL                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_RANGE                   1:1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0                   MK_ADDR_CONST(0x3b0004)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SCR                       SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_RESET_VAL                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_RANGE                   1:1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0                   MK_ADDR_CONST(0x3b0008)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_SCR                       SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_RESET_VAL                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_RANGE                   1:1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0                      MK_ADDR_CONST(0x3b000c)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SCR                  SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0                  MK_ADDR_CONST(0x3b0010)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SCR                      SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0                  MK_ADDR_CONST(0x3b0014)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_SCR                      SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0                     MK_ADDR_CONST(0x3b0018)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0                 MK_ADDR_CONST(0x3b001c)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0                 MK_ADDR_CONST(0x3b0020)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0                     MK_ADDR_CONST(0x3b0024)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0_SWR_DPAUX2_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0                 MK_ADDR_CONST(0x3b0028)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0_SET_SWR_DPAUX2_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0                 MK_ADDR_CONST(0x3b002c)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0_CLR_SWR_DPAUX2_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0                     MK_ADDR_CONST(0x3b0030)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0_SWR_DPAUX3_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0                 MK_ADDR_CONST(0x3b0034)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0_SET_SWR_DPAUX3_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0                 MK_ADDR_CONST(0x3b0038)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0_CLR_SWR_DPAUX3_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CEC_0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0                        MK_ADDR_CONST(0x3b003c)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SCR                    SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0                    MK_ADDR_CONST(0x3b0040)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SCR                        SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0                    MK_ADDR_CONST(0x3b0044)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_SCR                        SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0                   MK_ADDR_CONST(0x3b1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_SCR                       SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_RANGE                       1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0                       MK_ADDR_CONST(0x3b1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SCR                   SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_RANGE                       1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0                       MK_ADDR_CONST(0x3b1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_SCR                   SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_RANGE                       1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0                  MK_ADDR_CONST(0x3b100c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_SCR                      SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0                      MK_ADDR_CONST(0x3b1010)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SCR                  SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0                      MK_ADDR_CONST(0x3b1014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_SCR                  SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0                 MK_ADDR_CONST(0x3b1018)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0                     MK_ADDR_CONST(0x3b101c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0                     MK_ADDR_CONST(0x3b1020)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0                 MK_ADDR_CONST(0x3b1024)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0_CLK_ENB_DPAUX2_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0                     MK_ADDR_CONST(0x3b1028)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0_SET_CLK_ENB_DPAUX2_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0                     MK_ADDR_CONST(0x3b102c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0_CLR_CLK_ENB_DPAUX2_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0                 MK_ADDR_CONST(0x3b1030)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0_CLK_ENB_DPAUX3_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0                     MK_ADDR_CONST(0x3b1034)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0_SET_CLK_ENB_DPAUX3_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0                     MK_ADDR_CONST(0x3b1038)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0_CLR_CLK_ENB_DPAUX3_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0                    MK_ADDR_CONST(0x3b103c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_SCR                        SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0                        MK_ADDR_CONST(0x3b1040)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SCR                    SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0                        MK_ADDR_CONST(0x3b1044)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_SCR                    SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0                   MK_ADDR_CONST(0x3b2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_SCR                       SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_RANGE                      1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0                  MK_ADDR_CONST(0x3b2004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_SCR                      SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0                 MK_ADDR_CONST(0x3b2008)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0                 MK_ADDR_CONST(0x3b200c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0_BOND_OUT_DPAUX2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0                 MK_ADDR_CONST(0x3b2010)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_SCR                     SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0_BOND_OUT_DPAUX3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0                    MK_ADDR_CONST(0x3b2014)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_SCR                        SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0                    MK_ADDR_CONST(0x3b3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SCR                        SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_RESET_VAL                  MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_RESET_MASK                         MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_READ_MASK                  MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_WRITE_MASK                         MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLLD_OUT2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLLD2_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLLD3_OUT0                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLLD4_OUT0                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_RANGE                        15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_RANGE                        14:14
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0                     MK_ADDR_CONST(0x3b4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_SCR                         SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0x3b4004

// Reserved address 0x3b4008

// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0                   MK_ADDR_CONST(0x3b8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SCR                       SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0_SOR0_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0                    MK_ADDR_CONST(0x3b8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SCR                        SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0_SOR0_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0                 MK_ADDR_CONST(0x3b8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SCR                     SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0                        MK_ADDR_CONST(0x3b800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SCR                    SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0_SOR0_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0                     MK_ADDR_CONST(0x3b8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SCR                         SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0_SOR0_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0                   MK_ADDR_CONST(0x3b8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SCR                       SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0_SOR0_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0                    MK_ADDR_CONST(0x3b8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SCR                        SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0_SOR0_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0                     MK_ADDR_CONST(0x3b801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SCR                         SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0_SOR0_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0                   MK_ADDR_CONST(0x3b8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SCR                       SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0                       MK_ADDR_CONST(0x3b8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SCR                   SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0_SOR0_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0                       MK_ADDR_CONST(0x3b8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SCR                   SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0_SOR0_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0                       MK_ADDR_CONST(0x3b802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SCR                   SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0_SOR0_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0                    MK_ADDR_CONST(0x3b8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SCR                        SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0_SOR0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0                     MK_ADDR_CONST(0x3b8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SCR                         SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0_SOR0_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0                       MK_ADDR_CONST(0x3b8038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SCR                   SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0                        MK_ADDR_CONST(0x3b803c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SCR                    SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0                     MK_ADDR_CONST(0x3b8040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SCR                         SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0                    MK_ADDR_CONST(0x3b8044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SCR                        SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0                 MK_ADDR_CONST(0x3b8048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SCR                     SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0_SOR_SAFE_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0                       MK_ADDR_CONST(0x3b804c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SCR                   SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0                        MK_ADDR_CONST(0x3b8050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SCR                    SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0                 MK_ADDR_CONST(0x3b8054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SCR                     SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_RESET_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_READ_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_WRITE_MASK                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0_SOR_SAFE_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0                       MK_ADDR_CONST(0x3b8058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SCR                   SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_RESET_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_READ_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_WRITE_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0                   MK_ADDR_CONST(0x3b805c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SCR                       SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0                   MK_ADDR_CONST(0x3b8060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SCR                       SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0                   MK_ADDR_CONST(0x3b8064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SCR                       SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0_SOR_SAFE_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0                        MK_ADDR_CONST(0x3b8068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SCR                    SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0_SOR_SAFE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0                 MK_ADDR_CONST(0x3b806c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SCR                     SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0_SOR_SAFE_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0                      MK_ADDR_CONST(0x3bf000)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOR0_SCR_FMON_0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0                      MK_ADDR_CONST(0x3bf004)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR0_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0                  MK_ADDR_CONST(0x3bf008)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_SATA_0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0                       MK_ADDR_CONST(0x3c0000)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_RESET_VAL                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0                   MK_ADDR_CONST(0x3c0004)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_RESET_VAL                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0                   MK_ADDR_CONST(0x3c0008)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_RESET_VAL                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0                   MK_ADDR_CONST(0x3c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0                       MK_ADDR_CONST(0x3c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_WRITE_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0                       MK_ADDR_CONST(0x3c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0                   MK_ADDR_CONST(0x3c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_RANGE                        2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_RANGE                   1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0                        MK_ADDR_CONST(0x3c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_RESET_VAL                      MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0                    MK_ADDR_CONST(0x3c3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_RESET_VAL                  MK_MASK_CONST(0xc1000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_RESET_MASK                         MK_MASK_CONST(0xe10000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_READ_MASK                  MK_MASK_CONST(0xe10000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_WRITE_MASK                         MK_MASK_CONST(0xe10000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_RANGE                     24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_MSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_SATA_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0                     MK_ADDR_CONST(0x3c4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_HDA_0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0                        MK_ADDR_CONST(0x3d0000)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0                    MK_ADDR_CONST(0x3d0004)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0                    MK_ADDR_CONST(0x3d0008)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0                    MK_ADDR_CONST(0x3d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0                        MK_ADDR_CONST(0x3d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0                        MK_ADDR_CONST(0x3d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0                    MK_ADDR_CONST(0x3d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0                     MK_ADDR_CONST(0x3d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_RESET_VAL                   MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_PLLA_OUT0                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_CLK_S                   MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_CLK_M                   MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0                     MK_ADDR_CONST(0x3e0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0                 MK_ADDR_CONST(0x3e0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0                 MK_ADDR_CONST(0x3e0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0                     MK_ADDR_CONST(0x3e1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0                      MK_ADDR_CONST(0x3e2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLLC2_OUT0                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLLC3_OUT0                        MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_DFLL_SE                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0                       MK_ADDR_CONST(0x3e2004)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SCR                   0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_RESET_VAL                     MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_RESET_MASK                    MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_READ_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_WRITE_MASK                    MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_RANGE                   15:8
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0x3e2008

// Register CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0                     MK_ADDR_CONST(0x3f0000)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_SCR                         0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_RESET_VAL                   MK_MASK_CONST(0x190101)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_WRITE_MASK                  MK_MASK_CONST(0xffffff07)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_RANGE                       31:31
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_RANGE                        30:29
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_RANGE                        28:27
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                        23:16
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                      MK_MASK_CONST(0x19)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                        15:8
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_FIELD                    MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_RANGE                    7:3
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_RANGE                    2:2
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_RANGE                   1:1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_RANGE                   0:0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0                     MK_ADDR_CONST(0x3f0004)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_SCR                         0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_RESET_VAL                   MK_MASK_CONST(0x180150c0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                 MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                 11:0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                       MK_MASK_CONST(0xc0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                      12:12
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                        13:13
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                      14:14
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                        15:15
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                    16:16
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                      17:17
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_FIELD                        MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_RANGE                        26:18
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_DEFAULT_MASK                 MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                   31:27
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0                     MK_ADDR_CONST(0x3f0008)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_SCR                         0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_RESET_VAL                   MK_MASK_CONST(0x41318015)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_RESET_MASK                  MK_MASK_CONST(0x7fffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_READ_MASK                   MK_MASK_CONST(0x7fffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_WRITE_MASK                  MK_MASK_CONST(0x43ffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_RANGE                        30:30
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_SHIFT                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_RANGE                       29:26
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_LSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_RANGE                 25:25
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_MSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_RANGE                       24:24
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                    MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                    23:18
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                  MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_FIELD                       MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_RANGE                       17:6
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                     MK_MASK_CONST(0x600)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_RANGE                 5:5
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_RANGE                       4:4
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_RANGE                 3:3
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_RANGE                       2:2
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_RANGE                 1:1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_RANGE                       0:0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0                     MK_ADDR_CONST(0x3f000c)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_SCR                         0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_RESET_MASK                  MK_MASK_CONST(0xbfffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_READ_MASK                   MK_MASK_CONST(0xbfffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_WRITE_MASK                  MK_MASK_CONST(0xbfffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_FIELD                       MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_RANGE                       27:0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_DEFAULT_MASK                        MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_RANGE                 28:28
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_RANGE                    31:31
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_INIT_ENUM                        UTMIP_PLL_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_UTMIP_PLL_CLK_OUT_PTO_OBS                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTO_ROOT_CLK_SEL_UTMIP_PLL_CLK_OUT_PTO_DIV2                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0                      MK_ADDR_CONST(0x3f0010)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_SCR                  0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_RESET_VAL                    MK_MASK_CONST(0x600000f)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_RESET_MASK                   MK_MASK_CONST(0x8f0000ff)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x10000c0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x10000c7)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_READ_MASK                    MK_MASK_CONST(0x8f0000ff)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_WRITE_MASK                   MK_MASK_CONST(0x30000ff)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_RANGE                   31:31
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_RANGE                      27:26
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_INIT_ENUM                  SEQ_ON
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SEQ_OFF                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SEQ_ON                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SEQ_BUSY                   MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_RANGE                        25:25
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_INIT_ENUM                    SEQ_ON
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SEQ_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SEQ_ON                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_RANGE                     24:24
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_MSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_ENABLE                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE__PROD                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_RANGE                        7:7
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_SW_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE__PROD                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_RANGE                    6:6
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_SW_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET__PROD                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_RANGE                  5:5
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_RANGE                   4:4
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_RANGE                      3:3
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_RANGE                       2:2
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL__PROD                       MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_RANGE                    1:1
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE__PROD                    MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_RANGE                     0:0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL__PROD                     MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0                      MK_ADDR_CONST(0x3f0014)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_SCR                  0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_RESET_VAL                    MK_MASK_CONST(0x8012280f)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_RESET_MASK                   MK_MASK_CONST(0xff123fff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1003ff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_READ_MASK                    MK_MASK_CONST(0xff123fff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_WRITE_MASK                   MK_MASK_CONST(0xff123fff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_RANGE                 31:24
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_DEFAULT                       MK_MASK_CONST(0x80)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_RANGE                       20:20
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL__PROD                       MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_RANGE                      17:17
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_RANGE                       13:10
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_DEFAULT                     MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_FIELD                       MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_RANGE                       9:0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_DEFAULT_MASK                        MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY__PROD                       MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_APE_0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0                        MK_ADDR_CONST(0x400000)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_APE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0                    MK_ADDR_CONST(0x400004)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0                    MK_ADDR_CONST(0x400008)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0                    MK_ADDR_CONST(0x401000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0                        MK_ADDR_CONST(0x401004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0                        MK_ADDR_CONST(0x401008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0                        MK_ADDR_CONST(0x40100c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0                    MK_ADDR_CONST(0x401010)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0                    MK_ADDR_CONST(0x401014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0                   MK_ADDR_CONST(0x401018)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0                       MK_ADDR_CONST(0x40101c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0                       MK_ADDR_CONST(0x401020)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0                   MK_ADDR_CONST(0x401024)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0                       MK_ADDR_CONST(0x401028)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0                       MK_ADDR_CONST(0x40102c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0                    MK_ADDR_CONST(0x402000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0                        MK_ADDR_CONST(0x402004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0                   MK_ADDR_CONST(0x402008)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0                   MK_ADDR_CONST(0x40200c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0                 MK_ADDR_CONST(0x403000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SCR                     0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_RESET_VAL                       MK_MASK_CONST(0x700000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_RESET_MASK                      MK_MASK_CONST(0x20f00000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_READ_MASK                       MK_MASK_CONST(0x20f00000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_WRITE_MASK                      MK_MASK_CONST(0x20f00000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_RANGE                      29:29
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_RANGE                 23:20
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0                       MK_ADDR_CONST(0x403004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_RESET_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_READ_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_WRITE_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SPDIFIN                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S2                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S3                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S4                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S5                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_PLLA_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S6                    MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_APE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0                     MK_ADDR_CONST(0x403008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_RESET_VAL                   MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_PLLA_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_PLLA1_OUT1                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_CLK_M                   MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD2_BASE_0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0                 MK_ADDR_CONST(0x410000)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_RESET_VAL                       MK_MASK_CONST(0x42802)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_RESET_MASK                      MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_READ_MASK                       MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_WRITE_MASK                      MK_MASK_CONST(0xe7fdffff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_RANGE                        23:19
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_RANGE                        18:18
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_OFF                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_ON                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_RANGE                 16:16
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_FO                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_DEFAULT                      MK_MASK_CONST(0x28)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD2_MISC_0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0                 MK_ADDR_CONST(0x410004)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_RESET_VAL                       MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_RESET_MASK                      MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_READ_MASK                       MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_WRITE_MASK                      MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_INIT_ENUM                        PLLD2_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_PLLD2_CLK_OUT_PTO_OBS                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_PTO_ROOT_CLK_SEL_PLLD2_CLK_OUT_PTO_DIV2                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD2_MISC1_0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0                        MK_ADDR_CONST(0x410008)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_RESET_MASK                     MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_READ_MASK                      MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_WRITE_MASK                     MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_RANGE                       14:13
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_RANGE                       12:11
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_RANGE                      10:10
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_RANGE                       8:8
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_STOP_SYNCMUX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_RANGE                   7:7
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_SYNCMODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD2_MISC2_0
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0                        MK_ADDR_CONST(0x41000c)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_RESET_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_READ_MASK                      MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_WRITE_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_FIELD                      MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_RANGE                      27:0
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC2_0_PLLD2_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD2_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0                       MK_ADDR_CONST(0x410010)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_RESET_VAL                     MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_RESET_MASK                    MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_READ_MASK                     MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_RANGE                      25:23
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0                     MK_ADDR_CONST(0x410014)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0                     MK_ADDR_CONST(0x410018)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0                        MK_ADDR_CONST(0x420000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0                    MK_ADDR_CONST(0x420004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0                    MK_ADDR_CONST(0x420008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLREFE_BASE_0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0                       MK_ADDR_CONST(0x42000c)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_RESET_VAL                     MK_MASK_CONST(0x34104)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_RESET_MASK                    MK_MASK_CONST(0xfc1fffff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x7d0c)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_READ_MASK                     MK_MASK_CONST(0xfc1fffff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_WRITE_MASK                    MK_MASK_CONST(0xfc1fffff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_RANGE                 29:29
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_INIT_ENUM                     REF_ENABLE
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_REF_ENABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_REF_DISABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_RANGE                     28:27
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_SHIFT                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_RANGE                    26:26
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_LSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_FIELD                    MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_RANGE                    20:16
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_DEFAULT                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_DEFAULT                  MK_MASK_CONST(0x41)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_SW_DEFAULT                       MK_MASK_CONST(0x7d)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_SW_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN__PROD                    MK_MASK_CONST(0x7d)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_RANGE                    7:0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_DEFAULT                  MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_SW_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_SW_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM__PROD                    MK_MASK_CONST(0xc)


// Register CLK_RST_CONTROLLER_PLLREFE_MISC_0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0                       MK_ADDR_CONST(0x420010)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_RESET_VAL                     MK_MASK_CONST(0x41000000)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_RESET_MASK                    MK_MASK_CONST(0xff000000)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_READ_MASK                     MK_MASK_CONST(0xff000000)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_WRITE_MASK                    MK_MASK_CONST(0xe7000000)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_RANGE                   31:31
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_SHIFT                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_RANGE                       30:30
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_MSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_LSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_SHIFT                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_RANGE                     26:25
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_LSB                       MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_FO                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_VCO                       MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_RANGE                    24:24
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_MSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_ON                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLREFE_OUT_0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0                        MK_ADDR_CONST(0x420014)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_RESET_VAL                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_RESET_MASK                     MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_READ_MASK                      MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_WRITE_MASK                     MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_RANGE                     16:16
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_RANGE                       15:8
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN__PROD                       MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_RANGE                        0:0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_INIT_ENUM                    RESET_ENABLE
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_RESET_ENABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_RESET_DISABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLREFE_MISC1_0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0                      MK_ADDR_CONST(0x420018)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_RESET_MASK                   MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_READ_MASK                    MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_WRITE_MASK                   MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_FIELD                  MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_RANGE                  27:0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLREFE_MISC2_0
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0                      MK_ADDR_CONST(0x42001c)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_RESET_MASK                   MK_MASK_CONST(0x80007c00)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_READ_MASK                    MK_MASK_CONST(0x80007c00)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_WRITE_MASK                   MK_MASK_CONST(0x80007c00)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_RANGE                       31:31
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_INIT_ENUM                   PLLREFE_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_PLLREFE_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_PTO_ROOT_CLK_SEL_PLLREFE_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_RANGE                   14:13
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG14V_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_RANGE                   12:11
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_VREG10V_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_RANGE                  10:10
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC2_0_PLLREFE_BG_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0                        MK_ADDR_CONST(0x421000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC2_BASE_0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0                 MK_ADDR_CONST(0x430000)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_RESET_VAL                       MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_RESET_MASK                      MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_READ_MASK                       MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_WRITE_MASK                      MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_SHIFT                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_RANGE                        26:26
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_LSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_RANGE                        24:20
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_RANGE                        17:10
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_DEFAULT                      MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_0_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0                       MK_ADDR_CONST(0x430004)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_RESET_VAL                     MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_RESET_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_READ_MASK                     MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_WRITE_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_INIT_ENUM                      PLLC2_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_PLLC2_CLK_OUT_PTO_OBS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTO_ROOT_CLK_SEL_PLLC2_CLK_OUT_PTO_DIV2                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_SHIFT                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_RANGE                     30:30
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_MSB                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_LSB                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_RANGE                   19:4
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_DEFAULT                 MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_SW_DEFAULT                      MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_SW_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU__PROD                   MK_MASK_CONST(0x8000)

#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_RANGE                       3:3
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_FO                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_RANGE                 1:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_1_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0                       MK_ADDR_CONST(0x430008)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_RESET_VAL                     MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_RESET_MASK                    MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_READ_MASK                     MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_WRITE_MASK                    MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_OFF                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_ON                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_RANGE                        19:16
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_2_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0                       MK_ADDR_CONST(0x43000c)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_RESET_VAL                     MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_RESET_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_READ_MASK                     MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_WRITE_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_RANGE                        31:24
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_DEFAULT                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_RANGE                  23:16
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_DEFAULT                        MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_DEFAULT                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_SW_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM__PROD                        MK_MASK_CONST(0xf)

#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_RANGE                   4:4
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_RANGE                  2:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_3_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0                       MK_ADDR_CONST(0x430010)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_RESET_VAL                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_RESET_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_READ_MASK                     MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_WRITE_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_RANGE                      25:24
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_RANGE                     23:8
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_RANGE                      5:4
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_RANGE                        3:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_DEFAULT                      MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_4_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0                       MK_ADDR_CONST(0x430014)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_RESET_VAL                     MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_RESET_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_READ_MASK                     MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_WRITE_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_SHIFT                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_RANGE                     27:25
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_LSB                       MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_RANGE                     24:22
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_MSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_RANGE                     21:19
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_DEFAULT                   MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_RANGE                   18:16
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_DEFAULT                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC3_BASE_0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0                 MK_ADDR_CONST(0x440000)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_RESET_VAL                       MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_RESET_MASK                      MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_READ_MASK                       MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_WRITE_MASK                      MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_SHIFT                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_RANGE                        26:26
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_LSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_RANGE                        24:20
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_RANGE                        17:10
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_DEFAULT                      MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_0_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0                       MK_ADDR_CONST(0x440004)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_RESET_VAL                     MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_RESET_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_READ_MASK                     MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_WRITE_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_INIT_ENUM                      PLLC3_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_PLLC3_CLK_OUT_PTO_OBS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTO_ROOT_CLK_SEL_PLLC3_CLK_OUT_PTO_DIV2                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_SHIFT                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_RANGE                     30:30
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_MSB                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_LSB                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_RANGE                   19:4
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_DEFAULT                 MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_SW_DEFAULT                      MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_SW_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU__PROD                   MK_MASK_CONST(0x8000)

#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_RANGE                       3:3
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_FO                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_RANGE                 1:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_1_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0                       MK_ADDR_CONST(0x440008)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_RESET_VAL                     MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_RESET_MASK                    MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_READ_MASK                     MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_WRITE_MASK                    MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_OFF                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_ON                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_RANGE                        19:16
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_2_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0                       MK_ADDR_CONST(0x44000c)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_RESET_VAL                     MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_RESET_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_READ_MASK                     MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_WRITE_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_RANGE                        31:24
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_DEFAULT                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_RANGE                  23:16
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_DEFAULT                        MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_DEFAULT                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_SW_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM__PROD                        MK_MASK_CONST(0xf)

#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_RANGE                   4:4
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_RANGE                  2:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_3_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0                       MK_ADDR_CONST(0x440010)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_RESET_VAL                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_RESET_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_READ_MASK                     MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_WRITE_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_RANGE                      25:24
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_RANGE                     23:8
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_RANGE                      5:4
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_RANGE                        3:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_DEFAULT                      MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_4_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0                       MK_ADDR_CONST(0x440014)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_RESET_VAL                     MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_RESET_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_READ_MASK                     MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_WRITE_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_SHIFT                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_RANGE                     27:25
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_LSB                       MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_RANGE                     24:22
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_MSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_RANGE                     21:19
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_DEFAULT                   MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_RANGE                   18:16
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_DEFAULT                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_BASE_0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0                 MK_ADDR_CONST(0x12a0000)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_RESET_VAL                       MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_RESET_MASK                      MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_READ_MASK                       MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_WRITE_MASK                      MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_BYPASS_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_FREQ_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_SHIFT                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_RANGE                        26:26
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_LSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_RANGE                        24:20
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_RANGE                        17:10
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_DEFAULT                      MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_BASE_0_PLLCV_DIVM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_MISC_0_0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0                       MK_ADDR_CONST(0x12a0004)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_RESET_VAL                     MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_RESET_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_READ_MASK                     MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_WRITE_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_INIT_ENUM                      PLLCV_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_PLLCV_CLK_OUT_PTO_OBS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTO_ROOT_CLK_SEL_PLLCV_CLK_OUT_PTO_DIV2                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_SHIFT                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_RANGE                     30:30
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_MSB                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_LSB                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_RESET_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_RANGE                   19:4
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_DEFAULT                 MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_SW_DEFAULT                      MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_SW_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_EXT_FRU__PROD                   MK_MASK_CONST(0x8000)

#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_RANGE                       3:3
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_PTS_FO                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_RANGE                 1:0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_0_0_PLLCV_LOOP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_MISC_1_0
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0                       MK_ADDR_CONST(0x12a0008)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_RESET_VAL                     MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_RESET_MASK                    MK_MASK_CONST(0x800ffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_READ_MASK                     MK_MASK_CONST(0x800ffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_WRITE_MASK                    MK_MASK_CONST(0x800ffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_OFF                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_IDDQ_ON                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_1_0_PLLCV_DIVN_FRAC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_MISC_2_0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0                       MK_ADDR_CONST(0x12a000c)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_RESET_VAL                     MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_RESET_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_READ_MASK                     MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_WRITE_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_RANGE                        31:24
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_DEFAULT                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_LD_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_RANGE                  23:16
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_DEFAULT                        MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_PLL_FRUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_DEFAULT                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_SW_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_LD_MEM__PROD                        MK_MASK_CONST(0xf)

#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_RANGE                   4:4
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_DIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_RANGE                  2:0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_2_0_PLLCV_FLL_FRUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_MISC_3_0
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0                       MK_ADDR_CONST(0x12a0010)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_RESET_VAL                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_RESET_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_READ_MASK                     MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_WRITE_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_RANGE                      25:24
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_VREG10V_CTRL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_RANGE                     23:8
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_SETUP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_RANGE                      5:4
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_LDIV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_RANGE                        3:0
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_DEFAULT                      MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_3_0_PLLCV_PLL_LD_TOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_MISC_4_0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0                       MK_ADDR_CONST(0x12a0014)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_RESET_VAL                     MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_RESET_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_READ_MASK                     MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_WRITE_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_SEL_IREF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_SHIFT                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_RANGE                     27:25
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_LSB                       MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_LO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_RANGE                     24:22
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_MSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_HI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_RANGE                     21:19
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_DEFAULT                   MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_KP_STEP_TIMER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_RANGE                   18:16
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_DEFAULT                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_4_0_PLLCV_FRAC_STEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_MISC_5_0
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0                       MK_ADDR_CONST(0x12a0018)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_MISC_5_0_PLLCV_HPLL_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0                       MK_ADDR_CONST(0x12a001c)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_RESET_MASK                    MK_MASK_CONST(0xffffff81)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_READ_MASK                     MK_MASK_CONST(0xffffff81)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xffffff80)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_EN_SSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_RANGE                  30:15
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_RANGE                   14:11
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_LO_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_RANGE                   10:7
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSUG_HI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CFG_0_PLLCV_SSC_READY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0                     MK_ADDR_CONST(0x12a0020)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_RANGE                       31:16
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MAX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0_PLLCV_DIVN_FRAC_SSC_MIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0                     MK_ADDR_CONST(0x12a0024)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_RANGE                        31:24
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_STEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_RANGE                 23:8
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DLF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_RANGE                 7:0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0_PLLCV_SSC_DIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV2_BASE_0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0                        MK_ADDR_CONST(0x12b0000)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_RESET_VAL                      MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_RESET_MASK                     MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_READ_MASK                      MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_WRITE_MASK                     MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_BYPASS_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_REF_ENABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_REF_DIS_REF_DISABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_FREQ_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_LOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_RANGE                      24:20
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_RANGE                      17:10
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_DEFAULT                    MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_BASE_0_PLLCV2_DIVM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV2_MISC_0_0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0                      MK_ADDR_CONST(0x12b0004)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_RESET_VAL                    MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_RESET_MASK                   MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_READ_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_WRITE_MASK                   MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_INIT_ENUM                    PLLCV2_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_PLLCV2_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTO_ROOT_CLK_SEL_PLLCV2_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_RESET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_RANGE                 19:4
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_DEFAULT                       MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_SW_DEFAULT                    MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_SW_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_EXT_FRU__PROD                 MK_MASK_CONST(0x8000)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_RANGE                     3:3
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_PTS_FO                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_RANGE                       1:0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_0_0_PLLCV2_LOOP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV2_MISC_1_0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0                      MK_ADDR_CONST(0x12b0008)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_RESET_VAL                    MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_RESET_MASK                   MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_READ_MASK                    MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_WRITE_MASK                   MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_IDDQ_ON                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_RANGE                      19:16
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_EXT_SUBINT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_1_0_PLLCV2_DIVN_FRAC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV2_MISC_2_0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0                      MK_ADDR_CONST(0x12b000c)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_RESET_VAL                    MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_RESET_MASK                   MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_READ_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_WRITE_MASK                   MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_RANGE                      31:24
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_RANGE                        23:16
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_DEFAULT                      MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_PLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_LD_MEM__PROD                      MK_MASK_CONST(0xf)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_RANGE                 4:4
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_DIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_RANGE                        2:0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_DEFAULT                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_2_0_PLLCV2_FLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV2_MISC_3_0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0                      MK_ADDR_CONST(0x12b0010)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_RESET_VAL                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_RESET_MASK                   MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_READ_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_WRITE_MASK                   MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_RANGE                    25:24
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_VREG10V_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_RANGE                   23:8
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_SETUP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_RANGE                    5:4
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_LDIV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_RANGE                      3:0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_3_0_PLLCV2_PLL_LD_TOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV2_MISC_4_0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0                      MK_ADDR_CONST(0x12b0014)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_RESET_VAL                    MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_RESET_MASK                   MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_READ_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_WRITE_MASK                   MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_SEL_IREF_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_RANGE                   27:25
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_LO_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_RANGE                   24:22
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_MSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_HI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_RANGE                   21:19
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_DEFAULT                 MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_KP_STEP_TIMER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_RANGE                 18:16
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_DEFAULT                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV2_MISC_4_0_PLLCV2_FRAC_STEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV3_BASE_0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0                        MK_ADDR_CONST(0x12c0000)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_RESET_VAL                      MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_RESET_MASK                     MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_READ_MASK                      MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_WRITE_MASK                     MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_BYPASS_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_REF_ENABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_REF_DIS_REF_DISABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_FREQ_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_LOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_RANGE                      24:20
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_RANGE                      17:10
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_DEFAULT                    MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_BASE_0_PLLCV3_DIVM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV3_MISC_0_0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0                      MK_ADDR_CONST(0x12c0004)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_RESET_VAL                    MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_RESET_MASK                   MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_READ_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_WRITE_MASK                   MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_INIT_ENUM                    PLLCV3_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_PLLCV3_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTO_ROOT_CLK_SEL_PLLCV3_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_RESET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_RANGE                 19:4
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_DEFAULT                       MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_SW_DEFAULT                    MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_SW_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_EXT_FRU__PROD                 MK_MASK_CONST(0x8000)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_RANGE                     3:3
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_PTS_FO                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_RANGE                       1:0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_0_0_PLLCV3_LOOP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV3_MISC_1_0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0                      MK_ADDR_CONST(0x12c0008)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_RESET_VAL                    MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_RESET_MASK                   MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_READ_MASK                    MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_WRITE_MASK                   MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_IDDQ_ON                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_RANGE                      19:16
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_EXT_SUBINT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_1_0_PLLCV3_DIVN_FRAC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV3_MISC_2_0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0                      MK_ADDR_CONST(0x12c000c)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_RESET_VAL                    MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_RESET_MASK                   MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_READ_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_WRITE_MASK                   MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_RANGE                      31:24
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_RANGE                        23:16
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_DEFAULT                      MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_PLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_LD_MEM__PROD                      MK_MASK_CONST(0xf)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_RANGE                 4:4
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_DIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_RANGE                        2:0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_DEFAULT                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_2_0_PLLCV3_FLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV3_MISC_3_0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0                      MK_ADDR_CONST(0x12c0010)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_RESET_VAL                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_RESET_MASK                   MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_READ_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_WRITE_MASK                   MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_RANGE                    25:24
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_VREG10V_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_RANGE                   23:8
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_SETUP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_RANGE                    5:4
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_LDIV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_RANGE                      3:0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_3_0_PLLCV3_PLL_LD_TOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLCV3_MISC_4_0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0                      MK_ADDR_CONST(0x12c0014)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_RESET_VAL                    MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_RESET_MASK                   MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_READ_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_WRITE_MASK                   MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_SEL_IREF_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_RANGE                   27:25
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_LO_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_RANGE                   24:22
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_MSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_HI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_RANGE                   21:19
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_DEFAULT                 MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_KP_STEP_TIMER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_RANGE                 18:16
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_DEFAULT                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLCV3_MISC_4_0_PLLCV3_FRAC_STEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDP_BASE_0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0                 MK_ADDR_CONST(0x450000)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_RESET_VAL                       MK_MASK_CONST(0x42801)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_RESET_MASK                      MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x302a00)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0xf8ff00)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_READ_MASK                       MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_WRITE_MASK                      MK_MASK_CONST(0xe7fdffff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_RANGE                        23:19
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_SW_DEFAULT                   MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV__PROD                        MK_MASK_CONST(0x6)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_RANGE                        18:18
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_OFF                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_ON                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_RANGE                 16:16
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_FO                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_DEFAULT                      MK_MASK_CONST(0x28)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_SW_DEFAULT                   MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV__PROD                        MK_MASK_CONST(0x2a)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDP_MISC_0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0                 MK_ADDR_CONST(0x450004)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_RESET_VAL                       MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_RESET_MASK                      MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_READ_MASK                       MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_WRITE_MASK                      MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_INIT_ENUM                        PLLDP_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_PLLDP_CLK_OUT_PTO_OBS                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_PTO_ROOT_CLK_SEL_PLLDP_CLK_OUT_PTO_DIV2                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDP_MISC1_0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0                        MK_ADDR_CONST(0x450008)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_RESET_MASK                     MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_READ_MASK                      MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_WRITE_MASK                     MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_RANGE                       14:13
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_RANGE                       12:11
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_RANGE                      10:10
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_RANGE                       8:8
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_STOP_SYNCMUX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_RANGE                   7:7
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_SYNCMODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDP_MISC2_0
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0                        MK_ADDR_CONST(0x45000c)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_RESET_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_READ_MASK                      MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_WRITE_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_FIELD                      MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_RANGE                      27:0
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC2_0_PLLDP_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDP_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0                       MK_ADDR_CONST(0x450010)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_RESET_VAL                     MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_RESET_MASK                    MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_READ_MASK                     MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER__PROD                 MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_RANGE                      25:23
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0                     MK_ADDR_CONST(0x450014)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0xf600f147)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_SW_DEFAULT                        MK_MASK_CONST(0xf600)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_SW_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX__PROD                     MK_MASK_CONST(0xf600)

#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_SW_DEFAULT                        MK_MASK_CONST(0xf147)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN__PROD                     MK_MASK_CONST(0xf147)


// Register CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0                     MK_ADDR_CONST(0x450018)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x2f600)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_SW_DEFAULT                       MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP__PROD                    MK_MASK_CONST(0x2)

#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_SW_DEFAULT                    MK_MASK_CONST(0xf600)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN__PROD                 MK_MASK_CONST(0xf600)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0                  MK_ADDR_CONST(0x460000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0                      MK_ADDR_CONST(0x460004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0                      MK_ADDR_CONST(0x460008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLC4_BASE_0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0                 MK_ADDR_CONST(0x46000c)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_RESET_VAL                       MK_MASK_CONST(0xc2302)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_WRITE_MASK                      MK_MASK_CONST(0xe7ffffff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_RANGE                        23:19
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_RANGE                        18:18
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_OFF                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_ON                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_RANGE                 17:16
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_DEFAULT                      MK_MASK_CONST(0x23)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC4_MISC_0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0                 MK_ADDR_CONST(0x460010)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_RESET_VAL                       MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_RESET_MASK                      MK_MASK_CONST(0xc7ffffff)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_READ_MASK                       MK_MASK_CONST(0xc7ffffff)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_WRITE_MASK                      MK_MASK_CONST(0xc7ffffff)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_INIT_ENUM                        PLLC4_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_PLLC4_CLK_OUT_PTO_OBS                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_PTO_ROOT_CLK_SEL_PLLC4_CLK_OUT_PTO_DIV2                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_FIELD                       MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_RANGE                       23:0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_DEFAULT_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC4_MISC1_0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0                        MK_ADDR_CONST(0x460014)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_RESET_MASK                     MK_MASK_CONST(0x1ff80)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_READ_MASK                      MK_MASK_CONST(0x1ff80)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_WRITE_MASK                     MK_MASK_CONST(0x1ff80)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_RANGE                    16:15
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_PLLC4_OUT1                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_PLLC4_OUT2                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_PLLC4_VCO_DIV2                   MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_RANGE                       14:13
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_RANGE                       12:11
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_RANGE                      10:10
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_RANGE                 9:9
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_RANGE                       8:8
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_RANGE                   7:7
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC4_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0                       MK_ADDR_CONST(0x460018)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_RESET_VAL                     MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_RESET_MASK                    MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_READ_MASK                     MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_RANGE                      25:23
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0                     MK_ADDR_CONST(0x46001c)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0                     MK_ADDR_CONST(0x460020)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Reserved address 0x460024

// Reserved address 0x460028

// Reserved address 0x46002c

// Reserved address 0x460030

// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0                  MK_ADDR_CONST(0x461000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0                       MK_ADDR_CONST(0x470000)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_RESET_VAL                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0                   MK_ADDR_CONST(0x470004)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_RESET_VAL                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0                   MK_ADDR_CONST(0x470008)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_RESET_VAL                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0                   MK_ADDR_CONST(0x471000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0                       MK_ADDR_CONST(0x471004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0                       MK_ADDR_CONST(0x471008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0                   MK_ADDR_CONST(0x472000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_RANGE                    3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_RANGE                  2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_RANGE                   1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0                  MK_ADDR_CONST(0x473000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_CLK_M                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_PLLREFE_VCOCLK                    MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0                     MK_ADDR_CONST(0x473004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_CLK_M                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_PLLREFE_VCOCLK                  MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0                 MK_ADDR_CONST(0x473008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_RESET_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_READ_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_CLK_M                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_FO_48M                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_HSIC_480                        MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0                   MK_ADDR_CONST(0x47300c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_CLK_M                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_PLLREFE_VCOCLK                      MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0                 MK_ADDR_CONST(0x473010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_RESET_VAL                       MK_MASK_CONST(0x4000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_RESET_MASK                      MK_MASK_CONST(0xe70000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_READ_MASK                       MK_MASK_CONST(0xe70000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_WRITE_MASK                      MK_MASK_CONST(0xe70000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_CLK_M                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_PLLREFE_VCOCLK                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_CLK_S                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_HSIC_480                        MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_SHIFT                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_RANGE                     26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_LSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_RANGE                 25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_MSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_RANGE                 24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_MSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0                     MK_ADDR_CONST(0x474000)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0                    MK_ADDR_CONST(0x4d0000)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0                        MK_ADDR_CONST(0x4d0004)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0                        MK_ADDR_CONST(0x4d0008)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0                        MK_ADDR_CONST(0x4d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0                    MK_ADDR_CONST(0x4d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0                    MK_ADDR_CONST(0x4d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0                        MK_ADDR_CONST(0x4d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0                 MK_ADDR_CONST(0x4d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_RESET_MASK                      MK_MASK_CONST(0xf00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_READ_MASK                       MK_MASK_CONST(0xf00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_WRITE_MASK                      MK_MASK_CONST(0xf00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_PLLC2_OUT0                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_PLLC3_OUT0                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_DFLL_SE                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_RANGE                  28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_RANGE                  8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0                   MK_ADDR_CONST(0x4e0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0                       MK_ADDR_CONST(0x4e0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0                       MK_ADDR_CONST(0x4e0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0                   MK_ADDR_CONST(0x4e1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0                        MK_ADDR_CONST(0x4e2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_RESET_VAL                      MK_MASK_CONST(0xf0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_RESET_MASK                     MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_READ_MASK                      MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_WRITE_MASK                     MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x4f0000

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0                  MK_ADDR_CONST(0x500000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0                      MK_ADDR_CONST(0x500004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0                      MK_ADDR_CONST(0x500008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0                  MK_ADDR_CONST(0x501000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0                   MK_ADDR_CONST(0x502000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_PLLA_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_PLLA1_OUT1                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SYNC_CLK                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0                       MK_ADDR_CONST(0x503000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_RESET_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_READ_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_WRITE_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S2                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S3                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S4                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S5                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_PLLA_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S6                    MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CTRL_DMIC1_0
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0                 MK_ADDR_CONST(0x503004)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_SCR                     0
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_RANGE                 4:0
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC1_0_DMIC1_TRIMMER_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0                  MK_ADDR_CONST(0x510000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0                      MK_ADDR_CONST(0x510004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0                      MK_ADDR_CONST(0x510008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0                  MK_ADDR_CONST(0x511000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0                   MK_ADDR_CONST(0x512000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_PLLA_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_PLLA1_OUT1                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SYNC_CLK                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0                       MK_ADDR_CONST(0x513000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_RESET_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_READ_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_WRITE_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S2                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S3                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S4                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S5                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_PLLA_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S6                    MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CTRL_DMIC2_0
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0                 MK_ADDR_CONST(0x513004)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_SCR                     0
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_RANGE                 4:0
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC2_0_DMIC2_TRIMMER_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0                       MK_ADDR_CONST(0x520000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0                   MK_ADDR_CONST(0x520004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0                   MK_ADDR_CONST(0x520008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0                       MK_ADDR_CONST(0x521000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_SCR                   0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0                        MK_ADDR_CONST(0x522000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_PLLA1_OUT1                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C6_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0                       MK_ADDR_CONST(0x530000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SCR                   I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0                   MK_ADDR_CONST(0x530004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SCR                       I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0                   MK_ADDR_CONST(0x530008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_SCR                       I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0                   MK_ADDR_CONST(0x531000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_SCR                       I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0                       MK_ADDR_CONST(0x531004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SCR                   I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0                       MK_ADDR_CONST(0x531008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_SCR                   I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0                   MK_ADDR_CONST(0x532000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_SCR                       I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0                    MK_ADDR_CONST(0x533000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_SCR                        I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_RESET_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_READ_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_WRITE_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0                   MK_ADDR_CONST(0x538000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_SCR                       I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0_I2C6_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0                    MK_ADDR_CONST(0x538004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_SCR                        I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0_I2C6_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0                 MK_ADDR_CONST(0x538008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_SCR                     I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0                        MK_ADDR_CONST(0x53800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_SCR                    I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0_I2C6_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0                     MK_ADDR_CONST(0x538010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_SCR                         I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0_I2C6_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0                   MK_ADDR_CONST(0x538014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_SCR                       I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0_I2C6_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0                    MK_ADDR_CONST(0x538018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_SCR                        I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0_I2C6_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0                     MK_ADDR_CONST(0x53801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_SCR                         I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0_I2C6_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0                   MK_ADDR_CONST(0x538020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_SCR                       I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0                       MK_ADDR_CONST(0x538024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_SCR                   I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0_I2C6_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0                       MK_ADDR_CONST(0x538028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_SCR                   I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0_I2C6_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0                       MK_ADDR_CONST(0x53802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_SCR                   I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0_I2C6_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0                    MK_ADDR_CONST(0x538030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_SCR                        I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0_I2C6_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0                     MK_ADDR_CONST(0x538034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_SCR                         I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0_I2C6_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0                      MK_ADDR_CONST(0x53f000)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0                      MK_ADDR_CONST(0x53f004)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C6_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0x540000

// Register CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0                   MK_ADDR_CONST(0x550000)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0                       MK_ADDR_CONST(0x550004)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0                       MK_ADDR_CONST(0x550008)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0                      MK_ADDR_CONST(0x551000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0                  MK_ADDR_CONST(0x551004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0                  MK_ADDR_CONST(0x551008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0                       MK_ADDR_CONST(0x55100c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0                   MK_ADDR_CONST(0x551010)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0                   MK_ADDR_CONST(0x551014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0                      MK_ADDR_CONST(0x552000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0                       MK_ADDR_CONST(0x552004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_SCR                   0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0                       MK_ADDR_CONST(0x553000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_VIC_0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0                        MK_ADDR_CONST(0x560000)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SCR                    VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0                    MK_ADDR_CONST(0x560004)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SCR                        VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0                    MK_ADDR_CONST(0x560008)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_SCR                        VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0                    MK_ADDR_CONST(0x561000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_SCR                        VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0                        MK_ADDR_CONST(0x561004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SCR                    VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0                        MK_ADDR_CONST(0x561008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_SCR                    VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0                    MK_ADDR_CONST(0x562000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_SCR                        VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0                     MK_ADDR_CONST(0x563000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_SCR                         VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_RESET_VAL                   MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_RESET_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_READ_MASK                   MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_WRITE_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLLC2_OUT0                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLLC3_OUT0                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_CLK_M                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_DFLL_VIC                        MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_RANGE                      15:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0                      MK_ADDR_CONST(0x563004)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SCR                  0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_RESET_VAL                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_RESET_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_READ_MASK                    MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_WRITE_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_VIC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0                      MK_ADDR_CONST(0x564000)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0                    MK_ADDR_CONST(0x568000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_SCR                        VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0_VIC_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0                     MK_ADDR_CONST(0x568004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_SCR                         VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0_VIC_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0                  MK_ADDR_CONST(0x568008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_SCR                      VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0_VIC_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0                 MK_ADDR_CONST(0x56800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_SCR                     VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0_VIC_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0                      MK_ADDR_CONST(0x568010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_SCR                  VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0_VIC_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0                    MK_ADDR_CONST(0x568014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_SCR                        VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0_VIC_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0                     MK_ADDR_CONST(0x568018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_SCR                         VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0_VIC_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0                      MK_ADDR_CONST(0x56801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_SCR                  VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0_VIC_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0                    MK_ADDR_CONST(0x568020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_SCR                        VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0_VIC_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0                        MK_ADDR_CONST(0x568024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_SCR                    VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0_VIC_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0                        MK_ADDR_CONST(0x568028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_SCR                    VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0_VIC_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0                        MK_ADDR_CONST(0x56802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_SCR                    VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0_VIC_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0                     MK_ADDR_CONST(0x568030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_SCR                         VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0_VIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0                      MK_ADDR_CONST(0x568034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_SCR                  VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0_VIC_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0                       MK_ADDR_CONST(0x56f000)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SCR                   0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0                       MK_ADDR_CONST(0x56f004)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SCR                   0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x56f008

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0                        MK_ADDR_CONST(0x570000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0                    MK_ADDR_CONST(0x570004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0                    MK_ADDR_CONST(0x570008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0                        MK_ADDR_CONST(0x571000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0                 MK_ADDR_CONST(0x572000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_RESET_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x42)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_READ_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC__PROD                   MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x42)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR__PROD                       MK_MASK_CONST(0x42)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDEC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0                      MK_ADDR_CONST(0x580000)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0                  MK_ADDR_CONST(0x580004)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0                  MK_ADDR_CONST(0x580008)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0                  MK_ADDR_CONST(0x581000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0                      MK_ADDR_CONST(0x581004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0                      MK_ADDR_CONST(0x581008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0                  MK_ADDR_CONST(0x582000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0                   MK_ADDR_CONST(0x583000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLLC2_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLLC3_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_DFLL_NVDEC                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0                    MK_ADDR_CONST(0x583004)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_RESET_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_READ_MASK                  MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_WRITE_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0                    MK_ADDR_CONST(0x584000)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVJPG_0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0                      MK_ADDR_CONST(0x590000)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0                  MK_ADDR_CONST(0x590004)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0                  MK_ADDR_CONST(0x590008)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0                  MK_ADDR_CONST(0x591000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0                      MK_ADDR_CONST(0x591004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0                      MK_ADDR_CONST(0x591008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0                  MK_ADDR_CONST(0x592000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0                   MK_ADDR_CONST(0x593000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLLC2_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLLC3_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_DFLL_NVJPG                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0                    MK_ADDR_CONST(0x593004)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SCR                        0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_RESET_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_READ_MASK                  MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_WRITE_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVENC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0                      MK_ADDR_CONST(0x5a0000)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SCR                  NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0                  MK_ADDR_CONST(0x5a0004)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SCR                      NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0                  MK_ADDR_CONST(0x5a0008)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_SCR                      NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0                  MK_ADDR_CONST(0x5a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_SCR                      NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0                      MK_ADDR_CONST(0x5a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SCR                  NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0                      MK_ADDR_CONST(0x5a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_SCR                  NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0                  MK_ADDR_CONST(0x5a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_SCR                      NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0                   MK_ADDR_CONST(0x5a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_SCR                       NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLLC2_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLLC3_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_DFLL_NVENC                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0                    MK_ADDR_CONST(0x5a3004)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SCR                        NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_RESET_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_READ_MASK                  MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_WRITE_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0                    MK_ADDR_CONST(0x5a4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_SCR                        NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0                  MK_ADDR_CONST(0x5a8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_SCR                      NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0_NVENC_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0                   MK_ADDR_CONST(0x5a8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_SCR                       NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0_NVENC_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0                        MK_ADDR_CONST(0x5a8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_SCR                    NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0                       MK_ADDR_CONST(0x5a800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_SCR                   NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_RESET_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_READ_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_WRITE_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0_NVENC_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0                    MK_ADDR_CONST(0x5a8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_SCR                        NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0_NVENC_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0                  MK_ADDR_CONST(0x5a8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_SCR                      NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_READ_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0_NVENC_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0                   MK_ADDR_CONST(0x5a8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_SCR                       NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0_NVENC_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0                    MK_ADDR_CONST(0x5a801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_SCR                        NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_RESET_MASK                         MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_READ_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_WRITE_MASK                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0_NVENC_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0                  MK_ADDR_CONST(0x5a8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_SCR                      NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_RESET_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_READ_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_WRITE_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0                      MK_ADDR_CONST(0x5a8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_SCR                  NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0_NVENC_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0                      MK_ADDR_CONST(0x5a8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_SCR                  NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0_NVENC_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0                      MK_ADDR_CONST(0x5a802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_SCR                  NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0_NVENC_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0                   MK_ADDR_CONST(0x5a8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_SCR                       NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0_NVENC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0                    MK_ADDR_CONST(0x5a8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_SCR                        NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0_NVENC_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0                     MK_ADDR_CONST(0x5af000)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0                     MK_ADDR_CONST(0x5af004)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA1_BASE_0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0                 MK_ADDR_CONST(0x5b0000)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_RESET_VAL                       MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_RESET_MASK                      MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_READ_MASK                       MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_WRITE_MASK                      MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_SHIFT                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_RANGE                        26:26
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_LSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_RANGE                        24:20
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_RANGE                        17:10
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_DEFAULT                      MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_0_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0                       MK_ADDR_CONST(0x5b0004)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_RESET_VAL                     MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_RESET_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_READ_MASK                     MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_WRITE_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_INIT_ENUM                      PLLA1_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_PLLA1_CLK_OUT_PTO_OBS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTO_ROOT_CLK_SEL_PLLA1_CLK_OUT_PTO_DIV2                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_SHIFT                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_RANGE                     30:30
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_MSB                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_LSB                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_RANGE                   19:4
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_DEFAULT                 MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_SW_DEFAULT                      MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_SW_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU__PROD                   MK_MASK_CONST(0x8000)

#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_RANGE                       3:3
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_FO                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_RANGE                 1:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_1_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0                       MK_ADDR_CONST(0x5b0008)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_RESET_VAL                     MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_RESET_MASK                    MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_READ_MASK                     MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_WRITE_MASK                    MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_OFF                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_ON                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_RANGE                        19:16
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_2_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0                       MK_ADDR_CONST(0x5b000c)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_RESET_VAL                     MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_RESET_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_READ_MASK                     MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_WRITE_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_RANGE                        31:24
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_DEFAULT                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_RANGE                  23:16
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_DEFAULT                        MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_DEFAULT                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_SW_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM__PROD                        MK_MASK_CONST(0xf)

#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_RANGE                   4:4
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_RANGE                  2:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_3_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0                       MK_ADDR_CONST(0x5b0010)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_RESET_VAL                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_RESET_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_READ_MASK                     MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_WRITE_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_RANGE                      25:24
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_RANGE                     23:8
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_RANGE                      5:4
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_RANGE                        3:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_DEFAULT                      MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_4_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0                       MK_ADDR_CONST(0x5b0014)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_RESET_VAL                     MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_RESET_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_READ_MASK                     MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_WRITE_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF__PROD                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_SHIFT                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_RANGE                     27:25
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_LSB                       MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_RANGE                     24:22
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_MSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_RANGE                     21:19
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_DEFAULT                   MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_RANGE                   18:16
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_DEFAULT                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLA1_OUT1_0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0                 MK_ADDR_CONST(0x5b0018)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_RESET_VAL                       MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_RESET_MASK                      MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_READ_MASK                       MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_WRITE_MASK                      MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_RANGE                        16:16
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_RANGE                  1:1
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_INIT_ENUM                       RESET_ENABLE
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_RESET_ENABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_RESET_DISABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_QSPI0_0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0                      MK_ADDR_CONST(0x5c0000)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_0_SWR_QSPI0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0                  MK_ADDR_CONST(0x5c0004)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0_SET_SWR_QSPI0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0                  MK_ADDR_CONST(0x5c0008)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0_CLR_SWR_QSPI0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0                  MK_ADDR_CONST(0x5c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0_CLK_ENB_QSPI0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0                      MK_ADDR_CONST(0x5c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0_SET_CLK_ENB_QSPI0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0                      MK_ADDR_CONST(0x5c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0_CLR_CLK_ENB_QSPI0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0                  MK_ADDR_CONST(0x5c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0_BOND_OUT_QSPI0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0                   MK_ADDR_CONST(0x5c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_RESET_MASK                        MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_READ_MASK                         MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_WRITE_MASK                        MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_PLLC2_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_PLLC3_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_PLLC4_MUXED                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_RANGE                  8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIV2_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0_QSPI0_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0                  MK_ADDR_CONST(0x5e0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_RANGE                   0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0                      MK_ADDR_CONST(0x5e0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_RANGE                   0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0                      MK_ADDR_CONST(0x5e0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_RANGE                   0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0                  MK_ADDR_CONST(0x5e1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_RANGE                  0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0                   MK_ADDR_CONST(0x5e2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR__PROD                   MK_MASK_CONST(0x6)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0                     MK_ADDR_CONST(0x5f0000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_RESET_VAL                   MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_RESET_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_READ_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_WRITE_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_RANGE                  8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0                   MK_ADDR_CONST(0x5f0004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_RESET_VAL                         MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_RESET_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_READ_MASK                         MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_WRITE_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_RANGE                        8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0                   MK_ADDR_CONST(0x5f0008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_RESET_VAL                         MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_RESET_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_READ_MASK                         MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_WRITE_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_RANGE                        8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0                   MK_ADDR_CONST(0x5f000c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_RESET_VAL                         MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_RESET_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_READ_MASK                         MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_WRITE_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_RANGE                        8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_CE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0_PEX_USB_PAD_PLL3_MGMT_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0                   MK_ADDR_CONST(0x5f0010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_RESET_VAL                         MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_RESET_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_READ_MASK                         MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_WRITE_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_RANGE                        8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_CE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0_PEX_USB_PAD_PLL2_MGMT_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0                   MK_ADDR_CONST(0x600000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0                       MK_ADDR_CONST(0x600004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0                       MK_ADDR_CONST(0x600008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0                   MK_ADDR_CONST(0x601000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0                    MK_ADDR_CONST(0x602000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSECB_0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0                      MK_ADDR_CONST(0x610000)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0                  MK_ADDR_CONST(0x610004)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0                  MK_ADDR_CONST(0x610008)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0                  MK_ADDR_CONST(0x611000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0                      MK_ADDR_CONST(0x611004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0                      MK_ADDR_CONST(0x611008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0                  MK_ADDR_CONST(0x612000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0                   MK_ADDR_CONST(0x613000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLLC2_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLLC3_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_DFLL_TSECB                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0                    MK_ADDR_CONST(0x613004)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SCR                        0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_RESET_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_READ_MASK                  MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_WRITE_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_STRAP_TSECB_0
#define CLK_RST_CONTROLLER_STRAP_TSECB_0                        MK_ADDR_CONST(0x614000)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_SCR                    0
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_SHIFT)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_RANGE                     0:0
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_STRAP_TSECB_0_TSECB_KEYSEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_ADSP_0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0                       MK_ADDR_CONST(0x620000)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_RESET_VAL                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_RANGE                    7:7
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPCSITEPTM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_RANGE                        6:6
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_RANGE                 5:5
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_RANGE                 4:4
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_RANGE                      2:2
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0                   MK_ADDR_CONST(0x620004)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_RESET_VAL                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_RANGE                    7:7
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPCSITEPTM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_RANGE                        6:6
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_RANGE                 5:5
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_RANGE                 4:4
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_RANGE                      2:2
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0                   MK_ADDR_CONST(0x620008)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_RESET_VAL                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_RANGE                    7:7
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPCSITEPTM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_RANGE                        6:6
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_RANGE                 5:5
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_RANGE                 4:4
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_RANGE                      2:2
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0                   MK_ADDR_CONST(0x621000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_RESET_MASK                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_READ_MASK                         MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_WRITE_MASK                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0                       MK_ADDR_CONST(0x621004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_RESET_MASK                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_READ_MASK                     MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_WRITE_MASK                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0                       MK_ADDR_CONST(0x621008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_RESET_MASK                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_READ_MASK                     MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0                   MK_ADDR_CONST(0x622000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_RESET_MASK                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_READ_MASK                         MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_WRITE_MASK                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_RANGE                   2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0                  MK_ADDR_CONST(0x623000)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_SCR                      0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_RESET_VAL                        MK_MASK_CONST(0x10004444)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_RESET_MASK                       MK_MASK_CONST(0xfc00ffff)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_READ_MASK                        MK_MASK_CONST(0xfc00ffff)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_WRITE_MASK                       MK_MASK_CONST(0xfc00ffff)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_RANGE                 31:28
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_STDBY                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_IDLE                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_RUN                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_IRQ                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_FIQ                   MK_ENUM_CONST(8)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_RANGE                      27:27
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_RANGE                      26:26
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_RANGE                 15:12
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_DEFAULT                       MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA1_OUT0                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLP_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA_OUT                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_CLK_M                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA1_OUT_LJ                  MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA_OUT_LJ                   MK_ENUM_CONST(15)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_RANGE                 11:8
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_DEFAULT                       MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA1_OUT0                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLP_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA_OUT                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_CLK_M                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA1_OUT_LJ                  MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA_OUT_LJ                   MK_ENUM_CONST(15)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_RANGE                 7:4
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_DEFAULT                       MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA1_OUT0                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLP_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA_OUT                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_CLK_M                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA1_OUT_LJ                  MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA_OUT_LJ                   MK_ENUM_CONST(15)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_RANGE                        3:0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_DEFAULT                      MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA1_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLP_OUT0                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA_OUT0                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA_OUT                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_CLK_M                        MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA1_OUT_LJ                 MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA_OUT_LJ                  MK_ENUM_CONST(15)


// Register CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0                 MK_ADDR_CONST(0x623004)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SCR                     0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_RESET_MASK                      MK_MASK_CONST(0x96ffffff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_READ_MASK                       MK_MASK_CONST(0x96ffffff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_WRITE_MASK                      MK_MASK_CONST(0x96ffffff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_RANGE                   28:28
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_SHIFT                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_RANGE                   26:26
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_LSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_RANGE                   25:25
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_MSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_RANGE                  23:16
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x630000

// Reserved address 0x640000

// Register CLK_RST_CONTROLLER_RST_DEV_MPHY_0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0                       MK_ADDR_CONST(0x650000)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_RESET_VAL                     MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_RESET_MASK                    MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_READ_MASK                     MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_WRITE_MASK                    MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_RANGE                     29:29
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_RANGE                    16:16
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_RANGE                      9:9
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_RANGE                      8:8
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0                   MK_ADDR_CONST(0x650004)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_RESET_VAL                         MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_RESET_MASK                        MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_READ_MASK                         MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_WRITE_MASK                        MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_RANGE                     29:29
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_RANGE                    16:16
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_RANGE                      9:9
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_RANGE                      8:8
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0                   MK_ADDR_CONST(0x650008)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_RESET_VAL                         MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_RESET_MASK                        MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_READ_MASK                         MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_RANGE                     29:29
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_RANGE                    16:16
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_RANGE                      9:9
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_RANGE                      8:8
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0                   MK_ADDR_CONST(0x651000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_RESET_MASK                        MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_READ_MASK                         MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_WRITE_MASK                        MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_RANGE                 31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_RANGE                    30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_RANGE                 29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_RANGE                      15:15
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_RANGE                 4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0                       MK_ADDR_CONST(0x651004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_RESET_MASK                    MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_READ_MASK                     MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_WRITE_MASK                    MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_RANGE                 31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_RANGE                    30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_RANGE                 29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_RANGE                      15:15
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_RANGE                 4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0                       MK_ADDR_CONST(0x651008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_RESET_MASK                    MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_READ_MASK                     MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_RANGE                 31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_RANGE                    30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_RANGE                 29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_RANGE                      15:15
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_RANGE                 4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0                   MK_ADDR_CONST(0x652000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_RESET_MASK                        MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_READ_MASK                         MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_WRITE_MASK                        MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_RANGE                        31:31
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_RANGE                   30:30
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_RANGE                        29:29
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_RANGE                     15:15
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_RANGE                     7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_RANGE                        4:4
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_RANGE                    3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_RANGE                    0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0                     MK_ADDR_CONST(0x653000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_RESET_VAL                   MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0                        MK_ADDR_CONST(0x653004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_RESET_VAL                      MK_MASK_CONST(0x4a)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x4a)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0                     MK_ADDR_CONST(0x653008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0                      MK_ADDR_CONST(0x65300c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_RESET_VAL                    MK_MASK_CONST(0x26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0                      MK_ADDR_CONST(0x653010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_RESET_VAL                    MK_MASK_CONST(0x76)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x76)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_MPHY_MISC_0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0                      MK_ADDR_CONST(0x654000)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0                     MK_ADDR_CONST(0x655000)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0                   MK_ADDR_CONST(0x656000)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SCR                       0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_RESET_MASK                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_READ_MASK                         MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_WRITE_MASK                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_RANGE                    19:19
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_RANGE                     18:18
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_HS_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_RANGE                 17:17
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_RANGE                  16:9
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_LS_3XBIT_CLK_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_RANGE                  8:8
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0_SW_MPHY_L0_TX_HS_SYMB_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0                   MK_ADDR_CONST(0x657000)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SCR                       0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_RESET_MASK                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_READ_MASK                         MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_WRITE_MASK                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_RANGE                    19:19
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_RANGE                     18:18
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_HS_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_RANGE                   17:17
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_RANGE                    16:9
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_LS_BIT_CLK_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_RANGE                  8:8
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0_SW_MPHY_L0_RX_HS_SYMB_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVCSI_BASE_0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0                      MK_ADDR_CONST(0x660000)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_RESET_VAL                    MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_RESET_MASK                   MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_READ_MASK                    MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_WRITE_MASK                   MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_REF_ENABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_REF_DISABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_RANGE                     27:27
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_SHIFT                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_RANGE                  26:26
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_LSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_RANGE                  24:20
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_RANGE                  17:10
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_DEFAULT                        MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0                    MK_ADDR_CONST(0x660004)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_RESET_VAL                  MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_RESET_MASK                         MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_READ_MASK                  MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_WRITE_MASK                         MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_INIT_ENUM                        PLLNVCSI_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_PLLNVCSI_CLK_OUT_PTO_OBS                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTO_ROOT_CLK_SEL_PLLNVCSI_CLK_OUT_PTO_DIV2                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_SHIFT                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_RANGE                       30:30
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_MSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_LSB                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_RANGE                     19:4
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_DEFAULT                   MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_RANGE                 3:3
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_FO                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_RANGE                   1:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0                    MK_ADDR_CONST(0x660008)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_RESET_VAL                  MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_RESET_MASK                         MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_READ_MASK                  MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_WRITE_MASK                         MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_OFF                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_ON                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_RANGE                  19:16
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0                    MK_ADDR_CONST(0x66000c)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_RESET_VAL                  MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_RESET_MASK                         MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_READ_MASK                  MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_WRITE_MASK                         MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_RANGE                  31:24
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_DEFAULT                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_RANGE                    23:16
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_DEFAULT                  MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_RANGE                     4:4
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_RANGE                    2:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_DEFAULT                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0                    MK_ADDR_CONST(0x660010)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_RESET_VAL                  MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_RESET_MASK                         MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_READ_MASK                  MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_WRITE_MASK                         MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_RANGE                        25:24
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_RANGE                       23:8
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_RANGE                        5:4
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_RANGE                  3:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_DEFAULT                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0                    MK_ADDR_CONST(0x660014)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_RESET_VAL                  MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_RESET_MASK                         MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_READ_MASK                  MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_WRITE_MASK                         MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF__PROD                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_SHIFT                       MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_RANGE                       27:25
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_LSB                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_RANGE                       24:22
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_RANGE                       21:19
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_DEFAULT                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_RANGE                     18:16
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_DEFAULT                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_DEFAULT                 MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0                    MK_ADDR_CONST(0x670000)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_RESET_VAL                  MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_RESET_MASK                         MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_READ_MASK                  MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_WRITE_MASK                         MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_REF_ENABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_REF_DISABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_RANGE                      24:20
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_RANGE                      17:10
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_DEFAULT                    MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0                  MK_ADDR_CONST(0x670004)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_RESET_VAL                        MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_RESET_MASK                       MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_READ_MASK                        MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_WRITE_MASK                       MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_INIT_ENUM                    PLLDISPHUB_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_PLLDISPHUB_CLK_OUT_PTO_OBS                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTO_ROOT_CLK_SEL_PLLDISPHUB_CLK_OUT_PTO_DIV2                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_RANGE                 19:4
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_DEFAULT                       MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_RANGE                     3:3
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_FO                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_RANGE                       1:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0                  MK_ADDR_CONST(0x670008)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_RESET_VAL                        MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_RESET_MASK                       MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_READ_MASK                        MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_WRITE_MASK                       MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_ON                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_RANGE                      19:16
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0                  MK_ADDR_CONST(0x67000c)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_RESET_VAL                        MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_RESET_MASK                       MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_READ_MASK                        MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_WRITE_MASK                       MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_RANGE                      31:24
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_RANGE                        23:16
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_DEFAULT                      MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_RANGE                 4:4
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_RANGE                        2:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_DEFAULT                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0                  MK_ADDR_CONST(0x670010)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_RESET_VAL                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_RESET_MASK                       MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_READ_MASK                        MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_WRITE_MASK                       MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_RANGE                    25:24
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_RANGE                   23:8
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_RANGE                    5:4
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_RANGE                      3:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0                  MK_ADDR_CONST(0x670014)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_RESET_VAL                        MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_RESET_MASK                       MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_READ_MASK                        MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_WRITE_MASK                       MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF__PROD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_RANGE                   27:25
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_RANGE                   24:22
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_MSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_RANGE                   21:19
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_DEFAULT                 MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_RANGE                 18:16
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_DEFAULT                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD3_BASE_0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0                 MK_ADDR_CONST(0x680000)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_RESET_VAL                       MK_MASK_CONST(0x42801)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_RESET_MASK                      MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_READ_MASK                       MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_WRITE_MASK                      MK_MASK_CONST(0xe7fdffff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_RANGE                        23:19
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_RANGE                        18:18
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_OFF                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_ON                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_RANGE                 16:16
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_FO                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_DEFAULT                      MK_MASK_CONST(0x28)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD3_MISC_0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0                 MK_ADDR_CONST(0x680004)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_RESET_VAL                       MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_RESET_MASK                      MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_READ_MASK                       MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_WRITE_MASK                      MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_INIT_ENUM                        PLLD3_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_PLLD3_CLK_OUT_PTO_OBS                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_PTO_ROOT_CLK_SEL_PLLD3_CLK_OUT_PTO_DIV2                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD3_MISC1_0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0                        MK_ADDR_CONST(0x680008)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_RESET_MASK                     MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_READ_MASK                      MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_WRITE_MASK                     MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_RANGE                       14:13
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_RANGE                       12:11
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_RANGE                      10:10
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_RANGE                       8:8
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_STOP_SYNCMUX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_RANGE                   7:7
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_SYNCMODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD3_MISC2_0
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0                        MK_ADDR_CONST(0x68000c)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_RESET_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_READ_MASK                      MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_WRITE_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_FIELD                      MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_RANGE                      27:0
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC2_0_PLLD3_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD3_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0                       MK_ADDR_CONST(0x680010)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_RESET_VAL                     MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_RESET_MASK                    MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_READ_MASK                     MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_RANGE                      25:23
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0                     MK_ADDR_CONST(0x680014)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0                     MK_ADDR_CONST(0x680018)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD4_BASE_0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0                 MK_ADDR_CONST(0x1200000)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_RESET_VAL                       MK_MASK_CONST(0x42801)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_RESET_MASK                      MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_READ_MASK                       MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_WRITE_MASK                      MK_MASK_CONST(0xe7fdffff)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_BYPASS_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_REF_ENABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_DIS_REF_DISABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_FREQLOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_REF_SRC_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_LOCK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_RANGE                        23:19
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_RANGE                        18:18
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_OFF                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_IDDQ_ON                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_RANGE                 16:16
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_PTS_FO                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_DEFAULT                      MK_MASK_CONST(0x28)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_NDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_BASE_0_PLLD4_MDIV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD4_MISC_0
#define CLK_RST_CONTROLLER_PLLD4_MISC_0                 MK_ADDR_CONST(0x1200004)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_RESET_VAL                       MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_RESET_MASK                      MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_READ_MASK                       MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_WRITE_MASK                      MK_MASK_CONST(0xc7000000)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_INIT_ENUM                        PLLD4_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_PLLD4_CLK_OUT_PTO_OBS                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_PTO_ROOT_CLK_SEL_PLLD4_CLK_OUT_PTO_DIV2                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_EN_LCKDET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_SHIFT                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_LSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KCP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC_0_PLLD4_KVCO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD4_MISC1_0
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0                        MK_ADDR_CONST(0x1200008)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_RESET_MASK                     MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_READ_MASK                      MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_WRITE_MASK                     MK_MASK_CONST(0x7d80)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_RANGE                       14:13
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG14V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_RANGE                       12:11
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_VREG10V_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_RANGE                      10:10
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_BG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_RANGE                       8:8
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_STOP_SYNCMUX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_RANGE                   7:7
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC1_0_PLLD4_SYNCMODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD4_MISC2_0
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0                        MK_ADDR_CONST(0x120000c)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_RESET_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_READ_MASK                      MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_WRITE_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_FIELD                      MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_RANGE                      27:0
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_MISC2_0_PLLD4_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD4_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0                       MK_ADDR_CONST(0x1200010)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_RESET_VAL                     MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_RESET_MASK                    MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_READ_MASK                     MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SDM_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_SSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_EN_DITHER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_RANGE                      25:23
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CFG_0_PLLD4_SDM_TEST_OUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0                     MK_ADDR_CONST(0x1200014)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MAX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0_PLLD4_SDM_SSC_MIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0                     MK_ADDR_CONST(0x1200018)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_SSC_STEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0_PLLD4_SDM_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSB_BASE_0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0                        MK_ADDR_CONST(0x690000)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_RESET_VAL                      MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_RESET_MASK                     MK_MASK_CONST(0xec10ffff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_READ_MASK                      MK_MASK_CONST(0xec10ffff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_WRITE_MASK                     MK_MASK_CONST(0xe010ffff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_RANGE                 31:31
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_REF_ENABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_REF_DISABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_SHIFT                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_RANGE                 26:26
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_LSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_RANGE                      20:20
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_DEFAULT                    MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSB_MISC1_0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0                       MK_ADDR_CONST(0x690004)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_RESET_MASK                    MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_READ_MASK                     MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_WRITE_MASK                    MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_RANGE                       31:31
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_SW_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_CLAMP_PH90__PROD                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_FIELD                    MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_RANGE                    27:0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_DEFAULT_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSB_MISC2_0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0                       MK_ADDR_CONST(0x690008)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_RESET_VAL                     MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_RESET_MASK                    MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_READ_MASK                     MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_WRITE_MASK                    MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_RANGE                 31:31
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_INIT_ENUM                     PLLMSB_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_PLLMSB_CLK_OUT_PTO_OBS                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTO_ROOT_CLK_SEL_PLLMSB_CLK_OUT_PTO_DIV2                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_RANGE                     17:16
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_RANGE                     15:14
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_RANGE                 13:13
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_RANGE                  12:12
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_RANGE                    11:11
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_RANGE                       10:10
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_RANGE                      9:8
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_FO                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_RANGE                     5:5
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_RANGE                        4:4
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_RANGE                    3:3
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_RANGE                      2:1
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSBB_BASE_0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0                       MK_ADDR_CONST(0x69000c)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_RESET_VAL                     MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_RESET_MASK                    MK_MASK_CONST(0x4c10ffff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_READ_MASK                     MK_MASK_CONST(0x4c10ffff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_WRITE_MASK                    MK_MASK_CONST(0x4010ffff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_SHIFT                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_RANGE                       26:26
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_LSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_RANGE                    20:20
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_DEFAULT                  MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_RANGE                    7:0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_DEFAULT                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSBB_MISC1_0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0                      MK_ADDR_CONST(0x690010)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_RESET_VAL                    MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_RANGE                       31:31
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_INIT_ENUM                   PLLMSBB_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_PLLMSBB_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_PTO_ROOT_CLK_SEL_PLLMSBB_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_RANGE                      28:28
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_FIELD                  MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_RANGE                  27:0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0                      MK_ADDR_CONST(0x690014)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_RESET_VAL                    MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_RESET_MASK                   MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_READ_MASK                    MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_RANGE                      29:29
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_RANGE                       28:28
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_RANGE                       27:27
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_RANGE                    25:23
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0                    MK_ADDR_CONST(0x690018)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_RANGE                   31:16
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0                    MK_ADDR_CONST(0x69001c)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_RANGE                  31:16
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0                     MK_ADDR_CONST(0x690020)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_RESET_VAL                   MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_RESET_MASK                  MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_READ_MASK                   MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_WRITE_MASK                  MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_RANGE                    29:29
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_RANGE                     28:28
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_RANGE                     27:27
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0                   MK_ADDR_CONST(0x690024)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_RANGE                 31:16
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0                   MK_ADDR_CONST(0x690028)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_RANGE                        31:16
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0                    MK_ADDR_CONST(0x6a0000)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SCR                        AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_RESET_VAL                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_RESET_MASK                         MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_READ_MASK                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_WRITE_MASK                         MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0                        MK_ADDR_CONST(0x6a0004)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SCR                    AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_RESET_VAL                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_RESET_MASK                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_READ_MASK                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_WRITE_MASK                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0                        MK_ADDR_CONST(0x6a0008)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_SCR                    AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_RESET_VAL                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_RESET_MASK                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_READ_MASK                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0                        MK_ADDR_CONST(0x6a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_SCR                    AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0                    MK_ADDR_CONST(0x6a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SCR                        AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0                    MK_ADDR_CONST(0x6a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_SCR                        AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0                        MK_ADDR_CONST(0x6a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_SCR                    AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0                 MK_ADDR_CONST(0x6a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_SCR                     AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_RESET_VAL                       MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_RESET_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_READ_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_DFLL_AXI_CBB                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_PLLC2_OUT0                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_PLLC4_MUXED                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_CLK_M                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_CLK_S                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0                   MK_ADDR_CONST(0x6a3004)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SCR                       AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_RESET_MASK                        MK_MASK_CONST(0xc000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_READ_MASK                         MK_MASK_CONST(0xc000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_WRITE_MASK                        MK_MASK_CONST(0xc000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_RANGE                   30:30
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0                   MK_ADDR_CONST(0x6a3008)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SCR                       AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_RESET_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_READ_MASK                         MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_WRITE_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0                        MK_ADDR_CONST(0x6a8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_SCR                    AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0                 MK_ADDR_CONST(0x6a8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_SCR                     AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0_AXI_CBB_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0                      MK_ADDR_CONST(0x6a8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_SCR                  AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0                     MK_ADDR_CONST(0x6a800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_SCR                         AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0                  MK_ADDR_CONST(0x6a8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_SCR                      AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0_AXI_CBB_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0                        MK_ADDR_CONST(0x6a8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_SCR                    AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0                 MK_ADDR_CONST(0x6a8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_SCR                     AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0_AXI_CBB_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0                  MK_ADDR_CONST(0x6a801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_SCR                      AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_WRITE_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0_AXI_CBB_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0                        MK_ADDR_CONST(0x6a8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_SCR                    AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_RESET_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_READ_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_WRITE_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0                    MK_ADDR_CONST(0x6a8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_SCR                        AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0                    MK_ADDR_CONST(0x6a8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_SCR                        AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0                    MK_ADDR_CONST(0x6a802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_SCR                        AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0_AXI_CBB_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0                 MK_ADDR_CONST(0x6a8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_SCR                     AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0_AXI_CBB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0                  MK_ADDR_CONST(0x6a8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_SCR                      AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0_AXI_CBB_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0                   MK_ADDR_CONST(0x6af000)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SCR                       0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0                   MK_ADDR_CONST(0x6af004)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0                  MK_ADDR_CONST(0x6b0000)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SCR                      0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_RESET_VAL                        MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_RESET_MASK                       MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_READ_MASK                        MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_WRITE_MASK                       MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x730000)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x740000)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x750000)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x760000)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x770000)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x780000

// Reserved address 0x790000

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0                  MK_ADDR_CONST(0x7b0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0                      MK_ADDR_CONST(0x7b0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0                      MK_ADDR_CONST(0x7b0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0                  MK_ADDR_CONST(0x7b1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0                   MK_ADDR_CONST(0x7b2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_PLLA_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_PLLA1_OUT1                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SYNC_CLK                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0                       MK_ADDR_CONST(0x7b3000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_RESET_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_READ_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_WRITE_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S2                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S3                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S4                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S5                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_PLLA_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S6                    MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CTRL_DMIC3_0
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0                 MK_ADDR_CONST(0x7b3004)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_SCR                     0
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_RANGE                 4:0
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC3_0_DMIC3_TRIMMER_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0                  MK_ADDR_CONST(0x7c0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0                      MK_ADDR_CONST(0x7c0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0                      MK_ADDR_CONST(0x7c0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0                  MK_ADDR_CONST(0x7c1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0                   MK_ADDR_CONST(0x7c2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_RESET_VAL                         MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_PLLA_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_PLLA1_OUT1                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SYNC_CLK                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_CLK_M                       MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(4)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0                       MK_ADDR_CONST(0x7c3000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_RESET_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_READ_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_WRITE_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S2                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S3                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S4                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S5                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_PLLA_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S6                    MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CTRL_DMIC4_0
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0                 MK_ADDR_CONST(0x7c3004)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_SCR                     0
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_RANGE                 4:0
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC4_0_DMIC4_TRIMMER_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0                  MK_ADDR_CONST(0x7d0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0                      MK_ADDR_CONST(0x7d0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0                      MK_ADDR_CONST(0x7d0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0                  MK_ADDR_CONST(0x7d1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0                   MK_ADDR_CONST(0x7d2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_PLLA_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_PLLA1_OUT1                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SYNC_CLK                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0                       MK_ADDR_CONST(0x7d3000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_RESET_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_READ_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_WRITE_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S2                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S3                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S4                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S5                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_PLLA_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S6                    MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0                     MK_ADDR_CONST(0x7d3004)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_RESET_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_READ_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_WRITE_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_RANGE                     4:0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0_DSPK1_TRIMMER_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0                  MK_ADDR_CONST(0x7e0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0                      MK_ADDR_CONST(0x7e0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0                      MK_ADDR_CONST(0x7e0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0                  MK_ADDR_CONST(0x7e1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0                   MK_ADDR_CONST(0x7e2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_PLLA_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_PLLA1_OUT1                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SYNC_CLK                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0                       MK_ADDR_CONST(0x7e3000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_RESET_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_READ_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_WRITE_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S2                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S3                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S4                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S5                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_PLLA_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S6                    MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0                     MK_ADDR_CONST(0x7e3004)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_RESET_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_READ_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_WRITE_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_RANGE                     4:0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0_DSPK2_TRIMMER_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0                   MK_ADDR_CONST(0x7f0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0                       MK_ADDR_CONST(0x7f0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0                       MK_ADDR_CONST(0x7f0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0                   MK_ADDR_CONST(0x7f1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0                    MK_ADDR_CONST(0x7f2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_RESET_VAL                  MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_PLLA_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_PLLA1_OUT1                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SYNC_CLK                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0                        MK_ADDR_CONST(0x7f2004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SPDIFIN                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S1                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S2                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S3                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S4                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S5                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_PLLA_OUT0                        MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S6                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0                 MK_ADDR_CONST(0x800000)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SCR                     NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_RESET_VAL                       MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_RESET_MASK                      MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_READ_MASK                       MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_WRITE_MASK                      MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_RANGE                  10:10
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD3_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_RANGE                   9:9
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_RANGE                  8:8
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_RANGE                  7:7
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_RANGE                  6:6
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_RANGE                  5:5
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_RANGE                  2:2
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0                     MK_ADDR_CONST(0x800004)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SCR                         NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_RESET_VAL                   MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_RESET_MASK                  MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_READ_MASK                   MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_WRITE_MASK                  MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_RANGE                  10:10
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD3_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_RANGE                   9:9
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_RANGE                  8:8
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_RANGE                  7:7
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_RANGE                  6:6
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_RANGE                  5:5
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_RANGE                  2:2
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0                     MK_ADDR_CONST(0x800008)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_SCR                         NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_RESET_VAL                   MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_RESET_MASK                  MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_READ_MASK                   MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_RANGE                  10:10
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD3_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_RANGE                   9:9
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_RANGE                  8:8
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_RANGE                  7:7
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_RANGE                  6:6
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_RANGE                  5:5
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_RANGE                  2:2
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0                     MK_ADDR_CONST(0x801000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_SCR                         NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_RESET_MASK                  MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_READ_MASK                   MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_WRITE_MASK                  MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_RANGE                  3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0                 MK_ADDR_CONST(0x801004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SCR                     NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_RESET_MASK                      MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_READ_MASK                       MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_WRITE_MASK                      MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_RANGE                  3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0                 MK_ADDR_CONST(0x801008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_SCR                     NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_RESET_MASK                      MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_READ_MASK                       MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_WRITE_MASK                      MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_RANGE                  3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0                     MK_ADDR_CONST(0x802000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_SCR                         NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_RESET_MASK                  MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_READ_MASK                   MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_WRITE_MASK                  MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_RANGE                 3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_RANGE                       1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0                    MK_ADDR_CONST(0x803000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_SCR                        NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_RESET_VAL                  MK_MASK_CONST(0xa0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLD2_OUT0                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLD3_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLD4_OUT0                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_CLK_M                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLD_OUT2                     MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0                  MK_ADDR_CONST(0x804000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_SCR                      NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_RESET_VAL                        MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_RESET_MASK                       MK_MASK_CONST(0xff0000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_READ_MASK                        MK_MASK_CONST(0xff0000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_WRITE_MASK                       MK_MASK_CONST(0xff0000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_RANGE                     31:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x80)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_NVDISPLAY_P0_CLK                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_NVDISPLAY_P1_CLK                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_NVDISPLAY_P2_CLK                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_NVDISPLAY_P3_CLK                  MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SOR_SAFE_CLK                      MK_ENUM_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_CLK_M                     MK_ENUM_CONST(128)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0                    MK_ADDR_CONST(0x805000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_SCR                        NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_PLLDISPHUB                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_CLK_M                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_DFLLDISP                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0                     MK_ADDR_CONST(0x805004)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SCR                         NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_RESET_VAL                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_RESET_MASK                  MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_READ_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_WRITE_MASK                  MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0                       MK_ADDR_CONST(0x806000)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_SCR                   NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0                     MK_ADDR_CONST(0x808000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_SCR                         NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0                      MK_ADDR_CONST(0x808004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_SCR                  NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0                   MK_ADDR_CONST(0x808008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_SCR                       NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0                  MK_ADDR_CONST(0x80800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_SCR                      NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0                       MK_ADDR_CONST(0x808010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_SCR                   NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_FAULT_REPORT_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0_NVDISPLAY0_FMON_ACTION_RESET_REQ_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0                     MK_ADDR_CONST(0x808014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_SCR                         NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_RANGE                  6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_DC_FAULT_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                       5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REPORT_OVERFLOW_ERROR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_CLK_WINDOW_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_COUNTER_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0                      MK_ADDR_CONST(0x808018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_SCR                  NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                     FALNVDISPLAY0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_FALNVDISPLAY0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                 FALNVDISPLAY0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALNVDISPLAY0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                     0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                 FALNVDISPLAY0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_FALNVDISPLAY0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0                       MK_ADDR_CONST(0x80801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_SCR                   NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_RESET_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_READ_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_WRITE_MASK                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_INIT_ENUM                 FALNVDISPLAY0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_FALNVDISPLAY0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_CLEAR_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_INIT_ENUM                    FALNVDISPLAY0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_FALNVDISPLAY0                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_FAULT_OUT_STATUS_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_RANGE                  3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_INIT_ENUM                      FALNVDISPLAY0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_FALNVDISPLAY0                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_OVERFLOW_ERROR_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                  2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                      FALNVDISPLAY0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALNVDISPLAY0                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                       FALNVDISPLAY0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALNVDISPLAY0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_INIT_ENUM                    FALNVDISPLAY0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_FALNVDISPLAY0                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0_NVDISPLAY0_FMON_DC_FAULT_TRUE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0                     MK_ADDR_CONST(0x808020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_SCR                         NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_RESET_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_READ_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_WRITE_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_RANGE                 2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0                 MK_ADDR_CONST(0x808024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_SCR                     NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_DONE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0                 MK_ADDR_CONST(0x808028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_SCR                     NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_RANGE                      2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0                 MK_ADDR_CONST(0x80802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_SCR                     NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0_NVDISPLAY0_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0                      MK_ADDR_CONST(0x808030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_SCR                  NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0_NVDISPLAY0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0                       MK_ADDR_CONST(0x808034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_SCR                   NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_RANGE                      1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_REF_WINDOW_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0_NVDISPLAY0_FMON_ENABLE_DEBUG_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0                   MK_ADDR_CONST(0x808038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_SCR                       NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0                    MK_ADDR_CONST(0x80803c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_SCR                        NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0                 MK_ADDR_CONST(0x808040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_SCR                     NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0                        MK_ADDR_CONST(0x808044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_SCR                    NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0                     MK_ADDR_CONST(0x808048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_SCR                         NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0                   MK_ADDR_CONST(0x80804c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_SCR                       NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0                    MK_ADDR_CONST(0x808050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_SCR                        NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALNVDISPLAYHUB
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_FALNVDISPLAYHUB                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALNVDISPLAYHUB
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALNVDISPLAYHUB                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALNVDISPLAYHUB
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_FALNVDISPLAYHUB                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0                     MK_ADDR_CONST(0x808054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_SCR                         NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_INIT_ENUM                     FALNVDISPLAYHUB
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_FALNVDISPLAYHUB                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALNVDISPLAYHUB
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_FALNVDISPLAYHUB                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALNVDISPLAYHUB
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_FALNVDISPLAYHUB                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALNVDISPLAYHUB
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALNVDISPLAYHUB                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALNVDISPLAYHUB
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALNVDISPLAYHUB                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_INIT_ENUM                        FALNVDISPLAYHUB
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_FALNVDISPLAYHUB                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0                   MK_ADDR_CONST(0x808058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_SCR                       NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0                       MK_ADDR_CONST(0x80805c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_SCR                   NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0                       MK_ADDR_CONST(0x808060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_SCR                   NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0                       MK_ADDR_CONST(0x808064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_SCR                   NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0                    MK_ADDR_CONST(0x808068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_SCR                        NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0                     MK_ADDR_CONST(0x80806c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_SCR                         NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0_NVDISPLAYHUB_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0                        MK_ADDR_CONST(0x80f000)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0                        MK_ADDR_CONST(0x80f004)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0                      MK_ADDR_CONST(0x80f008)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0                     MK_ADDR_CONST(0x810000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_SCR                         NVDISPLAY1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0                 MK_ADDR_CONST(0x810004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SCR                     NVDISPLAY1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0                 MK_ADDR_CONST(0x810008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_SCR                     NVDISPLAY1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0                     MK_ADDR_CONST(0x811000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_SCR                         NVDISPLAY1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0                    MK_ADDR_CONST(0x812000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_SCR                        NVDISPLAY1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_RESET_VAL                  MK_MASK_CONST(0xa0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLD2_OUT0                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLD3_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLD4_OUT0                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_CLK_M                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLD_OUT2                     MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0                     MK_ADDR_CONST(0x818000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_SCR                         NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0                      MK_ADDR_CONST(0x818004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_SCR                  NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0                   MK_ADDR_CONST(0x818008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_SCR                       NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0                  MK_ADDR_CONST(0x81800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_SCR                      NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0                       MK_ADDR_CONST(0x818010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_SCR                   NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_FAULT_REPORT_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0_NVDISPLAY1_FMON_ACTION_RESET_REQ_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0                     MK_ADDR_CONST(0x818014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_SCR                         NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_RANGE                  6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_DC_FAULT_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                       5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REPORT_OVERFLOW_ERROR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_CLK_WINDOW_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_COUNTER_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0                      MK_ADDR_CONST(0x818018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_SCR                  NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                     FALNVDISPLAY1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_FALNVDISPLAY1                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                 FALNVDISPLAY1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALNVDISPLAY1                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                     0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                 FALNVDISPLAY1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_FALNVDISPLAY1                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0                       MK_ADDR_CONST(0x81801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_SCR                   NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_RESET_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_READ_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_WRITE_MASK                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_INIT_ENUM                 FALNVDISPLAY1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_FALNVDISPLAY1                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_CLEAR_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_INIT_ENUM                    FALNVDISPLAY1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_FALNVDISPLAY1                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_FAULT_OUT_STATUS_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_RANGE                  3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_INIT_ENUM                      FALNVDISPLAY1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_FALNVDISPLAY1                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_OVERFLOW_ERROR_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                  2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                      FALNVDISPLAY1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALNVDISPLAY1                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                       FALNVDISPLAY1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALNVDISPLAY1                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_INIT_ENUM                    FALNVDISPLAY1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_FALNVDISPLAY1                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0_NVDISPLAY1_FMON_DC_FAULT_TRUE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0                     MK_ADDR_CONST(0x818020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_SCR                         NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_RESET_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_READ_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_WRITE_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_RANGE                 2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0                 MK_ADDR_CONST(0x818024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_SCR                     NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_DONE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0                 MK_ADDR_CONST(0x818028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_SCR                     NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_RANGE                      2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0                 MK_ADDR_CONST(0x81802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_SCR                     NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0_NVDISPLAY1_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0                      MK_ADDR_CONST(0x818030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_SCR                  NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0_NVDISPLAY1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0                       MK_ADDR_CONST(0x818034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_SCR                   NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_RANGE                      1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_REF_WINDOW_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0_NVDISPLAY1_FMON_ENABLE_DEBUG_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0                        MK_ADDR_CONST(0x81f000)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0                        MK_ADDR_CONST(0x81f004)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0                     MK_ADDR_CONST(0x820000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_SCR                         NVDISPLAY2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0                 MK_ADDR_CONST(0x820004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SCR                     NVDISPLAY2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0                 MK_ADDR_CONST(0x820008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_SCR                     NVDISPLAY2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0                     MK_ADDR_CONST(0x821000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_SCR                         NVDISPLAY2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0                    MK_ADDR_CONST(0x822000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_SCR                        NVDISPLAY2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_RESET_VAL                  MK_MASK_CONST(0xa0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLD2_OUT0                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLD3_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLD4_OUT0                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_CLK_M                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLD_OUT2                     MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0                     MK_ADDR_CONST(0x828000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_SCR                         NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0                      MK_ADDR_CONST(0x828004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_SCR                  NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0                   MK_ADDR_CONST(0x828008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_SCR                       NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0                  MK_ADDR_CONST(0x82800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_SCR                      NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0                       MK_ADDR_CONST(0x828010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_SCR                   NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_FAULT_REPORT_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0_NVDISPLAY2_FMON_ACTION_RESET_REQ_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0                     MK_ADDR_CONST(0x828014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_SCR                         NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_RANGE                  6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_DC_FAULT_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                       5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REPORT_OVERFLOW_ERROR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_CLK_WINDOW_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_COUNTER_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0                      MK_ADDR_CONST(0x828018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_SCR                  NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                     FALNVDISPLAY2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_FALNVDISPLAY2                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                 FALNVDISPLAY2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALNVDISPLAY2                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                     0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                 FALNVDISPLAY2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_FALNVDISPLAY2                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0                       MK_ADDR_CONST(0x82801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_SCR                   NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_RESET_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_READ_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_WRITE_MASK                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_INIT_ENUM                 FALNVDISPLAY2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_FALNVDISPLAY2                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_CLEAR_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_INIT_ENUM                    FALNVDISPLAY2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_FALNVDISPLAY2                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_FAULT_OUT_STATUS_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_RANGE                  3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_INIT_ENUM                      FALNVDISPLAY2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_FALNVDISPLAY2                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_OVERFLOW_ERROR_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                  2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                      FALNVDISPLAY2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALNVDISPLAY2                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                       FALNVDISPLAY2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALNVDISPLAY2                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_INIT_ENUM                    FALNVDISPLAY2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_FALNVDISPLAY2                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0_NVDISPLAY2_FMON_DC_FAULT_TRUE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0                     MK_ADDR_CONST(0x828020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_SCR                         NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_RESET_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_READ_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_WRITE_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_RANGE                 2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0                 MK_ADDR_CONST(0x828024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_SCR                     NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_DONE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0                 MK_ADDR_CONST(0x828028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_SCR                     NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_RANGE                      2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0                 MK_ADDR_CONST(0x82802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_SCR                     NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0_NVDISPLAY2_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0                      MK_ADDR_CONST(0x828030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_SCR                  NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0_NVDISPLAY2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0                       MK_ADDR_CONST(0x828034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_SCR                   NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_RANGE                      1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_REF_WINDOW_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0_NVDISPLAY2_FMON_ENABLE_DEBUG_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0                        MK_ADDR_CONST(0x82f000)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0                        MK_ADDR_CONST(0x82f004)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0                     MK_ADDR_CONST(0x830000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_SCR                         NVDISPLAY3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0_CLK_ENB_NVDISPLAY_P3_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0                 MK_ADDR_CONST(0x830004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SCR                     NVDISPLAY3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0_SET_CLK_ENB_NVDISPLAY_P3_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0                 MK_ADDR_CONST(0x830008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_SCR                     NVDISPLAY3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0_CLR_CLK_ENB_NVDISPLAY_P3_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0                     MK_ADDR_CONST(0x831000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_SCR                         NVDISPLAY3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0_BOND_OUT_NVDISPLAY_P3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0                    MK_ADDR_CONST(0x832000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_SCR                        NVDISPLAY3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_RESET_VAL                  MK_MASK_CONST(0xa0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_PLLD2_OUT0                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_PLLD3_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_PLLD4_OUT0                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_CLK_M                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_SRC_PLLD_OUT2                     MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0_NVDISPLAY_P3_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0                     MK_ADDR_CONST(0x838000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_SCR                         NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0                      MK_ADDR_CONST(0x838004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_SCR                  NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0                   MK_ADDR_CONST(0x838008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_SCR                       NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0                  MK_ADDR_CONST(0x83800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_SCR                      NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0                       MK_ADDR_CONST(0x838010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_SCR                   NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_FAULT_REPORT_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0_NVDISPLAY3_FMON_ACTION_RESET_REQ_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0                     MK_ADDR_CONST(0x838014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_SCR                         NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_RANGE                  6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_DC_FAULT_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                       5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REPORT_OVERFLOW_ERROR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_CLK_WINDOW_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_COUNTER_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0                      MK_ADDR_CONST(0x838018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_SCR                  NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                     FALNVDISPLAY3
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_FALNVDISPLAY3                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                 FALNVDISPLAY3
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALNVDISPLAY3                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                     0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                 FALNVDISPLAY3
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_FALNVDISPLAY3                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0                       MK_ADDR_CONST(0x83801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_SCR                   NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_RESET_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_READ_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_WRITE_MASK                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_INIT_ENUM                 FALNVDISPLAY3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_FALNVDISPLAY3                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_CLEAR_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_INIT_ENUM                    FALNVDISPLAY3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_FALNVDISPLAY3                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_FAULT_OUT_STATUS_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_RANGE                  3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_INIT_ENUM                      FALNVDISPLAY3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_FALNVDISPLAY3                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_OVERFLOW_ERROR_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                  2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                      FALNVDISPLAY3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALNVDISPLAY3                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                       FALNVDISPLAY3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALNVDISPLAY3                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_INIT_ENUM                    FALNVDISPLAY3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_FALNVDISPLAY3                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0_NVDISPLAY3_FMON_DC_FAULT_TRUE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0                     MK_ADDR_CONST(0x838020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_SCR                         NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_RESET_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_READ_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_WRITE_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_RANGE                 2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0                 MK_ADDR_CONST(0x838024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_SCR                     NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_DONE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0                 MK_ADDR_CONST(0x838028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_SCR                     NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_RANGE                      2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0                 MK_ADDR_CONST(0x83802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_SCR                     NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0_NVDISPLAY3_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0                      MK_ADDR_CONST(0x838030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_SCR                  NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0_NVDISPLAY3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0                       MK_ADDR_CONST(0x838034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_SCR                   NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_RANGE                      1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_REF_WINDOW_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0_NVDISPLAY3_FMON_ENABLE_DEBUG_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0                        MK_ADDR_CONST(0x83f000)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0                        MK_ADDR_CONST(0x83f004)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x840000

// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0                  MK_ADDR_CONST(0x840000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0                      MK_ADDR_CONST(0x840004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0                      MK_ADDR_CONST(0x840008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0                      MK_ADDR_CONST(0x841000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0                  MK_ADDR_CONST(0x841004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0                  MK_ADDR_CONST(0x841008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0                      MK_ADDR_CONST(0x842000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0                       MK_ADDR_CONST(0x843000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_RESET_VAL                     MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_CLK_M                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0                  MK_ADDR_CONST(0x850000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0                      MK_ADDR_CONST(0x850004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0                      MK_ADDR_CONST(0x850008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0                      MK_ADDR_CONST(0x851000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0                  MK_ADDR_CONST(0x851004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0                  MK_ADDR_CONST(0x851008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0                      MK_ADDR_CONST(0x852000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0                       MK_ADDR_CONST(0x853000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_RESET_VAL                     MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_CLK_M                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0                  MK_ADDR_CONST(0x860000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0                      MK_ADDR_CONST(0x860004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0                      MK_ADDR_CONST(0x860008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0                      MK_ADDR_CONST(0x861000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0                  MK_ADDR_CONST(0x861004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0                  MK_ADDR_CONST(0x861008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0                      MK_ADDR_CONST(0x862000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0                       MK_ADDR_CONST(0x863000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_RESET_VAL                     MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_CLK_M                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0                  MK_ADDR_CONST(0x870000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0                      MK_ADDR_CONST(0x870004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0                      MK_ADDR_CONST(0x870008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0                      MK_ADDR_CONST(0x871000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0                  MK_ADDR_CONST(0x871004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0                  MK_ADDR_CONST(0x871008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0                      MK_ADDR_CONST(0x872000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0                       MK_ADDR_CONST(0x873000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_RESET_VAL                     MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_CLK_M                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0                  MK_ADDR_CONST(0x880000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0                      MK_ADDR_CONST(0x880004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0                      MK_ADDR_CONST(0x880008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0                      MK_ADDR_CONST(0x881000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0                  MK_ADDR_CONST(0x881004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0                  MK_ADDR_CONST(0x881008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0                      MK_ADDR_CONST(0x882000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0                       MK_ADDR_CONST(0x883000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_RESET_VAL                     MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_CLK_M                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_TACH_0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0                       MK_ADDR_CONST(0x890000)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0                   MK_ADDR_CONST(0x890004)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0                   MK_ADDR_CONST(0x890008)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0                   MK_ADDR_CONST(0x891000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0                       MK_ADDR_CONST(0x891004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0                       MK_ADDR_CONST(0x891008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0                   MK_ADDR_CONST(0x892000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0                    MK_ADDR_CONST(0x893000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_RESET_VAL                  MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_CLK_M                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_EQOS_0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0                       MK_ADDR_CONST(0x8a0000)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SCR                   EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0                   MK_ADDR_CONST(0x8a0004)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SCR                       EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0                   MK_ADDR_CONST(0x8a0008)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_SCR                       EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0                   MK_ADDR_CONST(0x8a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_SCR                       EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0                       MK_ADDR_CONST(0x8a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SCR                   EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0                       MK_ADDR_CONST(0x8a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_SCR                   EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0                   MK_ADDR_CONST(0x8a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_SCR                       EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0                    MK_ADDR_CONST(0x8a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_SCR                        EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_RESET_VAL                  MK_MASK_CONST(0x800)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_RESET_MASK                         MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_READ_MASK                  MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_WRITE_MASK                         MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_RANGE                 15:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0                        MK_ADDR_CONST(0x8a3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_SCR                    EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_RESET_VAL                      MK_MASK_CONST(0x3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_RESET_MASK                     MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_READ_MASK                      MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_WRITE_MASK                     MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_RANGE                 15:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x30)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0                     MK_ADDR_CONST(0x8a3008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_SCR                         EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_RESET_VAL                   MK_MASK_CONST(0x800)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_RESET_MASK                  MK_MASK_CONST(0x1ff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_READ_MASK                   MK_MASK_CONST(0x1ff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_WRITE_MASK                  MK_MASK_CONST(0x1ff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_RANGE                   16:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0                        MK_ADDR_CONST(0x8a8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_SCR                    EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0                 MK_ADDR_CONST(0x8a8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_SCR                     EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0_EQOS_TX_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0                      MK_ADDR_CONST(0x8a8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_SCR                  EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0                     MK_ADDR_CONST(0x8a800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_SCR                         EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0                  MK_ADDR_CONST(0x8a8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_SCR                      EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0_EQOS_TX_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0                        MK_ADDR_CONST(0x8a8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_SCR                    EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0                 MK_ADDR_CONST(0x8a8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_SCR                     EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0_EQOS_TX_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0                  MK_ADDR_CONST(0x8a801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_SCR                      EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_WRITE_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0_EQOS_TX_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0                        MK_ADDR_CONST(0x8a8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_SCR                    EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_RESET_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_READ_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_WRITE_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0                    MK_ADDR_CONST(0x8a8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_SCR                        EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0                    MK_ADDR_CONST(0x8a8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_SCR                        EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0                    MK_ADDR_CONST(0x8a802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_SCR                        EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0_EQOS_TX_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0                 MK_ADDR_CONST(0x8a8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_SCR                     EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0_EQOS_TX_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0                  MK_ADDR_CONST(0x8a8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_SCR                      EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0_EQOS_TX_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0                       MK_ADDR_CONST(0x8a8038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_SCR                   EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0                        MK_ADDR_CONST(0x8a803c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_SCR                    EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0                     MK_ADDR_CONST(0x8a8040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_SCR                         EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0                    MK_ADDR_CONST(0x8a8044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_SCR                        EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0                 MK_ADDR_CONST(0x8a8048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_SCR                     EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0_EQOS_AXI_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0                       MK_ADDR_CONST(0x8a804c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_SCR                   EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0                        MK_ADDR_CONST(0x8a8050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_SCR                    EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0                 MK_ADDR_CONST(0x8a8054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_SCR                     EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_RESET_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_READ_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_WRITE_MASK                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0_EQOS_AXI_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0                       MK_ADDR_CONST(0x8a8058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_SCR                   EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_RESET_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_READ_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_WRITE_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0                   MK_ADDR_CONST(0x8a805c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_SCR                       EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0                   MK_ADDR_CONST(0x8a8060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_SCR                       EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0                   MK_ADDR_CONST(0x8a8064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_SCR                       EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0_EQOS_AXI_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0                        MK_ADDR_CONST(0x8a8068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_SCR                    EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0_EQOS_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0                 MK_ADDR_CONST(0x8a806c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_SCR                     EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0_EQOS_AXI_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0                       MK_ADDR_CONST(0x8a8070)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_SCR                   EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0                        MK_ADDR_CONST(0x8a8074)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_SCR                    EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0                     MK_ADDR_CONST(0x8a8078)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_SCR                         EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0                    MK_ADDR_CONST(0x8a807c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_SCR                        EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0                 MK_ADDR_CONST(0x8a8080)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_SCR                     EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0_EQOS_PTP_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0                       MK_ADDR_CONST(0x8a8084)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_SCR                   EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0                        MK_ADDR_CONST(0x8a8088)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_SCR                    EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0                 MK_ADDR_CONST(0x8a808c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_SCR                     EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_RESET_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_READ_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_WRITE_MASK                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0_EQOS_PTP_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0                       MK_ADDR_CONST(0x8a8090)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_SCR                   EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_RESET_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_READ_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_WRITE_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0                   MK_ADDR_CONST(0x8a8094)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_SCR                       EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0                   MK_ADDR_CONST(0x8a8098)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_SCR                       EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0                   MK_ADDR_CONST(0x8a809c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_SCR                       EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0_EQOS_PTP_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0                        MK_ADDR_CONST(0x8a80a0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_SCR                    EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0_EQOS_PTP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0                 MK_ADDR_CONST(0x8a80a4)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_SCR                     EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0_EQOS_PTP_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0                      MK_ADDR_CONST(0x8af000)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0                   MK_ADDR_CONST(0x8af004)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0                  MK_ADDR_CONST(0x8af008)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0                  MK_ADDR_CONST(0x8af00c)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0                        MK_ADDR_CONST(0x8b0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0                    MK_ADDR_CONST(0x8b0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0                    MK_ADDR_CONST(0x8b0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0                        MK_ADDR_CONST(0x8b1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSB_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0                      MK_ADDR_CONST(0x8c0000)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SCR                  EMCSB_SCR_EMCSB_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0                  MK_ADDR_CONST(0x8c0004)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SCR                      EMCSB_SCR_EMCSB_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0                  MK_ADDR_CONST(0x8c0008)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_SCR                      EMCSB_SCR_EMCSB_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_RESET_VAL                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0                  MK_ADDR_CONST(0x8c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_SCR                      EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_RESET_VAL                        MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_RESET_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_READ_MASK                        MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_WRITE_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0                      MK_ADDR_CONST(0x8c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SCR                  EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_RESET_VAL                    MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_RESET_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_READ_MASK                    MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_WRITE_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0                      MK_ADDR_CONST(0x8c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_SCR                  EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_RESET_VAL                    MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_RESET_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_READ_MASK                    MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0                  MK_ADDR_CONST(0x8c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_SCR                      EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_RESET_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_READ_MASK                        MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_WRITE_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_RANGE                   10:10
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_RANGE                       9:9
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_RANGE                      8:8
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_RANGE                     7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_RANGE                    6:6
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_RANGE                    5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_RANGE                   2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_RANGE                       1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0                   MK_ADDR_CONST(0x8c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_SCR                       EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_RESET_VAL                         MK_MASK_CONST(0x60900000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_RESET_MASK                        MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_READ_MASK                         MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_WRITE_MASK                        MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_RANGE                      31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_DEFAULT                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_INIT_ENUM                  OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLM_OUT0                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLC_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLP_OUT0                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_OSC_UNDIV                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLM_UD                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLMB_UD                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLMB_OUT0                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLP_UD                    MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_RANGE                    27:27
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_RANGE                      26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_RANGE                 23:23
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_SWITCH_COMPLETE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_RANGE                 20:20
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_RANGE                     15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0                   MK_ADDR_CONST(0x8c3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_SCR                       EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_RESET_VAL                         MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_CLK_M                 MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0                       MK_ADDR_CONST(0x8c3008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_SCR                   EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_RESET_VAL                     MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_RESET_MASK                    MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_READ_MASK                     MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_WRITE_MASK                    MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLM_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLM_UD                       MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLMB_UD                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLMB_OUT0                    MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLP_UD                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_RANGE                    11:10
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_PLLM_VCOA                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_PLLM_VCOB                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_EMC_DLL_SWITCH_OUT                       MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0                  MK_ADDR_CONST(0x8c300c)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_SCR                      EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_RESET_VAL                        MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_RESET_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_READ_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_RANGE                      31:31
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_RANGE                      11:11
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_RANGE                      10:10
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_RANGE                      9:9
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_RANGE                      8:8
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_RANGE                        7:7
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                    DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_PROG                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_RANGE                  6:6
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                      ACTIVE
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_ACTIVE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_BYPASS                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_RANGE                 4:3
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_RANGE                 1:0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0                     MK_ADDR_CONST(0x8c3010)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_SCR                         EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_RESET_VAL                   MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_RESET_MASK                  MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_READ_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_WRITE_MASK                  MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_ACTIVE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_BYPASS                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0                      MK_ADDR_CONST(0x8c3014)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_SCR                  EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_RESET_VAL                    MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_RESET_MASK                   MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_READ_MASK                    MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_WRITE_MASK                   MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_RANGE                    31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_INIT_ENUM                        CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_OUT0                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLC_OUT0                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_OUT0                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_CLK_M                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_UD                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_UD                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_UD                  MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_LSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0                     MK_ADDR_CONST(0x8c4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_SCR                         EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0                      MK_ADDR_CONST(0x8c8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_SCR                  EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0                       MK_ADDR_CONST(0x8c8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_SCR                   EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0                    MK_ADDR_CONST(0x8c8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_SCR                        EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0                   MK_ADDR_CONST(0x8c800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_SCR                       EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0                        MK_ADDR_CONST(0x8c8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_SCR                    EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0_EMCSB_CDB_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0                      MK_ADDR_CONST(0x8c8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_SCR                  EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_RESET_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_READ_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0                       MK_ADDR_CONST(0x8c8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_SCR                   EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0                        MK_ADDR_CONST(0x8c801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_SCR                    EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_RESET_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_READ_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0_EMCSB_CDB_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0                      MK_ADDR_CONST(0x8c8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_SCR                  EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_RESET_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_READ_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_WRITE_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0                  MK_ADDR_CONST(0x8c8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_SCR                      EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0                  MK_ADDR_CONST(0x8c8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_SCR                      EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0                  MK_ADDR_CONST(0x8c802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_SCR                      EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0_EMCSB_CDB_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0                       MK_ADDR_CONST(0x8c8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_SCR                   EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0_EMCSB_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0                        MK_ADDR_CONST(0x8c8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_SCR                    EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0_EMCSB_CDB_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0                   MK_ADDR_CONST(0x8cf000)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SCR                       0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0                       MK_ADDR_CONST(0x8cf004)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SCR                   0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0                   MK_ADDR_CONST(0x8cf008)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0                        MK_ADDR_CONST(0x8d0000)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_RESET_VAL                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0                    MK_ADDR_CONST(0x8d0004)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_RESET_VAL                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0                    MK_ADDR_CONST(0x8d0008)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_RESET_VAL                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0                    MK_ADDR_CONST(0x8d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_RESET_MASK                         MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_READ_MASK                  MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_WRITE_MASK                         MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_RANGE                   31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0                        MK_ADDR_CONST(0x8d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_RESET_MASK                     MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_READ_MASK                      MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_WRITE_MASK                     MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_RANGE                   31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0                        MK_ADDR_CONST(0x8d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_RESET_MASK                     MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_READ_MASK                      MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_RANGE                   31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0                    MK_ADDR_CONST(0x8d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_RESET_MASK                         MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_READ_MASK                  MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_WRITE_MASK                         MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_RANGE                  31:31
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0                    MK_ADDR_CONST(0x8d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_CLK_M                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_PLLREFE_VCOCLK                        MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0                      MK_ADDR_CONST(0x8d3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_RESET_MASK                   MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_READ_MASK                    MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_WRITE_MASK                   MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_CLK_M                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_PLLREFE_VCOCLK                    MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_RANGE                 8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVCSI_0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0                      MK_ADDR_CONST(0x8e0000)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SCR                  NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0                  MK_ADDR_CONST(0x8e0004)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SCR                      NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0                  MK_ADDR_CONST(0x8e0008)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_SCR                      NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0                  MK_ADDR_CONST(0x8e1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_SCR                      NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0                      MK_ADDR_CONST(0x8e1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SCR                  NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0                      MK_ADDR_CONST(0x8e1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_SCR                  NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0                  MK_ADDR_CONST(0x8e2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_SCR                      NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_RANGE                   1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0                   MK_ADDR_CONST(0x8e3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_SCR                       NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_RESET_VAL                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_RESET_MASK                        MK_MASK_CONST(0xe00003ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_READ_MASK                         MK_MASK_CONST(0xe00003ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_WRITE_MASK                        MK_MASK_CONST(0xe00003ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_PLLNVCSI_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_CLK_M                       MK_ENUM_CONST(4)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_RANGE                      9:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_INIT_ENUM                  CSI_AB_PAD_CLOCKOUT
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_CSI_AB_PAD_CLOCKOUT                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_CSI_CD_PAD_CLOCKOUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_CSI_EF_PAD_CLOCKOUT                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_CSI_GH_PAD_CLOCKOUT                        MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0                 MK_ADDR_CONST(0x8e3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_SCR                     NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_RESET_VAL                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_RESET_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_READ_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_CLK_M                   MK_ENUM_CONST(4)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CSI_CLK_SRC_0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0                        MK_ADDR_CONST(0x8e3008)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_SCR                    NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_SHIFT)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_RANGE                 7:7
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_B_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_SHIFT)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_RANGE                 6:6
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_GH_A_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_SHIFT)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_RANGE                 5:5
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_B_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_SHIFT)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_RANGE                 4:4
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_EF_A_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_SHIFT)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_RANGE                 3:3
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_B_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_SHIFT)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_RANGE                 2:2
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_CD_A_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_SHIFT)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_RANGE                 1:1
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_B_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_SHIFT)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_RANGE                 0:0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CSI_CLK_SRC_0_CSI_CLK_SRC_AB_A_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0                  MK_ADDR_CONST(0x8e8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_SCR                      NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0_NVCSI_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0                   MK_ADDR_CONST(0x8e8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_SCR                       NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0_NVCSI_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0                        MK_ADDR_CONST(0x8e8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_SCR                    NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0                       MK_ADDR_CONST(0x8e800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_SCR                   NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_RESET_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_READ_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_WRITE_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0_NVCSI_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0                    MK_ADDR_CONST(0x8e8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_SCR                        NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0_NVCSI_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0                  MK_ADDR_CONST(0x8e8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_SCR                      NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_READ_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0                   MK_ADDR_CONST(0x8e8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_SCR                       NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0_NVCSI_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0                    MK_ADDR_CONST(0x8e801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_SCR                        NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_RESET_MASK                         MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_READ_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_WRITE_MASK                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0_NVCSI_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0                  MK_ADDR_CONST(0x8e8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_SCR                      NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_RESET_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_READ_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_WRITE_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0                      MK_ADDR_CONST(0x8e8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_SCR                  NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0_NVCSI_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0                      MK_ADDR_CONST(0x8e8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_SCR                  NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0_NVCSI_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0                      MK_ADDR_CONST(0x8e802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_SCR                  NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0_NVCSI_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0                   MK_ADDR_CONST(0x8e8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_SCR                       NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0_NVCSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0                    MK_ADDR_CONST(0x8e8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_SCR                        NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0_NVCSI_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0                        MK_ADDR_CONST(0x8e8038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_SCR                    NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0                 MK_ADDR_CONST(0x8e803c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_SCR                     NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0_NVCSILP_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0                      MK_ADDR_CONST(0x8e8040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_SCR                  NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0                     MK_ADDR_CONST(0x8e8044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_SCR                         NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0                  MK_ADDR_CONST(0x8e8048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_SCR                      NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0_NVCSILP_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0                        MK_ADDR_CONST(0x8e804c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_SCR                    NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0                 MK_ADDR_CONST(0x8e8050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_SCR                     NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0_NVCSILP_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0                  MK_ADDR_CONST(0x8e8054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_SCR                      NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_WRITE_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0_NVCSILP_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0                        MK_ADDR_CONST(0x8e8058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_SCR                    NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_RESET_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_READ_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_WRITE_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0                    MK_ADDR_CONST(0x8e805c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_SCR                        NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0                    MK_ADDR_CONST(0x8e8060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_SCR                        NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0                    MK_ADDR_CONST(0x8e8064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_SCR                        NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0_NVCSILP_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0                 MK_ADDR_CONST(0x8e8068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_SCR                     NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0_NVCSILP_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0                  MK_ADDR_CONST(0x8e806c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_SCR                      NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0_NVCSILP_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0                     MK_ADDR_CONST(0x8ef000)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SCR                         0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0                       MK_ADDR_CONST(0x8ef004)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SCR                   0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0                     MK_ADDR_CONST(0x8ef008)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SCR                         0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C7_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0                       MK_ADDR_CONST(0x8f0000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SCR                   I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0                   MK_ADDR_CONST(0x8f0004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SCR                       I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0                   MK_ADDR_CONST(0x8f0008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_SCR                       I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0                   MK_ADDR_CONST(0x8f1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_SCR                       I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0                       MK_ADDR_CONST(0x8f1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SCR                   I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0                       MK_ADDR_CONST(0x8f1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_SCR                   I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0                   MK_ADDR_CONST(0x8f2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_SCR                       I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0                    MK_ADDR_CONST(0x8f3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_SCR                        I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_RESET_VAL                  MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_RESET_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_READ_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_WRITE_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_CLK_M                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0                   MK_ADDR_CONST(0x8f8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_SCR                       I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0_I2C7_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0                    MK_ADDR_CONST(0x8f8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_SCR                        I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0_I2C7_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0                 MK_ADDR_CONST(0x8f8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_SCR                     I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0                        MK_ADDR_CONST(0x8f800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_SCR                    I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0_I2C7_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0                     MK_ADDR_CONST(0x8f8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_SCR                         I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0_I2C7_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0                   MK_ADDR_CONST(0x8f8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_SCR                       I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0_I2C7_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0                    MK_ADDR_CONST(0x8f8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_SCR                        I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0_I2C7_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0                     MK_ADDR_CONST(0x8f801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_SCR                         I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0_I2C7_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0                   MK_ADDR_CONST(0x8f8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_SCR                       I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0                       MK_ADDR_CONST(0x8f8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_SCR                   I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0_I2C7_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0                       MK_ADDR_CONST(0x8f8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_SCR                   I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0_I2C7_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0                       MK_ADDR_CONST(0x8f802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_SCR                   I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0_I2C7_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0                    MK_ADDR_CONST(0x8f8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_SCR                        I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0_I2C7_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0                     MK_ADDR_CONST(0x8f8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_SCR                         I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0_I2C7_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0                      MK_ADDR_CONST(0x8ff000)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0                      MK_ADDR_CONST(0x8ff004)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C7_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C9_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0                       MK_ADDR_CONST(0x900000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SCR                   I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0                   MK_ADDR_CONST(0x900004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SCR                       I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0                   MK_ADDR_CONST(0x900008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_SCR                       I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0                   MK_ADDR_CONST(0x901000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_SCR                       I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0                       MK_ADDR_CONST(0x901004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SCR                   I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0                       MK_ADDR_CONST(0x901008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_SCR                   I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0                   MK_ADDR_CONST(0x902000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_SCR                       I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0                    MK_ADDR_CONST(0x903000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_SCR                        I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_RESET_VAL                  MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_RESET_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_READ_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_WRITE_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_CLK_M                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0                   MK_ADDR_CONST(0x908000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_SCR                       I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0_I2C9_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0                    MK_ADDR_CONST(0x908004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_SCR                        I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0_I2C9_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0                 MK_ADDR_CONST(0x908008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_SCR                     I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0                        MK_ADDR_CONST(0x90800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_SCR                    I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0_I2C9_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0                     MK_ADDR_CONST(0x908010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_SCR                         I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0_I2C9_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0                   MK_ADDR_CONST(0x908014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_SCR                       I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0_I2C9_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0                    MK_ADDR_CONST(0x908018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_SCR                        I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0_I2C9_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0                     MK_ADDR_CONST(0x90801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_SCR                         I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0_I2C9_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0                   MK_ADDR_CONST(0x908020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_SCR                       I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0                       MK_ADDR_CONST(0x908024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_SCR                   I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0_I2C9_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0                       MK_ADDR_CONST(0x908028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_SCR                   I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0_I2C9_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0                       MK_ADDR_CONST(0x90802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_SCR                   I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0_I2C9_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0                    MK_ADDR_CONST(0x908030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_SCR                        I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0_I2C9_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0                     MK_ADDR_CONST(0x908034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_SCR                         I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0_I2C9_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0                      MK_ADDR_CONST(0x90f000)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0                      MK_ADDR_CONST(0x90f004)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C9_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0x910000

// Register CLK_RST_CONTROLLER_RST_DEV_I2C12_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0                      MK_ADDR_CONST(0x920000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0                  MK_ADDR_CONST(0x920004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0                  MK_ADDR_CONST(0x920008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0                  MK_ADDR_CONST(0x921000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0                      MK_ADDR_CONST(0x921004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0                      MK_ADDR_CONST(0x921008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0                  MK_ADDR_CONST(0x922000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0                   MK_ADDR_CONST(0x923000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_RESET_VAL                         MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_RESET_MASK                        MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_READ_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_WRITE_MASK                        MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_CLK_M                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C13_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0                      MK_ADDR_CONST(0x930000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0                  MK_ADDR_CONST(0x930004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0                  MK_ADDR_CONST(0x930008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0                  MK_ADDR_CONST(0x931000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0                      MK_ADDR_CONST(0x931004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0                      MK_ADDR_CONST(0x931008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0                  MK_ADDR_CONST(0x932000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0                   MK_ADDR_CONST(0x933000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_RESET_VAL                         MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_RESET_MASK                        MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_READ_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_WRITE_MASK                        MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_CLK_M                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C14_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0                      MK_ADDR_CONST(0x940000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0                  MK_ADDR_CONST(0x940004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0                  MK_ADDR_CONST(0x940008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0                  MK_ADDR_CONST(0x941000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0                      MK_ADDR_CONST(0x941004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0                      MK_ADDR_CONST(0x941008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0                  MK_ADDR_CONST(0x942000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0                   MK_ADDR_CONST(0x943000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_RESET_VAL                         MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_RESET_MASK                        MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_READ_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_WRITE_MASK                        MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_CLK_M                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM1_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0                       MK_ADDR_CONST(0x950000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0                   MK_ADDR_CONST(0x950004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0                   MK_ADDR_CONST(0x950008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0                   MK_ADDR_CONST(0x951000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0                       MK_ADDR_CONST(0x951004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0                       MK_ADDR_CONST(0x951008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0                   MK_ADDR_CONST(0x952000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0                    MK_ADDR_CONST(0x953000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x953004

// Register CLK_RST_CONTROLLER_RST_DEV_PWM2_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0                       MK_ADDR_CONST(0x960000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0                   MK_ADDR_CONST(0x960004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0                   MK_ADDR_CONST(0x960008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0                   MK_ADDR_CONST(0x961000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0                       MK_ADDR_CONST(0x961004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0                       MK_ADDR_CONST(0x961008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0                   MK_ADDR_CONST(0x962000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0                    MK_ADDR_CONST(0x963000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x963004

// Register CLK_RST_CONTROLLER_RST_DEV_PWM3_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0                       MK_ADDR_CONST(0x970000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0                   MK_ADDR_CONST(0x970004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0                   MK_ADDR_CONST(0x970008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0                   MK_ADDR_CONST(0x971000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0                       MK_ADDR_CONST(0x971004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0                       MK_ADDR_CONST(0x971008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0                   MK_ADDR_CONST(0x972000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0                    MK_ADDR_CONST(0x973000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x973004

// Reserved address 0x980000

// Register CLK_RST_CONTROLLER_RST_DEV_PWM5_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0                       MK_ADDR_CONST(0x990000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0                   MK_ADDR_CONST(0x990004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0                   MK_ADDR_CONST(0x990008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0                   MK_ADDR_CONST(0x991000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0                       MK_ADDR_CONST(0x991004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0                       MK_ADDR_CONST(0x991008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0                   MK_ADDR_CONST(0x992000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0                    MK_ADDR_CONST(0x993000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x993004

// Register CLK_RST_CONTROLLER_RST_DEV_PWM6_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0                       MK_ADDR_CONST(0x9a0000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0                   MK_ADDR_CONST(0x9a0004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0                   MK_ADDR_CONST(0x9a0008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0                   MK_ADDR_CONST(0x9a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0                       MK_ADDR_CONST(0x9a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0                       MK_ADDR_CONST(0x9a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0                   MK_ADDR_CONST(0x9a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0                    MK_ADDR_CONST(0x9a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x9a3004

// Register CLK_RST_CONTROLLER_RST_DEV_PWM7_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0                       MK_ADDR_CONST(0x9b0000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0                   MK_ADDR_CONST(0x9b0004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0                   MK_ADDR_CONST(0x9b0008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0                   MK_ADDR_CONST(0x9b1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0                       MK_ADDR_CONST(0x9b1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0                       MK_ADDR_CONST(0x9b1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0                   MK_ADDR_CONST(0x9b2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0                    MK_ADDR_CONST(0x9b3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x9b3004

// Register CLK_RST_CONTROLLER_RST_DEV_PWM8_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0                       MK_ADDR_CONST(0x9c0000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0                   MK_ADDR_CONST(0x9c0004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0                   MK_ADDR_CONST(0x9c0008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0                   MK_ADDR_CONST(0x9c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0                       MK_ADDR_CONST(0x9c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0                       MK_ADDR_CONST(0x9c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0                   MK_ADDR_CONST(0x9c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0                    MK_ADDR_CONST(0x9c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x9c3004

// Register CLK_RST_CONTROLLER_RST_DEV_UARTE_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0                      MK_ADDR_CONST(0x9d0000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0                  MK_ADDR_CONST(0x9d0004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0                  MK_ADDR_CONST(0x9d0008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0                  MK_ADDR_CONST(0x9d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0                      MK_ADDR_CONST(0x9d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0                      MK_ADDR_CONST(0x9d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0                  MK_ADDR_CONST(0x9d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0                   MK_ADDR_CONST(0x9d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_RESET_VAL                         MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_RESET_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_READ_MASK                         MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_WRITE_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTF_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0                      MK_ADDR_CONST(0x9e0000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0                  MK_ADDR_CONST(0x9e0004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0                  MK_ADDR_CONST(0x9e0008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0                  MK_ADDR_CONST(0x9e1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0                      MK_ADDR_CONST(0x9e1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0                      MK_ADDR_CONST(0x9e1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0                  MK_ADDR_CONST(0x9e2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0                   MK_ADDR_CONST(0x9e3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_RESET_VAL                         MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_RESET_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_READ_MASK                         MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_WRITE_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0                 MK_ADDR_CONST(0x9f0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0                     MK_ADDR_CONST(0x9f0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0                     MK_ADDR_CONST(0x9f0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0                 MK_ADDR_CONST(0x9f1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0                  MK_ADDR_CONST(0x9f2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_RESET_VAL                        MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_CLK_S                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_CLK_M                     MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0                    MK_ADDR_CONST(0xa00000)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_SCR                        BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_RESET_VAL                  MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_RESET_MASK                         MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_READ_MASK                  MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_WRITE_MASK                         MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_REF_ENABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_REF_DISABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_RANGE                      24:20
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_RANGE                      17:10
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_DEFAULT                    MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0                  MK_ADDR_CONST(0xa00004)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_RESET_VAL                        MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_RESET_MASK                       MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_READ_MASK                        MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_WRITE_MASK                       MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_INIT_ENUM                    PLLBPMPCAM_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_PLLBPMPCAM_CLK_OUT_PTO_OBS                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTO_ROOT_CLK_SEL_PLLBPMPCAM_CLK_OUT_PTO_DIV2                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_RANGE                 19:4
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_DEFAULT                       MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_RANGE                     3:3
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_FO                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_RANGE                       1:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0                  MK_ADDR_CONST(0xa00008)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_RESET_VAL                        MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_RESET_MASK                       MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_READ_MASK                        MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_WRITE_MASK                       MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_ON                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_RANGE                      19:16
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0                  MK_ADDR_CONST(0xa0000c)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_RESET_VAL                        MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_RESET_MASK                       MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_READ_MASK                        MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_WRITE_MASK                       MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_RANGE                      31:24
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_RANGE                        23:16
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_DEFAULT                      MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_RANGE                 4:4
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_RANGE                        2:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_DEFAULT                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0                  MK_ADDR_CONST(0xa00010)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_RESET_VAL                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_RESET_MASK                       MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_READ_MASK                        MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_WRITE_MASK                       MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_RANGE                    25:24
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_RANGE                   23:8
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_RANGE                    5:4
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_RANGE                      3:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0                  MK_ADDR_CONST(0xa00014)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_RESET_VAL                        MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_RESET_MASK                       MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_READ_MASK                        MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_WRITE_MASK                       MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF__PROD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_RANGE                   27:25
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_RANGE                   24:22
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_MSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_RANGE                   21:19
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_DEFAULT                 MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_RANGE                 18:16
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_DEFAULT                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0                     MK_ADDR_CONST(0xa01000)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0                       MK_ADDR_CONST(0xa10000)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0                   MK_ADDR_CONST(0xa10004)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0                   MK_ADDR_CONST(0xa10008)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_RESET_MASK                        MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_READ_MASK                         MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0                    MK_ADDR_CONST(0xa1000c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SCR                        BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0                        MK_ADDR_CONST(0xa10010)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SCR                    BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0                        MK_ADDR_CONST(0xa10014)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_SCR                    BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0                   MK_ADDR_CONST(0xa10018)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0                       MK_ADDR_CONST(0xa1001c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0                       MK_ADDR_CONST(0xa10020)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0                   MK_ADDR_CONST(0xa10024)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0                       MK_ADDR_CONST(0xa10028)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0                       MK_ADDR_CONST(0xa1002c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0                  MK_ADDR_CONST(0xa10030)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SCR                      BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0                      MK_ADDR_CONST(0xa10034)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0                      MK_ADDR_CONST(0xa10038)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0                   MK_ADDR_CONST(0xa1003c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0                       MK_ADDR_CONST(0xa10040)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0                       MK_ADDR_CONST(0xa10044)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0                   MK_ADDR_CONST(0xa10048)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0                       MK_ADDR_CONST(0xa1004c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0                       MK_ADDR_CONST(0xa10050)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0                   MK_ADDR_CONST(0xa11000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_RESET_VAL                         MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_RESET_MASK                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_READ_MASK                         MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_WRITE_MASK                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0                       MK_ADDR_CONST(0xa11004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_RESET_VAL                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_RESET_MASK                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_READ_MASK                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_WRITE_MASK                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0                       MK_ADDR_CONST(0xa11008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_RESET_VAL                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_RESET_MASK                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_READ_MASK                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0                   MK_ADDR_CONST(0xa12000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_RESET_MASK                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_READ_MASK                         MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_WRITE_MASK                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_RANGE                   2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_RANGE                       1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0                    MK_ADDR_CONST(0xa13000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_SCR                        BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_RESET_MASK                         MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_READ_MASK                  MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_PLLC2_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_PLLC3_OUT0                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_CLK_DFLL_BPMP                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_RANGE                      17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NIC_RATE_0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0                      MK_ADDR_CONST(0xa13004)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_SCR                  BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_RESET_VAL                    MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_RESET_MASK                   MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_READ_MASK                    MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_WRITE_MASK                   MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_RANGE                        4:4
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_RANGE                  1:0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0                 MK_ADDR_CONST(0xa13008)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_SCR                     BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_RESET_VAL                       MK_MASK_CONST(0x40)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_RANGE                   15:0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_DEFAULT                 MK_MASK_CONST(0x40)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0                       MK_ADDR_CONST(0xa18000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_SCR                   BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0                        MK_ADDR_CONST(0xa18004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_SCR                    BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0                     MK_ADDR_CONST(0xa18008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_SCR                         BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0                    MK_ADDR_CONST(0xa1800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_SCR                        BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0                 MK_ADDR_CONST(0xa18010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_SCR                     BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0_BPMP_CPU_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0                       MK_ADDR_CONST(0xa18014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_SCR                   BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0                        MK_ADDR_CONST(0xa18018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_SCR                    BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0                 MK_ADDR_CONST(0xa1801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_SCR                     BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_RESET_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_READ_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_WRITE_MASK                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0_BPMP_CPU_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0                       MK_ADDR_CONST(0xa18020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_SCR                   BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_RESET_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_READ_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_WRITE_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0                   MK_ADDR_CONST(0xa18024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_SCR                       BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0                   MK_ADDR_CONST(0xa18028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_SCR                       BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0                   MK_ADDR_CONST(0xa1802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_SCR                       BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0_BPMP_CPU_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0                        MK_ADDR_CONST(0xa18030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_SCR                    BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0_BPMP_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0                 MK_ADDR_CONST(0xa18034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_SCR                     BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0_BPMP_CPU_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0                       MK_ADDR_CONST(0xa20000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0                   MK_ADDR_CONST(0xa20004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0                   MK_ADDR_CONST(0xa20008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0                       MK_ADDR_CONST(0xa21000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_SCR                   0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0                        MK_ADDR_CONST(0xa22000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_SCR                    BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_RESET_MASK                     MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_READ_MASK                      MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_CLK_DFLL_BPMP                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_RANGE                      17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0                       MK_ADDR_CONST(0xa28000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_SCR                   BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0                        MK_ADDR_CONST(0xa28004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_SCR                    BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0_BPMP_APB_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0                     MK_ADDR_CONST(0xa28008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_SCR                         BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0                    MK_ADDR_CONST(0xa2800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_SCR                        BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0                 MK_ADDR_CONST(0xa28010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_SCR                     BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0_BPMP_APB_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0                       MK_ADDR_CONST(0xa28014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_SCR                   BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0                        MK_ADDR_CONST(0xa28018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_SCR                    BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0_BPMP_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0                 MK_ADDR_CONST(0xa2801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_SCR                     BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_RESET_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_READ_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_WRITE_MASK                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0_BPMP_APB_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0                       MK_ADDR_CONST(0xa28020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_SCR                   BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_RESET_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_READ_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_WRITE_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0                   MK_ADDR_CONST(0xa28024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_SCR                       BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0                   MK_ADDR_CONST(0xa28028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_SCR                       BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0                   MK_ADDR_CONST(0xa2802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_SCR                       BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0_BPMP_APB_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0                        MK_ADDR_CONST(0xa28030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_SCR                    BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0_BPMP_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0                 MK_ADDR_CONST(0xa28034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_SCR                     BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0_BPMP_APB_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0                      MK_ADDR_CONST(0xa30000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_SCR                  BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0                  MK_ADDR_CONST(0xa30004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SCR                      BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0                  MK_ADDR_CONST(0xa30008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_SCR                      BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0                      MK_ADDR_CONST(0xa31000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0                       MK_ADDR_CONST(0xa32000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SCR                   BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_ACTMON_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0                     MK_ADDR_CONST(0xa40000)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SCR                         BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_RESET_VAL                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0                 MK_ADDR_CONST(0xa40004)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_RESET_VAL                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0                 MK_ADDR_CONST(0xa40008)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_RESET_VAL                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0                 MK_ADDR_CONST(0xa41000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0                     MK_ADDR_CONST(0xa41004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SCR                         BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0                     MK_ADDR_CONST(0xa41008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_SCR                         BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0                 MK_ADDR_CONST(0xa42000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0                  MK_ADDR_CONST(0xa43000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_SCR                      BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0                        MK_ADDR_CONST(0xa50000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_SCR                    BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0                    MK_ADDR_CONST(0xa50004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SCR                        BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0                    MK_ADDR_CONST(0xa50008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_SCR                        BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0                        MK_ADDR_CONST(0xa51000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0                 MK_ADDR_CONST(0xa52000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_SCR                     BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_RESET_VAL                       MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_RESET_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_READ_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_INIT_ENUM                       CLK_S
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0                     MK_ADDR_CONST(0xa60000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_SCR                         BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_READ_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_WRITE_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_DFLL_BPMP                       MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0                      MK_ADDR_CONST(0xa60004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                  BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_BPMP                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0                       MK_ADDR_CONST(0xa60008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0                       MK_ADDR_CONST(0xa6000c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_READ_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0                    MK_ADDR_CONST(0xa60010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCR                        BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0                        MK_ADDR_CONST(0xa60014)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_SCR                    BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0                 MK_ADDR_CONST(0xa60018)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                     BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0                  MK_ADDR_CONST(0xa6001c)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0                  MK_ADDR_CONST(0xa60020)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0                       MK_ADDR_CONST(0xa60024)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0                 MK_ADDR_CONST(0xa60028)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_SCR                     BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_RESET_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_READ_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_WRITE_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_CLK_DFLL_BPMP                       MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0                  MK_ADDR_CONST(0xa6002c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_BPMP                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0                   MK_ADDR_CONST(0xa60030)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0                   MK_ADDR_CONST(0xa60034)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_READ_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0                        MK_ADDR_CONST(0xa60038)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_SCR                    BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0                 MK_ADDR_CONST(0xa6003c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_SCR                     BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_RESET_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_READ_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_CLK_DFLL_BPMP                       MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0                  MK_ADDR_CONST(0xa60040)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCR                      BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_BPMP                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0                   MK_ADDR_CONST(0xa60044)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0                   MK_ADDR_CONST(0xa60048)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0                        MK_ADDR_CONST(0xa6004c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCR                    BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0                    MK_ADDR_CONST(0xa60050)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_SCR                        BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0                     MK_ADDR_CONST(0xa60054)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_SCR                         BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0                      MK_ADDR_CONST(0xa60058)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0                      MK_ADDR_CONST(0xa6005c)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0                   MK_ADDR_CONST(0xa60060)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0                     MK_ADDR_CONST(0xa60064)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_SCR                         BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_CLK_DFLL_BPMP                       MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0                      MK_ADDR_CONST(0xa60068)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_BPMP                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0                       MK_ADDR_CONST(0xa6006c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0                       MK_ADDR_CONST(0xa60070)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0                    MK_ADDR_CONST(0xa60074)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_SCR                        BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0                  MK_ADDR_CONST(0xa60078)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_SCR                      BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_RESET_MASK                       MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_READ_MASK                        MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_WRITE_MASK                       MK_MASK_CONST(0x40000007)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_RANGE                    31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_RANGE                    30:30
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_RANGE                  2:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0                     MK_ADDR_CONST(0xa6007c)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_SCR                         BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_RESET_VAL                   MK_MASK_CONST(0x1c30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_RESET_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_READ_MASK                   MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_WRITE_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_RANGE                     12:12
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_RANGE                 11:11
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_RANGE                   10:10
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_RANGE                       9:9
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_RANGE                     8:8
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_RANGE                       7:7
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_RANGE                 6:6
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_RANGE                 5:5
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_RANGE                     4:4
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_RANGE                     3:3
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_RANGE                  1:1
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_RANGE                    0:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0                       MK_ADDR_CONST(0xa60080)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_RESET_VAL                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_RESET_MASK                    MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_READ_MASK                     MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_WRITE_MASK                    MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_RANGE                        31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_RANGE                        30:30
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_RANGE                     29:29
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_FIELD                  MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_RANGE                  11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0                  MK_ADDR_CONST(0xa60084)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_RESET_VAL                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_RESET_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_READ_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_WRITE_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_RANGE                   31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_FIELD                  MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_RANGE                  11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_DEFAULT_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0                 MK_ADDR_CONST(0xa60088)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_SCR                     BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_VAL                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_READ_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_WRITE_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_FIELD                        MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_RANGE                        11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_DEFAULT                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_DEFAULT_MASK                 MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0                      MK_ADDR_CONST(0xa6008c)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCR                  BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_READ_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_WRITE_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_RANGE                    31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_FIELD                        MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_RANGE                        11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_DEFAULT                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_DEFAULT_MASK                 MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0                 MK_ADDR_CONST(0xa60090)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_SCR                     BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_VAL                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_MASK                      MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_READ_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_WRITE_MASK                      MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_RANGE                 31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_FIELD                     MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_RANGE                     11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_DEFAULT_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0                   MK_ADDR_CONST(0xa60094)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_RESET_VAL                         MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_READ_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_FIELD                      MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_RANGE                      5:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT                    MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0                  MK_ADDR_CONST(0xa60098)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_READ_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_WRITE_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_RANGE                      3:3
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_RANGE                  2:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0                    MK_ADDR_CONST(0xa6009c)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_SCR                        BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_RESET_MASK                         MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_READ_MASK                  MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_RANGE                       31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_RANGE                      30:30
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_RANGE                      7:4
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0                     MK_ADDR_CONST(0xa600a0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_SCR                         0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_RESET_MASK                  MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_READ_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_RANGE                       31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_FIELD                   MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_RANGE                   11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0                    MK_ADDR_CONST(0xa70000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_SCR                        BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_RESET_VAL                  MK_MASK_CONST(0x82)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_RESET_MASK                         MK_MASK_CONST(0x300fb)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_READ_MASK                  MK_MASK_CONST(0x300fb)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_WRITE_MASK                         MK_MASK_CONST(0xfb)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                     17:17
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_RANGE                     16:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_RANGE                     7:7
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_RANGE                        6:6
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                        5:5
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                       4:4
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_RANGE                    3:3
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0                   MK_ADDR_CONST(0xa70004)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_SCR                       BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_RESET_VAL                         MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_RESET_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_READ_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_WRITE_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                      31:28
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                    MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                      27:24
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_RANGE                       20:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_RANGE                       4:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_DEFAULT                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0                    MK_ADDR_CONST(0xa70008)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_SCR                        BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_RESET_VAL                  MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_RESET_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_READ_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_WRITE_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                     20:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                   MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                       15:8
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_RANGE                     7:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0                    MK_ADDR_CONST(0xa7000c)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_SCR                        BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                       31:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0                   MK_ADDR_CONST(0xa70010)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_SCR                       BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_RESET_VAL                         MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_RANGE                      31:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_RANGE                   15:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0                   MK_ADDR_CONST(0xa70014)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_SCR                       BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_RESET_VAL                         MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_RESET_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_READ_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_WRITE_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                        31:28
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                    27:24
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                        23:20
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                 19:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                       7:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0                    MK_ADDR_CONST(0xa70018)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_SCR                        BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_RESET_MASK                         MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_READ_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_RANGE                   15:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0                       MK_ADDR_CONST(0xa7001c)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_SCR                   BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_RESET_VAL                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_RESET_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_READ_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_WRITE_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_RANGE                    31:24
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_RANGE                   23:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0                        MK_ADDR_CONST(0xa70020)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_SCR                    BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                    MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                    7:3
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                     2:1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_RANGE                       0:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0                       MK_ADDR_CONST(0xa70024)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_SCR                   BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_READ_MASK                     MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                    13:13
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                     12:12
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_RANGE                  11:3
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_DEFAULT                        MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                  2:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0_BPMP_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xa70028

// Reserved address 0xa7002c

// Reserved address 0xa70030

// Reserved address 0xa70034

// Reserved address 0xa70038

// Reserved address 0xa7003c

// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0                  MK_ADDR_CONST(0xa70040)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_SCR                      BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0                  MK_ADDR_CONST(0xa70044)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_SCR                      BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_READ_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0                   MK_ADDR_CONST(0xa70048)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_SCR                       BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_RESET_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_READ_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0                   MK_ADDR_CONST(0xa7004c)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_RESET_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_READ_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0                      MK_ADDR_CONST(0xa70050)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_SCR                  0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_RESET_MASK                   MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_READ_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_RANGE                     16:8
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                   7:4
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0                 MK_ADDR_CONST(0xa70054)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_RESET_VAL                       MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_RESET_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_READ_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_WRITE_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                  25:25
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                   19:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                    12:12
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_RANGE                      8:8
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_RANGE                       2:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0                 MK_ADDR_CONST(0xa70058)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                     29:28
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                     23:20
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                       12:4
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                       3:2
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                    1:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0                 MK_ADDR_CONST(0xa7005c)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_RESET_MASK                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_READ_MASK                       MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                        3:3
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xa70060

// Reserved address 0xa70064

// Reserved address 0xa70068

// Register CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0                       MK_ADDR_CONST(0xa7006c)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_SCR                   BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_RESET_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_READ_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_RANGE                     31:28
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                   27:27
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_RANGE                        25:25
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_RANGE                      24:24
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                    19:16
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                 15:15
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                        2:0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0                      MK_ADDR_CONST(0xa70070)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_SCR                  BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_FIELD                    MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0                      MK_ADDR_CONST(0xa70074)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_SCR                  BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_RANGE                    3:0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xa70078

// Register CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0                       MK_ADDR_CONST(0xa7007c)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_SCR                   0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_RANGE                      3:3
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_INIT_ENUM                  DFLL_BPMP_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_DFLL_BPMP_CLK_OUT_PTO_OBS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_NAFLLBPMP_PTO_ROOT_CLK_SEL_DFLL_BPMP_CLK_OUT_PTO_DIV2                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_RANGE                        2:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_DEFAULT                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_INIT_ENUM                    CLK_NULL
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_DFLL_BPMP_CLK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_DFLL_BPMP_PRE_SKP_CLK                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_DFLL_BPMP_FLL_UPD_CLK                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_ADC_SOC_REF_BPMP_CLK                 MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_BPMP_APB_LUT_BPMP_CLK                        MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_OSC_DIV_CLK                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0_BPMP_PTS_CLK_NULL                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0                  MK_ADDR_CONST(0xa80000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_SCR                      BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_READ_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V0_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_RANGE                   3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_V1_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_RANGE                   5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_CV_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0                      MK_ADDR_CONST(0xa80004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SCR                  BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_RESET_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_READ_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_WRITE_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V0_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_RANGE                   3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_V1_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_RANGE                   5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_CV_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0                      MK_ADDR_CONST(0xa80008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_SCR                  BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_RESET_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_READ_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V0_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_RANGE                   3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_V1_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_RANGE                   5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_CV_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0                  MK_ADDR_CONST(0xa81000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_READ_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_RANGE                 1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_RANGE                  2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_RANGE                  3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_V1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_RANGE                 4:4
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_RANGE                  5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_CV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0                   MK_ADDR_CONST(0xa82000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SCR                       BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_RESET_VAL                         MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_JTAG_TCK_IB                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_CLK_M                       MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Reserved address 0xa90000

// Reserved address 0xaa0000

// Reserved address 0xab0000

// Reserved address 0xac0000

// Reserved address 0xad0000

// Register CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0                      MK_ADDR_CONST(0xae0000)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0_CLK_SPARE_REG_BPMP_SHARED_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0                     MK_ADDR_CONST(0xae1000)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_SCR                         BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0_CLK_SPARE_REG_BPMP_PRIVATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0                       MK_ADDR_CONST(0xae2000)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_SCR                   BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0_CLK_SPARE_REG_BPMP_THERM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0                        MK_ADDR_CONST(0xae3000)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_SCR                    BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0_CLK_SPARE_REG_BPMP_DVFS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0                       MK_ADDR_CONST(0xae4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_SCR                   BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0_CLK_SPARE_REG_BPMP_SIMON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0                       MK_ADDR_CONST(0xae5000)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_SCR                   BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0_CLK_SPARE_REG_BPMP_BPMP_CPU_FMON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0                       MK_ADDR_CONST(0xae6000)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_SCR                   BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0_CLK_SPARE_REG_BPMP_BPMP_APB_FMON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0                    MK_ADDR_CONST(0xaef000)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SCR                        0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0                   MK_ADDR_CONST(0xaef004)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SCR                       0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0                     MK_ADDR_CONST(0xaef008)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SCR                         0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0                      MK_ADDR_CONST(0xaef00c)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SCR                  0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0                     MK_ADDR_CONST(0xaef010)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SCR                         0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0                  MK_ADDR_CONST(0xaef014)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0                  MK_ADDR_CONST(0xaef018)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0                        MK_ADDR_CONST(0xb00000)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0                    MK_ADDR_CONST(0xb00004)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0                    MK_ADDR_CONST(0xb00008)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_RESET_MASK                         MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_READ_MASK                  MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0                    MK_ADDR_CONST(0xb0000c)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SCR                        AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0                        MK_ADDR_CONST(0xb00010)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SCR                    AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0                        MK_ADDR_CONST(0xb00014)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_SCR                    AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0                   MK_ADDR_CONST(0xb00018)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SCR                       AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0                       MK_ADDR_CONST(0xb0001c)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SCR                   AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0                       MK_ADDR_CONST(0xb00020)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_SCR                   AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0                 MK_ADDR_CONST(0xb00024)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SCR                     AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0                     MK_ADDR_CONST(0xb00028)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0                     MK_ADDR_CONST(0xb0002c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOPM_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0                       MK_ADDR_CONST(0xb00030)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0                   MK_ADDR_CONST(0xb00034)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0                   MK_ADDR_CONST(0xb00038)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOVC_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0                       MK_ADDR_CONST(0xb0003c)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0                   MK_ADDR_CONST(0xb00040)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0                   MK_ADDR_CONST(0xb00044)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0                    MK_ADDR_CONST(0xb00048)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0                        MK_ADDR_CONST(0xb0004c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0                        MK_ADDR_CONST(0xb00050)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0                   MK_ADDR_CONST(0xb00054)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SCR                       AON_SCR_GPIO_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0                       MK_ADDR_CONST(0xb00058)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SCR                   AON_SCR_GPIO_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0                       MK_ADDR_CONST(0xb0005c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_SCR                   AON_SCR_GPIO_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0                    MK_ADDR_CONST(0xb00060)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SCR                        AON_SCR_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0                        MK_ADDR_CONST(0xb00064)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SCR                    AON_SCR_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0                        MK_ADDR_CONST(0xb00068)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_SCR                    AON_SCR_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0                    MK_ADDR_CONST(0xb01000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_RESET_VAL                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0                        MK_ADDR_CONST(0xb01004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_RESET_VAL                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0                        MK_ADDR_CONST(0xb01008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_RESET_VAL                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0                    MK_ADDR_CONST(0xb02000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_RANGE                     1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0                     MK_ADDR_CONST(0xb03000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_RESET_MASK                  MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_READ_MASK                   MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_INIT_ENUM                       OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_OSC_UNDIV                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_RANGE                        17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_NIC_RATE_0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0                       MK_ADDR_CONST(0xb03004)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_RESET_VAL                     MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_RESET_MASK                    MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_READ_MASK                     MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_WRITE_MASK                    MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_RANGE                  4:4
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_RANGE                    1:0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0                 MK_ADDR_CONST(0xb03008)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_SCR                     AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_RESET_VAL                       MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_WRITE_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_RANGE                    31:31
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_RANGE                      7:0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_DEFAULT                    MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0                  MK_ADDR_CONST(0xb0300c)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_SCR                      AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_RESET_VAL                        MK_MASK_CONST(0x40)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_RANGE                     15:0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_DEFAULT                   MK_MASK_CONST(0x40)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0                        MK_ADDR_CONST(0xb08000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_SCR                    AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0                 MK_ADDR_CONST(0xb08004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_SCR                     AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0_AON_CPU_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0                      MK_ADDR_CONST(0xb08008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_SCR                  AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0                     MK_ADDR_CONST(0xb0800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_SCR                         AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0                  MK_ADDR_CONST(0xb08010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_SCR                      AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0_AON_CPU_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0                        MK_ADDR_CONST(0xb08014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_SCR                    AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0                 MK_ADDR_CONST(0xb08018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_SCR                     AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0_AON_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0                  MK_ADDR_CONST(0xb0801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_SCR                      AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_WRITE_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0_AON_CPU_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0                        MK_ADDR_CONST(0xb08020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_SCR                    AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_RESET_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_READ_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_WRITE_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0                    MK_ADDR_CONST(0xb08024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_SCR                        AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0                    MK_ADDR_CONST(0xb08028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_SCR                        AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0                    MK_ADDR_CONST(0xb0802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_SCR                        AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0_AON_CPU_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0                 MK_ADDR_CONST(0xb08030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_SCR                     AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0_AON_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0                  MK_ADDR_CONST(0xb08034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_SCR                      AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0_AON_CPU_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN1_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0                       MK_ADDR_CONST(0xb10000)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0                   MK_ADDR_CONST(0xb10004)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0                   MK_ADDR_CONST(0xb10008)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0                   MK_ADDR_CONST(0xb11000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_RESET_VAL                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0                       MK_ADDR_CONST(0xb11004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_RESET_VAL                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0                       MK_ADDR_CONST(0xb11008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_RESET_VAL                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0                   MK_ADDR_CONST(0xb12000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0                    MK_ADDR_CONST(0xb13000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_SCR                        AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CAN1_CORE_RATE_0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0                     MK_ADDR_CONST(0xb13004)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_SCR                         AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_RESET_VAL                   MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_RESET_MASK                  MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_READ_MASK                   MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_WRITE_MASK                  MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_RANGE                      4:4
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_RANGE                        1:0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0                   MK_ADDR_CONST(0xb18000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_SCR                       CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0_CAN1_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0                    MK_ADDR_CONST(0xb18004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_SCR                        CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0_CAN1_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0                 MK_ADDR_CONST(0xb18008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_SCR                     CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0                        MK_ADDR_CONST(0xb1800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_SCR                    CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0_CAN1_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0                     MK_ADDR_CONST(0xb18010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_SCR                         CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0_CAN1_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0                   MK_ADDR_CONST(0xb18014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_SCR                       CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0_CAN1_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0                    MK_ADDR_CONST(0xb18018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_SCR                        CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0_CAN1_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0                     MK_ADDR_CONST(0xb1801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_SCR                         CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0_CAN1_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0                   MK_ADDR_CONST(0xb18020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_SCR                       CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0                       MK_ADDR_CONST(0xb18024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_SCR                   CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0_CAN1_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0                       MK_ADDR_CONST(0xb18028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_SCR                   CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0_CAN1_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0                       MK_ADDR_CONST(0xb1802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_SCR                   CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0_CAN1_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0                    MK_ADDR_CONST(0xb18030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_SCR                        CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0_CAN1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0                     MK_ADDR_CONST(0xb18034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_SCR                         CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0_CAN1_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN2_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0                       MK_ADDR_CONST(0xb20000)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0                   MK_ADDR_CONST(0xb20004)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0                   MK_ADDR_CONST(0xb20008)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0                   MK_ADDR_CONST(0xb21000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_RESET_VAL                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0                       MK_ADDR_CONST(0xb21004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_RESET_VAL                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0                       MK_ADDR_CONST(0xb21008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_RESET_VAL                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0                   MK_ADDR_CONST(0xb22000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0                    MK_ADDR_CONST(0xb23000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_SCR                        AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CAN2_CORE_RATE_0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0                     MK_ADDR_CONST(0xb23004)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_SCR                         AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_RESET_VAL                   MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_RESET_MASK                  MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_READ_MASK                   MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_WRITE_MASK                  MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_RANGE                      4:4
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_RANGE                        1:0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0                   MK_ADDR_CONST(0xb28000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_SCR                       CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0_CAN2_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0                    MK_ADDR_CONST(0xb28004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_SCR                        CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0_CAN2_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0                 MK_ADDR_CONST(0xb28008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_SCR                     CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0                        MK_ADDR_CONST(0xb2800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_SCR                    CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0_CAN2_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0                     MK_ADDR_CONST(0xb28010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_SCR                         CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0_CAN2_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0                   MK_ADDR_CONST(0xb28014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_SCR                       CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0_CAN2_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0                    MK_ADDR_CONST(0xb28018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_SCR                        CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0_CAN2_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0                     MK_ADDR_CONST(0xb2801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_SCR                         CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0_CAN2_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0                   MK_ADDR_CONST(0xb28020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_SCR                       CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0                       MK_ADDR_CONST(0xb28024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_SCR                   CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0_CAN2_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0                       MK_ADDR_CONST(0xb28028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_SCR                   CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0_CAN2_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0                       MK_ADDR_CONST(0xb2802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_SCR                   CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0_CAN2_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0                    MK_ADDR_CONST(0xb28030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_SCR                        CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0_CAN2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0                     MK_ADDR_CONST(0xb28034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_SCR                         CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0_CAN2_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0                        MK_ADDR_CONST(0xb30000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0                    MK_ADDR_CONST(0xb30004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0                    MK_ADDR_CONST(0xb30008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0                        MK_ADDR_CONST(0xb31000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0                 MK_ADDR_CONST(0xb32000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_SCR                     AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_RESET_MASK                      MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_READ_MASK                       MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_INIT_ENUM                       OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_OSC_UNDIV                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_RANGE                        17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0                        MK_ADDR_CONST(0xb38000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_SCR                    AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0_AON_APB_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0                 MK_ADDR_CONST(0xb38004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_SCR                     AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0_AON_APB_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0                      MK_ADDR_CONST(0xb38008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_SCR                  AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0                     MK_ADDR_CONST(0xb3800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_SCR                         AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0_AON_APB_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0                  MK_ADDR_CONST(0xb38010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_SCR                      AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0_AON_APB_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0                        MK_ADDR_CONST(0xb38014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_SCR                    AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0                 MK_ADDR_CONST(0xb38018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_SCR                     AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0_AON_APB_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0                  MK_ADDR_CONST(0xb3801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_SCR                      AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_WRITE_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0_AON_APB_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0                        MK_ADDR_CONST(0xb38020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_SCR                    AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_RESET_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_READ_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_WRITE_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0                    MK_ADDR_CONST(0xb38024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_SCR                        AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0_AON_APB_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0                    MK_ADDR_CONST(0xb38028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_SCR                        AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0_AON_APB_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0                    MK_ADDR_CONST(0xb3802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_SCR                        AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0_AON_APB_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0                 MK_ADDR_CONST(0xb38030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_SCR                     AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0_AON_APB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0                  MK_ADDR_CONST(0xb38034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_SCR                      AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0_AON_APB_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTC_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0                      MK_ADDR_CONST(0xb40000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SCR                  AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0                  MK_ADDR_CONST(0xb40004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SCR                      AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0                  MK_ADDR_CONST(0xb40008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_SCR                      AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0                  MK_ADDR_CONST(0xb41000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_SCR                      AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0                      MK_ADDR_CONST(0xb41004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SCR                  AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0                      MK_ADDR_CONST(0xb41008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_SCR                  AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0                  MK_ADDR_CONST(0xb42000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_SCR                      AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0                   MK_ADDR_CONST(0xb43000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SCR                       AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_VAL                         MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_READ_MASK                         MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WRITE_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_INIT_ENUM                   OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLC4_MUXED                 MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTG_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0                      MK_ADDR_CONST(0xb50000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SCR                  AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0                  MK_ADDR_CONST(0xb50004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SCR                      AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0                  MK_ADDR_CONST(0xb50008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_SCR                      AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0                  MK_ADDR_CONST(0xb51000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_SCR                      AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0                      MK_ADDR_CONST(0xb51004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SCR                  AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0                      MK_ADDR_CONST(0xb51008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_SCR                  AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0                  MK_ADDR_CONST(0xb52000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_SCR                      AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0                   MK_ADDR_CONST(0xb53000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_SCR                       AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_RESET_VAL                         MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_RESET_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_READ_MASK                         MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_WRITE_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_INIT_ENUM                   OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0                  MK_ADDR_CONST(0xb60000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_SCR                      AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0                      MK_ADDR_CONST(0xb60004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SCR                  AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0                      MK_ADDR_CONST(0xb60008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_SCR                  AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0                  MK_ADDR_CONST(0xb61000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_SCR                      AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0                   MK_ADDR_CONST(0xb62000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_SCR                       AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_INIT_ENUM                   OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C2_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0                       MK_ADDR_CONST(0xb70000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SCR                   AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0                   MK_ADDR_CONST(0xb70004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SCR                       AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0                   MK_ADDR_CONST(0xb70008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_SCR                       AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0                   MK_ADDR_CONST(0xb71000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_SCR                       AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0                       MK_ADDR_CONST(0xb71004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SCR                   AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0                       MK_ADDR_CONST(0xb71008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_SCR                   AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0                   MK_ADDR_CONST(0xb72000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_SCR                       AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0                    MK_ADDR_CONST(0xb73000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SCR                        AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_READ_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WRITE_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0                   MK_ADDR_CONST(0xb78000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_SCR                       I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0_I2C2_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0                    MK_ADDR_CONST(0xb78004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_SCR                        I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0_I2C2_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0                 MK_ADDR_CONST(0xb78008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_SCR                     I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0                        MK_ADDR_CONST(0xb7800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_SCR                    I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0_I2C2_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0                     MK_ADDR_CONST(0xb78010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_SCR                         I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0_I2C2_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0                   MK_ADDR_CONST(0xb78014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_SCR                       I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0_I2C2_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0                    MK_ADDR_CONST(0xb78018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_SCR                        I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0_I2C2_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0                     MK_ADDR_CONST(0xb7801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_SCR                         I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0_I2C2_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0                   MK_ADDR_CONST(0xb78020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_SCR                       I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0                       MK_ADDR_CONST(0xb78024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_SCR                   I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0_I2C2_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0                       MK_ADDR_CONST(0xb78028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_SCR                   I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0_I2C2_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0                       MK_ADDR_CONST(0xb7802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_SCR                   I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0_I2C2_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0                    MK_ADDR_CONST(0xb78030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_SCR                        I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0_I2C2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0                     MK_ADDR_CONST(0xb78034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_SCR                         I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0_I2C2_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C8_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0                       MK_ADDR_CONST(0xb80000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SCR                   AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0                   MK_ADDR_CONST(0xb80004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SCR                       AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0                   MK_ADDR_CONST(0xb80008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_SCR                       AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0                   MK_ADDR_CONST(0xb81000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_SCR                       AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0                       MK_ADDR_CONST(0xb81004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SCR                   AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0                       MK_ADDR_CONST(0xb81008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_SCR                   AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0                   MK_ADDR_CONST(0xb82000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_SCR                       AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0                    MK_ADDR_CONST(0xb83000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_SCR                        AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_RESET_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_READ_MASK                  MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_WRITE_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0                   MK_ADDR_CONST(0xb88000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_SCR                       I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0_I2C8_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0                    MK_ADDR_CONST(0xb88004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_SCR                        I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0_I2C8_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0                 MK_ADDR_CONST(0xb88008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_SCR                     I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0                        MK_ADDR_CONST(0xb8800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_SCR                    I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0_I2C8_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0                     MK_ADDR_CONST(0xb88010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_SCR                         I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0_I2C8_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0                   MK_ADDR_CONST(0xb88014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_SCR                       I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0_I2C8_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0                    MK_ADDR_CONST(0xb88018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_SCR                        I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0_I2C8_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0                     MK_ADDR_CONST(0xb8801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_SCR                         I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0_I2C8_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0                   MK_ADDR_CONST(0xb88020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_SCR                       I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0                       MK_ADDR_CONST(0xb88024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_SCR                   I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0_I2C8_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0                       MK_ADDR_CONST(0xb88028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_SCR                   I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0_I2C8_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0                       MK_ADDR_CONST(0xb8802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_SCR                   I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0_I2C8_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0                    MK_ADDR_CONST(0xb88030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_SCR                        I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0_I2C8_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0                     MK_ADDR_CONST(0xb88034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_SCR                         I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0_I2C8_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C10_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0                      MK_ADDR_CONST(0xb90000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SCR                  AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0                  MK_ADDR_CONST(0xb90004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SCR                      AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0                  MK_ADDR_CONST(0xb90008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_SCR                      AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0                  MK_ADDR_CONST(0xb91000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_SCR                      AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0                      MK_ADDR_CONST(0xb91004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SCR                  AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0                      MK_ADDR_CONST(0xb91008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_SCR                  AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0                  MK_ADDR_CONST(0xb92000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_SCR                      AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0                   MK_ADDR_CONST(0xb93000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_SCR                       AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_RESET_MASK                        MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_READ_MASK                         MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_WRITE_MASK                        MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_INIT_ENUM                   OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0                  MK_ADDR_CONST(0xb98000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_SCR                      I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0_I2C10_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0                   MK_ADDR_CONST(0xb98004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_SCR                       I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0_I2C10_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0                        MK_ADDR_CONST(0xb98008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_SCR                    I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0                       MK_ADDR_CONST(0xb9800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_SCR                   I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_RESET_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_READ_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_WRITE_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0_I2C10_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0                    MK_ADDR_CONST(0xb98010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_SCR                        I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0_I2C10_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0                  MK_ADDR_CONST(0xb98014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_SCR                      I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_READ_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0_I2C10_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0                   MK_ADDR_CONST(0xb98018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_SCR                       I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0_I2C10_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0                    MK_ADDR_CONST(0xb9801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_SCR                        I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_RESET_MASK                         MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_READ_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_WRITE_MASK                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0_I2C10_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0                  MK_ADDR_CONST(0xb98020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_SCR                      I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_RESET_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_READ_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_WRITE_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0                      MK_ADDR_CONST(0xb98024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_SCR                  I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0_I2C10_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0                      MK_ADDR_CONST(0xb98028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_SCR                  I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0_I2C10_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0                      MK_ADDR_CONST(0xb9802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_SCR                  I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0_I2C10_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0                   MK_ADDR_CONST(0xb98030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_SCR                       I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0_I2C10_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0                    MK_ADDR_CONST(0xb98034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_SCR                        I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0_I2C10_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0                   MK_ADDR_CONST(0xba0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_SCR                       AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0                       MK_ADDR_CONST(0xba0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SCR                   AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0                       MK_ADDR_CONST(0xba0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_SCR                   AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0                   MK_ADDR_CONST(0xba1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_SCR                       AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0                    MK_ADDR_CONST(0xba2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_SCR                        AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0                   MK_ADDR_CONST(0xba8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_SCR                       AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0                    MK_ADDR_CONST(0xba8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_SCR                        AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0                 MK_ADDR_CONST(0xba8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_SCR                     AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0                        MK_ADDR_CONST(0xba800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_SCR                    AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0                     MK_ADDR_CONST(0xba8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_SCR                         AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0                   MK_ADDR_CONST(0xba8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_SCR                       AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0                    MK_ADDR_CONST(0xba8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_SCR                        AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0                     MK_ADDR_CONST(0xba801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_SCR                         AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0                   MK_ADDR_CONST(0xba8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_SCR                       AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0                       MK_ADDR_CONST(0xba8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_SCR                   AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0                       MK_ADDR_CONST(0xba8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_SCR                   AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0                       MK_ADDR_CONST(0xba802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_SCR                   AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0                    MK_ADDR_CONST(0xba8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_SCR                        AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0                     MK_ADDR_CONST(0xba8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_SCR                         AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0_AON_I2C_SLOW_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI2_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0                       MK_ADDR_CONST(0xbb0000)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SCR                   AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0                   MK_ADDR_CONST(0xbb0004)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SCR                       AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0                   MK_ADDR_CONST(0xbb0008)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_SCR                       AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0                   MK_ADDR_CONST(0xbb1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_SCR                       AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0                       MK_ADDR_CONST(0xbb1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SCR                   AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0                       MK_ADDR_CONST(0xbb1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_SCR                   AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0                   MK_ADDR_CONST(0xbb2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_SCR                       AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0                    MK_ADDR_CONST(0xbb3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SCR                        AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_DMIC5_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0                      MK_ADDR_CONST(0xbc0000)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SCR                  AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0                  MK_ADDR_CONST(0xbc0004)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SCR                      AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0                  MK_ADDR_CONST(0xbc0008)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_SCR                      AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0                  MK_ADDR_CONST(0xbc1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_SCR                      AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0                      MK_ADDR_CONST(0xbc1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SCR                  AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0                      MK_ADDR_CONST(0xbc1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_SCR                  AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0                  MK_ADDR_CONST(0xbc2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_SCR                      AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0                   MK_ADDR_CONST(0xbc3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_SCR                       AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_INIT_ENUM                   OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CTRL_DMIC5_0
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0                 MK_ADDR_CONST(0xbc3004)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_SCR                     0
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_RANGE                 4:0
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_DMIC5_0_DMIC5_TRIMMER_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0                      MK_ADDR_CONST(0xbd0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_SCR                  AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0                  MK_ADDR_CONST(0xbd0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SCR                      AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0                  MK_ADDR_CONST(0xbd0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_SCR                      AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0                      MK_ADDR_CONST(0xbd1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_SCR                  AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0                       MK_ADDR_CONST(0xbd2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_SCR                   AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_INIT_ENUM                   OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLAON_BASE_0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0                        MK_ADDR_CONST(0xbe0000)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_SCR                    AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_RESET_VAL                      MK_MASK_CONST(0x10108002)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_RESET_MASK                     MK_MASK_CONST(0xfdf3fcff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_READ_MASK                      MK_MASK_CONST(0xfdf3fcff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_WRITE_MASK                     MK_MASK_CONST(0xf1f3fcff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_REF_ENABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_REF_DISABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_RANGE                      24:20
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_RANGE                      17:10
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_DEFAULT                    MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_0_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0                      MK_ADDR_CONST(0xbe0004)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_RESET_VAL                    MK_MASK_CONST(0x40080000)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_RESET_MASK                   MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_READ_MASK                    MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_WRITE_MASK                   MK_MASK_CONST(0xc00ffffb)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_INIT_ENUM                    PLLAON_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_PLLAON_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTO_ROOT_CLK_SEL_PLLAON_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_RANGE                 19:4
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_DEFAULT                       MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_RANGE                     3:3
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_FO                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_RANGE                       1:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_1_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0                      MK_ADDR_CONST(0xbe0008)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_RESET_VAL                    MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_RESET_MASK                   MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_READ_MASK                    MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_WRITE_MASK                   MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_ON                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_RANGE                      19:16
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_2_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0                      MK_ADDR_CONST(0xbe000c)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_RESET_VAL                    MK_MASK_CONST(0x1f720f05)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_RESET_MASK                   MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_READ_MASK                    MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_WRITE_MASK                   MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_RANGE                      31:24
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_RANGE                        23:16
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_DEFAULT                      MK_MASK_CONST(0x72)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_DEFAULT                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_RANGE                 4:4
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_RANGE                        2:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_DEFAULT                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_3_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0                      MK_ADDR_CONST(0xbe0010)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_RESET_VAL                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_RESET_MASK                   MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_READ_MASK                    MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_WRITE_MASK                   MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_RANGE                    25:24
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_RANGE                   23:8
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_RANGE                    5:4
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_RANGE                      3:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_4_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0                      MK_ADDR_CONST(0xbe0014)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_RESET_VAL                    MK_MASK_CONST(0x1e30fff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_RESET_MASK                   MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_READ_MASK                    MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_WRITE_MASK                   MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_SW_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF__PROD                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_RANGE                   27:25
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_RANGE                   24:22
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_MSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_RANGE                   21:19
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_DEFAULT                 MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_RANGE                 18:16
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_DEFAULT                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_OSC_CTRL_0
#define CLK_RST_CONTROLLER_OSC_CTRL_0                   MK_ADDR_CONST(0xbf0000)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_SCR                       AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_VAL                         MK_MASK_CONST(0x50000011)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_MASK                        MK_MASK_CONST(0xfffdf3f5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_READ_MASK                         MK_MASK_CONST(0xfffdf3f5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_WRITE_MASK                        MK_MASK_CONST(0xfffdf3f5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_RANGE                    31:28
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_INIT_ENUM                        OSC38P4
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC13                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC19P2                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC12                    MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC26                    MK_ENUM_CONST(12)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC16P8                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC38P4                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC48                    MK_ENUM_CONST(9)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_RANGE                 27:26
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_LSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DIV1                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DIV2                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DIV4                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_RESERVED                      MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_RANGE                 25:18
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_MSB                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_RANGE                        16:12
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_RANGE                        9:4
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_RANGE                      2:2
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_RANGE                 0:0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0                  MK_ADDR_CONST(0xbf0004)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_SCR                      AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_RESET_VAL                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_SHIFT)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_RANGE                      1:1
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_SHIFT)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_RANGE                  0:0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0                       MK_ADDR_CONST(0xbf0008)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SCR                   AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_MASK                    MK_MASK_CONST(0x8000000f)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_READ_MASK                     MK_MASK_CONST(0x8000000f)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WRITE_MASK                    MK_MASK_CONST(0x8000000f)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_RANGE                       31:31
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_RANGE                 3:0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0                        MK_ADDR_CONST(0xbf000c)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SCR                    AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_RANGE                        31:31
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_RANGE                 15:0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_MISC_REG0_0
#define CLK_RST_CONTROLLER_MISC_REG0_0                  MK_ADDR_CONST(0xbf0010)
#define CLK_RST_CONTROLLER_MISC_REG0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_MISC_REG0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_MISC_REG0_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_MISC_REG0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_MISC_REG0_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_SHIFT)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_RANGE                  0:0
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON__PROD                  MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0                  MK_ADDR_CONST(0xbf0014)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_SCR                      AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_RESET_VAL                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_OVERRIDE_ENABLE_WB0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_RANGE                      1:1
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_IDDQ_WB0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_RANGE                    0:0
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WB0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PWR_SEQ_0
#define CLK_RST_CONTROLLER_PWR_SEQ_0                    MK_ADDR_CONST(0xbf0018)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PWR_SEQ_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PWR_SEQ_0_SCR                        AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_PWR_SEQ_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PWR_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_SHIFT)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_RANGE                     0:0
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PWR_SEQ_0_CAR_USE_NEW_LP0_EXIT_SEQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM4_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0                       MK_ADDR_CONST(0xc00000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SCR                   AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0                   MK_ADDR_CONST(0xc00004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SCR                       AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0                   MK_ADDR_CONST(0xc00008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_SCR                       AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0                   MK_ADDR_CONST(0xc01000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_SCR                       AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0                       MK_ADDR_CONST(0xc01004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SCR                   AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0                       MK_ADDR_CONST(0xc01008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_SCR                   AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0                   MK_ADDR_CONST(0xc02000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_SCR                       AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0                    MK_ADDR_CONST(0xc03000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_SCR                        AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0                   MK_ADDR_CONST(0xc10000)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SCR                       AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0                       MK_ADDR_CONST(0xc10004)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SCR                   AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0                       MK_ADDR_CONST(0xc10008)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_SCR                   AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0                    MK_ADDR_CONST(0xc1000c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0                        MK_ADDR_CONST(0xc10010)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0                        MK_ADDR_CONST(0xc10014)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0                    MK_ADDR_CONST(0xc10018)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0                        MK_ADDR_CONST(0xc1001c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0                        MK_ADDR_CONST(0xc10020)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0                    MK_ADDR_CONST(0xc11000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_SCR                        AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_RESET_VAL                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0                        MK_ADDR_CONST(0xc11004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SCR                    AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0                        MK_ADDR_CONST(0xc11008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_SCR                    AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_RESET_VAL                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0                    MK_ADDR_CONST(0xc12000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_SCR                        AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0                     MK_ADDR_CONST(0xc13000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_SCR                         AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_INIT_ENUM                       OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_OSC_UNDIV                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0                   MK_ADDR_CONST(0xc13004)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SCR                       AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_RESET_VAL                         MK_MASK_CONST(0x802702ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_RESET_MASK                        MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_READ_MASK                         MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_WRITE_MASK                        MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_FIELD                   MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_RANGE                   21:12
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_DEFAULT                 MK_MASK_CONST(0x270)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_DEFAULT_MASK                    MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_FIELD                    MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_RANGE                    9:0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_DEFAULT                  MK_MASK_CONST(0x2ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0                  MK_ADDR_CONST(0xc13008)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SCR                      AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_RESET_VAL                        MK_MASK_CONST(0x802702ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_RESET_MASK                       MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_READ_MASK                        MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_WRITE_MASK                       MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_FIELD                 MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_RANGE                 21:12
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_DEFAULT                       MK_MASK_CONST(0x270)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_FIELD                  MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_RANGE                  9:0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_DEFAULT                        MK_MASK_CONST(0x2ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0                  MK_ADDR_CONST(0xc1300c)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_SCR                      AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_RESET_MASK                       MK_MASK_CONST(0xc0000707)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_READ_MASK                        MK_MASK_CONST(0xc0000707)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_WRITE_MASK                       MK_MASK_CONST(0xc0000707)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_RANGE                 31:31
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_INIT_ENUM                     TSC_HS_REF_CLK
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_TSC_HS_REF_CLK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_TSC_OSC_REF_CLK                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_RANGE                    30:30
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_RANGE                 10:10
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_RANGE                      9:9
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_RANGE                        8:8
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_RANGE                  2:2
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_RANGE                       1:1
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_RANGE                 0:0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0                        MK_ADDR_CONST(0xc18000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_SCR                    TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0                 MK_ADDR_CONST(0xc18004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_SCR                     TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0_TSC_REF_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0                      MK_ADDR_CONST(0xc18008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_SCR                  TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0                     MK_ADDR_CONST(0xc1800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_SCR                         TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0                  MK_ADDR_CONST(0xc18010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_SCR                      TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0_TSC_REF_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0                        MK_ADDR_CONST(0xc18014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_SCR                    TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0                 MK_ADDR_CONST(0xc18018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_SCR                     TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0_TSC_REF_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0                  MK_ADDR_CONST(0xc1801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_SCR                      TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_WRITE_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0_TSC_REF_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0                        MK_ADDR_CONST(0xc18020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_SCR                    TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_RESET_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_READ_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_WRITE_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0                    MK_ADDR_CONST(0xc18024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_SCR                        TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0                    MK_ADDR_CONST(0xc18028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_SCR                        TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0                    MK_ADDR_CONST(0xc1802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_SCR                        TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0_TSC_REF_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0                 MK_ADDR_CONST(0xc18030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_SCR                     TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0_TSC_REF_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0                  MK_ADDR_CONST(0xc18034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_SCR                      TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0_TSC_REF_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0                    MK_ADDR_CONST(0xc20000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_SCR                        AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0                        MK_ADDR_CONST(0xc20004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SCR                    AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0                        MK_ADDR_CONST(0xc20008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_SCR                    AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0                    MK_ADDR_CONST(0xc21000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_SCR                        AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0                     MK_ADDR_CONST(0xc22000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_SCR                         AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_INIT_ENUM                       OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_OSC_UNDIV                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0                    MK_ADDR_CONST(0xc28000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_SCR                        MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0                     MK_ADDR_CONST(0xc28004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_SCR                         MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0                  MK_ADDR_CONST(0xc28008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_SCR                      MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0                 MK_ADDR_CONST(0xc2800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_SCR                     MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0                      MK_ADDR_CONST(0xc28010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_SCR                  MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0                    MK_ADDR_CONST(0xc28014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_SCR                        MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0                     MK_ADDR_CONST(0xc28018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_SCR                         MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0                      MK_ADDR_CONST(0xc2801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_SCR                  MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0                    MK_ADDR_CONST(0xc28020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_SCR                        MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0                        MK_ADDR_CONST(0xc28024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_SCR                    MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0                        MK_ADDR_CONST(0xc28028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_SCR                    MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0                        MK_ADDR_CONST(0xc2802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_SCR                    MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0                     MK_ADDR_CONST(0xc28030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_SCR                         MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0                      MK_ADDR_CONST(0xc28034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_SCR                  MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0_MSS_ENCRYPT_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0                      MK_ADDR_CONST(0xc30000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_SCR                  AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_READ_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_WRITE_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0                       MK_ADDR_CONST(0xc30004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0                        MK_ADDR_CONST(0xc30008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0                   MK_ADDR_CONST(0xc3000c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_RESET_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_READ_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_WRITE_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0                        MK_ADDR_CONST(0xc30010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0                   MK_ADDR_CONST(0xc30014)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_RESET_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_READ_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_WRITE_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0                     MK_ADDR_CONST(0xc30018)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCR                         AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0                        MK_ADDR_CONST(0xc3001c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_RESET_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_READ_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_WRITE_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0                 MK_ADDR_CONST(0xc30020)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_SCR                     AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0                  MK_ADDR_CONST(0xc30024)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0                   MK_ADDR_CONST(0xc30028)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0                      MK_ADDR_CONST(0xc3002c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_SCR                  AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_WRITE_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0                   MK_ADDR_CONST(0xc30030)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0                      MK_ADDR_CONST(0xc30034)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_SCR                  AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_WRITE_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0                        MK_ADDR_CONST(0xc30038)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0                   MK_ADDR_CONST(0xc3003c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0                  MK_ADDR_CONST(0xc30040)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_RESET_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_READ_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_WRITE_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0                   MK_ADDR_CONST(0xc30044)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0                    MK_ADDR_CONST(0xc30048)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0                       MK_ADDR_CONST(0xc3004c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_RESET_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_READ_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_WRITE_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0                    MK_ADDR_CONST(0xc30050)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_READ_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0                       MK_ADDR_CONST(0xc30054)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_RESET_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_READ_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_WRITE_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0                 MK_ADDR_CONST(0xc30058)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_SCR                     AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0                    MK_ADDR_CONST(0xc3005c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_RESET_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_READ_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_WRITE_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0                  MK_ADDR_CONST(0xc30060)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_SCR                      AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0                   MK_ADDR_CONST(0xc30064)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCR                       AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0                    MK_ADDR_CONST(0xc30068)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0                       MK_ADDR_CONST(0xc3006c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0                    MK_ADDR_CONST(0xc30070)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0                       MK_ADDR_CONST(0xc30074)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0                 MK_ADDR_CONST(0xc30078)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCR                     AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_READ_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0                    MK_ADDR_CONST(0xc3007c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0                     MK_ADDR_CONST(0xc30080)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0                      MK_ADDR_CONST(0xc30084)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_SCR                  AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0                       MK_ADDR_CONST(0xc30088)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0                  MK_ADDR_CONST(0xc3008c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_SCR                      AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0                       MK_ADDR_CONST(0xc30090)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0                  MK_ADDR_CONST(0xc30094)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_SCR                      AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0                    MK_ADDR_CONST(0xc30098)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0                       MK_ADDR_CONST(0xc3009c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0                      MK_ADDR_CONST(0xc300a0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_SCR                  AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_pllAON_out                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0                       MK_ADDR_CONST(0xc300a4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0                        MK_ADDR_CONST(0xc300a8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0                   MK_ADDR_CONST(0xc300ac)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_SCR                       AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0                        MK_ADDR_CONST(0xc300b0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0                   MK_ADDR_CONST(0xc300b4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_SCR                       AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_pllAON_out                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0                     MK_ADDR_CONST(0xc300b8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_pllAON_out                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0                        MK_ADDR_CONST(0xc300bc)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_pllAON_out                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0                   MK_ADDR_CONST(0xc300c0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_SCR                       AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_RESET_MASK                        MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_READ_MASK                         MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_WRITE_MASK                        MK_MASK_CONST(0x40000007)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_RANGE                      31:31
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_RANGE                      30:30
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_RANGE                    2:0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0                      MK_ADDR_CONST(0xc300c4)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_SCR                  AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_RESET_VAL                    MK_MASK_CONST(0x1c30)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_RESET_MASK                   MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_READ_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_WRITE_MASK                   MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_RANGE                       12:12
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_RANGE                   11:11
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_RANGE                 9:9
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_RANGE                       8:8
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_RANGE                 7:7
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_RANGE                   6:6
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_RANGE                   5:5
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_RANGE                       4:4
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_RANGE                       3:3
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0                        MK_ADDR_CONST(0xc300c8)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_RESET_VAL                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_RESET_MASK                     MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_READ_MASK                      MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_WRITE_MASK                     MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_RANGE                  31:31
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_RANGE                  30:30
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_RANGE                       29:29
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_FIELD                    MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_RANGE                    11:0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_DEFAULT                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0                   MK_ADDR_CONST(0xc300cc)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_RESET_VAL                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_RESET_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_READ_MASK                         MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_WRITE_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_RANGE                     31:31
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_FIELD                    MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_RANGE                    11:0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_DEFAULT                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_DEFAULT_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0                  MK_ADDR_CONST(0xc300d0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_VAL                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_READ_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_WRITE_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_FIELD                  MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_RANGE                  11:0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_DEFAULT_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0                       MK_ADDR_CONST(0xc300d4)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_VAL                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_READ_MASK                     MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_WRITE_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_RANGE                      31:31
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_FIELD                  MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_RANGE                  11:0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_DEFAULT_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0                  MK_ADDR_CONST(0xc300d8)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_VAL                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_READ_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_WRITE_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_RANGE                   31:31
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_FIELD                       MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_RANGE                       11:0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_DEFAULT_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0                    MK_ADDR_CONST(0xc300dc)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_RESET_VAL                  MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_WRITE_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_RANGE                        5:0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT                      MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0                   MK_ADDR_CONST(0xc300e0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_RANGE                        3:3
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_RANGE                    2:0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_STATUS_0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0                     MK_ADDR_CONST(0xc300e4)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_SCR                         AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_RESET_MASK                  MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_READ_MASK                   MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_RANGE                 31:31
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_RANGE                        30:30
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_RANGE                        7:4
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_RANGE                      3:0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0                      MK_ADDR_CONST(0xc300e8)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_RESET_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_READ_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_RANGE                 31:31
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_FIELD                     MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_RANGE                     11:0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_DEFAULT_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0                     MK_ADDR_CONST(0xc50000)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_SCR                         AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_RESET_VAL                   MK_MASK_CONST(0x7b381)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_RESET_MASK                  MK_MASK_CONST(0xf7f7f3)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_READ_MASK                   MK_MASK_CONST(0xf7f7f3)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_WRITE_MASK                  MK_MASK_CONST(0xf7f7f3)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_RANGE                      23:20
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_AVERAGING_WINDOW_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_FIELD                        MK_FIELD_CONST(0x7f, CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_RANGE                        18:12
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_DEFAULT                      MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_HIGH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_FIELD                 MK_FIELD_CONST(0x7f, CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_SHIFT)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_RANGE                 10:4
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_DEFAULT                       MK_MASK_CONST(0x38)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_DEFAULT_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_THRESHOLD_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_RANGE                        0:0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xc60000

// Reserved address 0xc70000

// Reserved address 0xc80000

// Reserved address 0xc90000

// Reserved address 0xca0000

// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0                       MK_ADDR_CONST(0xcb0000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0_CLK_SPARE_REG_AON_SHARED_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0                      MK_ADDR_CONST(0xcb1000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_SCR                  AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0_CLK_SPARE_REG_AON_PRIVATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0                     MK_ADDR_CONST(0xcb2000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_SCR                         AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0_CLK_SPARE_REG_AON_I2C_SLOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0                        MK_ADDR_CONST(0xcb3000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_SCR                    AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0_CLK_SPARE_REG_AON_DMIC5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0                  MK_ADDR_CONST(0xcb4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_SCR                      AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0_CLK_SPARE_REG_AON_CAN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0                 MK_ADDR_CONST(0xcb5000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_SCR                     AON_SCR_GPIO_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0_CLK_SPARE_REG_AON_GPIO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0                  MK_ADDR_CONST(0xcb6000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_SCR                      AON_SCR_HSP_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0_CLK_SPARE_REG_AON_HSP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0                        MK_ADDR_CONST(0xcb7000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_SCR                    AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0_CLK_SPARE_REG_AON_I2C10_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0                 MK_ADDR_CONST(0xcb8000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_SCR                     AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0_CLK_SPARE_REG_AON_I2C2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0                 MK_ADDR_CONST(0xcb9000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_SCR                     AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0_CLK_SPARE_REG_AON_I2C8_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0                  MK_ADDR_CONST(0xcba000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_SCR                      AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0                  MK_ADDR_CONST(0xcbb000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_SCR                      AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0_CLK_SPARE_REG_AON_OSC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0                       MK_ADDR_CONST(0xcbc000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_SCR                   AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0_CLK_SPARE_REG_AON_PLLAON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0                 MK_ADDR_CONST(0xcbd000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_SCR                     AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0_CLK_SPARE_REG_AON_PWM4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0                 MK_ADDR_CONST(0xcbe000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_SCR                     AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0_CLK_SPARE_REG_AON_SPI2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0                  MK_ADDR_CONST(0xcbf000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_SCR                      AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0_CLK_SPARE_REG_AON_TSC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0                        MK_ADDR_CONST(0xcc0000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_SCR                    AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0_CLK_SPARE_REG_AON_UARTC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0                        MK_ADDR_CONST(0xcc1000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_SCR                    AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0_CLK_SPARE_REG_AON_UARTG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0                        MK_ADDR_CONST(0xcc2000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_SCR                    AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0_CLK_SPARE_REG_AON_UART_MIPI_CAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0                  MK_ADDR_CONST(0xcc3000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_SCR                      AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0_CLK_SPARE_REG_AON_UFS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0                        MK_ADDR_CONST(0xcc4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_SCR                    AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0_CLK_SPARE_REG_AON_TOUCH_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0                 MK_ADDR_CONST(0xcc5000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_SCR                     AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0_CLK_SPARE_REG_AON_AON_APB_FMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0                    MK_ADDR_CONST(0xcc6000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_SCR                        CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0_CLK_SPARE_REG_AON_CAN1_FMON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0                    MK_ADDR_CONST(0xcc7000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_SCR                        AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0_CLK_SPARE_REG_AON_I2C_SLOW_SCR_FMON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0                    MK_ADDR_CONST(0xcc8000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_SCR                        CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0_CLK_SPARE_REG_AON_CAN2_FMON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0                    MK_ADDR_CONST(0xcc9000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_SCR                        I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0_CLK_SPARE_REG_AON_I2C2_FMON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0                    MK_ADDR_CONST(0xcca000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_SCR                        I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0_CLK_SPARE_REG_AON_I2C8_FMON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0                   MK_ADDR_CONST(0xccb000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_SCR                       I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0_CLK_SPARE_REG_AON_I2C10_FMON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0                 MK_ADDR_CONST(0xccc000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_SCR                     AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0_CLK_SPARE_REG_AON_AON_CPU_FMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0                 MK_ADDR_CONST(0xccd000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_SCR                     TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0_CLK_SPARE_REG_AON_TSC_REF_FMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0                     MK_ADDR_CONST(0xcce000)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_SCR                         MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0_CLK_SPARE_REG_AON_MSS_ENCRYPT_FMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0                     MK_ADDR_CONST(0xcdf000)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SCR                         0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0                    MK_ADDR_CONST(0xcdf004)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SCR                        0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0                       MK_ADDR_CONST(0xcdf008)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0                        MK_ADDR_CONST(0xcdf00c)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0                      MK_ADDR_CONST(0xcdf010)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_GPIO_0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0                       MK_ADDR_CONST(0xcdf014)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_HSP_0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0                        MK_ADDR_CONST(0xcdf018)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0                       MK_ADDR_CONST(0xcdf01c)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0                       MK_ADDR_CONST(0xcdf020)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0                      MK_ADDR_CONST(0xcdf024)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0                        MK_ADDR_CONST(0xcdf028)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0                        MK_ADDR_CONST(0xcdf02c)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0                     MK_ADDR_CONST(0xcdf030)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SCR                         0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0                       MK_ADDR_CONST(0xcdf034)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0                       MK_ADDR_CONST(0xcdf038)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0                        MK_ADDR_CONST(0xcdf03c)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0                      MK_ADDR_CONST(0xcdf040)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0                      MK_ADDR_CONST(0xcdf044)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0                      MK_ADDR_CONST(0xcdf048)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0                        MK_ADDR_CONST(0xcdf04c)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0                      MK_ADDR_CONST(0xcdf050)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0                   MK_ADDR_CONST(0xcdf054)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0                      MK_ADDR_CONST(0xcdf058)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CAN1_SCR_FMON_0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0                      MK_ADDR_CONST(0xcdf05c)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CAN2_SCR_FMON_0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0                      MK_ADDR_CONST(0xcdf060)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C2_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0                      MK_ADDR_CONST(0xcdf064)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C2_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C8_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0                      MK_ADDR_CONST(0xcdf068)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C8_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_I2C10_SCR_FMON_0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0                     MK_ADDR_CONST(0xcdf06c)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SCR                         0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_I2C10_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0                   MK_ADDR_CONST(0xcdf070)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0                   MK_ADDR_CONST(0xcdf074)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0                       MK_ADDR_CONST(0xcdf078)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SCR                   0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0                 MK_ADDR_CONST(0xce0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_SCR                     VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_BYPASS_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0_CLK_ENB_VREFRO_OUT_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0                     MK_ADDR_CONST(0xce0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SCR                         VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_BYPASS_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0_SET_CLK_ENB_VREFRO_OUT_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0                     MK_ADDR_CONST(0xce0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_SCR                         VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_BYPASS_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0_CLR_CLK_ENB_VREFRO_OUT_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_VREFRO_BASE_0
#define CLK_RST_CONTROLLER_VREFRO_BASE_0                        MK_ADDR_CONST(0xce000c)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_SCR                    VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_RESET_MASK                     MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_READ_MASK                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_WRITE_MASK                     MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_RANGE                    31:31
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_BASE_0_VREFRO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VREFRO_MISC_0
#define CLK_RST_CONTROLLER_VREFRO_MISC_0                        MK_ADDR_CONST(0xce0010)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_SCR                    VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_RANGE                       0:0
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_MISC_0_VREFRO_PTS_FO                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_VREFRO_CTRL_0_0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0                      MK_ADDR_CONST(0xce0014)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_SCR                  VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_RANGE                        0:0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_0_0_VREFRO_POWER_OK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VREFRO_CTRL_1_0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0                      MK_ADDR_CONST(0xce0018)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_SCR                  VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_1_0_VREFRO_IDDQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VREFRO_CTRL_2_0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0                      MK_ADDR_CONST(0xce001c)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_SCR                  VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_RANGE                       0:0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_CTRL_2_0_VREFRO_L2RESTART_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VREFRO_SETUP_1_0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0                     MK_ADDR_CONST(0xce0020)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_SCR                         VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_RANGE                  7:0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_1_0_VREFRO_SPARE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VREFRO_SETUP_2_0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0                     MK_ADDR_CONST(0xce0024)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_SCR                         VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_RESET_VAL                   MK_MASK_CONST(0x82)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_RANGE                        1:0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_SCHMITT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_RANGE                        7:2
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_DEFAULT                      MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SETUP_2_0_VREFRO_FREQADJ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0                  MK_ADDR_CONST(0xce0028)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_SCR                      VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_RANGE                 0:0
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_INIT_ENUM                     VREFRO_OUT
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_PLLP_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0_VREFRO_FTM_CLK_SEL_VREFRO_OUT                    MK_ENUM_CONST(0)


// Register CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0                  MK_ADDR_CONST(0xce1000)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_SCR                      0
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0_VREFRO_BYPASS_CLK_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0                 MK_ADDR_CONST(0xce2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_SCR                     VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_RANGE                    1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_BYPASS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0_BOND_OUT_VREFRO_OUT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0                      MK_ADDR_CONST(0xcef000)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SCR                  0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0                        MK_ADDR_CONST(0xd00000)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0                    MK_ADDR_CONST(0xd00004)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0                    MK_ADDR_CONST(0xd00008)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_RESET_MASK                         MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_READ_MASK                  MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0                 MK_ADDR_CONST(0xd0000c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SCR                     SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0                     MK_ADDR_CONST(0xd00010)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0                     MK_ADDR_CONST(0xd00014)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0                     MK_ADDR_CONST(0xd00018)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SCR                         SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0                 MK_ADDR_CONST(0xd0001c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SCR                     SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0                 MK_ADDR_CONST(0xd00020)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_SCR                     SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0                    MK_ADDR_CONST(0xd00024)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0                        MK_ADDR_CONST(0xd00028)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0                        MK_ADDR_CONST(0xd0002c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0                   MK_ADDR_CONST(0xd00030)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SCR                       SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0                       MK_ADDR_CONST(0xd00034)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0                       MK_ADDR_CONST(0xd00038)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0                    MK_ADDR_CONST(0xd0003c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0                        MK_ADDR_CONST(0xd00040)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0                        MK_ADDR_CONST(0xd00044)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0                    MK_ADDR_CONST(0xd00048)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0                        MK_ADDR_CONST(0xd0004c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0                        MK_ADDR_CONST(0xd00050)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0                    MK_ADDR_CONST(0xd00054)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0                        MK_ADDR_CONST(0xd00058)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0                        MK_ADDR_CONST(0xd0005c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0                    MK_ADDR_CONST(0xd01000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_SCR                        SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_RESET_VAL                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0                        MK_ADDR_CONST(0xd01004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_RESET_VAL                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0                        MK_ADDR_CONST(0xd01008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_RESET_VAL                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0                    MK_ADDR_CONST(0xd02000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_RANGE                     1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0                     MK_ADDR_CONST(0xd03000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_RESET_MASK                  MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_READ_MASK                   MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_PLLC2_OUT0                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_PLLC3_OUT0                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_CLK_DFLL_SCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_RANGE                        17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NIC_RATE_0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0                       MK_ADDR_CONST(0xd03004)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_RESET_VAL                     MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_RESET_MASK                    MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_READ_MASK                     MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_WRITE_MASK                    MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_RANGE                  4:4
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_RANGE                    1:0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0                  MK_ADDR_CONST(0xd03008)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCR                      SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_RESET_VAL                        MK_MASK_CONST(0x40)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_RANGE                     15:0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_DEFAULT                   MK_MASK_CONST(0x40)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0                        MK_ADDR_CONST(0xd08000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCR                    SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0                 MK_ADDR_CONST(0xd08004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCR                     SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0_SCE_CPU_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0                      MK_ADDR_CONST(0xd08008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCR                  SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0                     MK_ADDR_CONST(0xd0800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCR                         SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0                  MK_ADDR_CONST(0xd08010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCR                      SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0_SCE_CPU_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0                        MK_ADDR_CONST(0xd08014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCR                    SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0                 MK_ADDR_CONST(0xd08018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCR                     SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0_SCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0                  MK_ADDR_CONST(0xd0801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCR                      SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_WRITE_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0_SCE_CPU_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0                        MK_ADDR_CONST(0xd08020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCR                    SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_RESET_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_READ_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_WRITE_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0                    MK_ADDR_CONST(0xd08024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCR                        SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0                    MK_ADDR_CONST(0xd08028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCR                        SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0                    MK_ADDR_CONST(0xd0802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCR                        SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0_SCE_CPU_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0                 MK_ADDR_CONST(0xd08030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCR                     SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0_SCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0                  MK_ADDR_CONST(0xd08034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCR                      SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0_SCE_CPU_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Reserved address 0xd10000

// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0                      MK_ADDR_CONST(0xd20000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCR                  SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_READ_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_WRITE_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_DFLL_SCE                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0                       MK_ADDR_CONST(0xd20004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                   SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_SCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0                        MK_ADDR_CONST(0xd20008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0                        MK_ADDR_CONST(0xd2000c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0                     MK_ADDR_CONST(0xd20010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCR                         SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0                 MK_ADDR_CONST(0xd20014)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCR                     SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0                  MK_ADDR_CONST(0xd20018)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                      SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0                   MK_ADDR_CONST(0xd2001c)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCR                       SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0                   MK_ADDR_CONST(0xd20020)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCR                       SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0                        MK_ADDR_CONST(0xd20024)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0                  MK_ADDR_CONST(0xd20028)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCR                      SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_RESET_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_READ_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_WRITE_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_CLK_DFLL_SCE                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0                   MK_ADDR_CONST(0xd2002c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                       SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_SCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0                    MK_ADDR_CONST(0xd20030)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCR                        SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0                    MK_ADDR_CONST(0xd20034)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCR                        SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_READ_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0                 MK_ADDR_CONST(0xd20038)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCR                     SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0                  MK_ADDR_CONST(0xd2003c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCR                      SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_CLK_DFLL_SCE                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0                   MK_ADDR_CONST(0xd20040)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCR                       SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_SCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0                    MK_ADDR_CONST(0xd20044)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_SCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0                    MK_ADDR_CONST(0xd20048)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_DFLL_SCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0                 MK_ADDR_CONST(0xd2004c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCR                     SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_READ_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_SCE                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0                     MK_ADDR_CONST(0xd20050)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0                      MK_ADDR_CONST(0xd20054)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCR                  SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0                       MK_ADDR_CONST(0xd20058)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0                       MK_ADDR_CONST(0xd2005c)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0                    MK_ADDR_CONST(0xd20060)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0                      MK_ADDR_CONST(0xd20064)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCR                  SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_CLK_DFLL_SCE                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0                       MK_ADDR_CONST(0xd20068)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_SCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0                        MK_ADDR_CONST(0xd2006c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_SCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0                        MK_ADDR_CONST(0xd20070)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_CLK_DFLL_SCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0                     MK_ADDR_CONST(0xd20074)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_SCE                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0                   MK_ADDR_CONST(0xd20078)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCR                       SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_RESET_MASK                        MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_READ_MASK                         MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_WRITE_MASK                        MK_MASK_CONST(0x40000007)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_RANGE                      31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_RANGE                      30:30
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_RANGE                    2:0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0                      MK_ADDR_CONST(0xd2007c)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCR                  SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_RESET_VAL                    MK_MASK_CONST(0xc20)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_RESET_MASK                   MK_MASK_CONST(0xfef)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_READ_MASK                    MK_MASK_CONST(0xfef)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_WRITE_MASK                   MK_MASK_CONST(0xfef)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_RANGE                   11:11
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_RANGE                     10:10
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_RANGE                 9:9
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_RANGE                       8:8
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_RANGE                 7:7
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_RANGE                   6:6
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_RANGE                   5:5
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_RANGE                       3:3
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_RANGE                    1:1
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_RANGE                      0:0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0                        MK_ADDR_CONST(0xd20080)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_RESET_VAL                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_RESET_MASK                     MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_READ_MASK                      MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_WRITE_MASK                     MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_RANGE                  31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_RANGE                  30:30
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_RANGE                       29:29
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_FIELD                    MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_RANGE                    11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_DEFAULT                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0                   MK_ADDR_CONST(0xd20084)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCR                       SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_RESET_VAL                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_RESET_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_READ_MASK                         MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_WRITE_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_RANGE                     31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_FIELD                    MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_RANGE                    11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_DEFAULT                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_DEFAULT_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0                  MK_ADDR_CONST(0xd20088)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCR                      SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_VAL                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_READ_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_WRITE_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_FIELD                  MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_RANGE                  11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_DEFAULT_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0                       MK_ADDR_CONST(0xd2008c)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCR                   SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_VAL                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_READ_MASK                     MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_WRITE_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_RANGE                      31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_FIELD                  MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_RANGE                  11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_DEFAULT_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0                  MK_ADDR_CONST(0xd20090)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCR                      SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_VAL                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_READ_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_WRITE_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_RANGE                   31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_FIELD                       MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_RANGE                       11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_DEFAULT_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0                    MK_ADDR_CONST(0xd20094)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCR                        SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_RESET_VAL                  MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_WRITE_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_RANGE                        5:0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT                      MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0                   MK_ADDR_CONST(0xd20098)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCR                       SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_RANGE                        3:3
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_RANGE                    2:0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0                     MK_ADDR_CONST(0xd2009c)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCR                         SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_RESET_MASK                  MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_READ_MASK                   MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_RANGE                 31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_RANGE                        30:30
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_RANGE                        7:4
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_RANGE                      3:0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0                      MK_ADDR_CONST(0xd200a0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCR                  0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_RESET_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_READ_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_RANGE                 31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_FIELD                     MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_RANGE                     11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_DEFAULT_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0                     MK_ADDR_CONST(0xd30000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCR                         SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_RESET_VAL                   MK_MASK_CONST(0x82)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_RESET_MASK                  MK_MASK_CONST(0x300fb)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_READ_MASK                   MK_MASK_CONST(0x300fb)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_WRITE_MASK                  MK_MASK_CONST(0xfb)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                       17:17
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_RANGE                       16:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_RANGE                       7:7
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_RANGE                  6:6
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                  5:5
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                 4:4
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_RANGE                      3:3
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0                    MK_ADDR_CONST(0xd30004)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCR                        SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_RESET_VAL                  MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_RESET_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_READ_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_WRITE_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                        31:28
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                        27:24
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_RANGE                 20:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_RANGE                 4:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0                     MK_ADDR_CONST(0xd30008)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCR                         SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_RESET_VAL                   MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_RESET_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_READ_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_WRITE_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                       20:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                     MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                 15:8
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_RANGE                       7:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0                     MK_ADDR_CONST(0xd3000c)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCR                         SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                 31:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0                    MK_ADDR_CONST(0xd30010)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCR                        SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_RESET_VAL                  MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_RANGE                        31:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_RANGE                     15:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0                    MK_ADDR_CONST(0xd30014)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCR                        SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_RESET_VAL                  MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_RESET_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_READ_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_WRITE_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                  31:28
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                      27:24
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                  23:20
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                   19:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_RANGE                    11:8
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                 7:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0                     MK_ADDR_CONST(0xd30018)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCR                         SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_RESET_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_READ_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_RANGE                     15:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0                        MK_ADDR_CONST(0xd3001c)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCR                    SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_RESET_VAL                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_RESET_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_READ_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_WRITE_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_RANGE                      31:24
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_RANGE                     23:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0                 MK_ADDR_CONST(0xd30020)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCR                     SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                      7:3
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                       2:1
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_RANGE                 0:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0                        MK_ADDR_CONST(0xd30024)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCR                    SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_RESET_VAL                      MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_RESET_MASK                     MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_READ_MASK                      MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                      13:13
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                       12:12
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_FIELD                    MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_RANGE                    11:3
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_DEFAULT                  MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                    2:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0_SCE_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xd30028

// Reserved address 0xd3002c

// Reserved address 0xd30030

// Reserved address 0xd30034

// Reserved address 0xd30038

// Reserved address 0xd3003c

// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0                   MK_ADDR_CONST(0xd30040)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCR                       SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0                   MK_ADDR_CONST(0xd30044)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCR                       SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_READ_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0                    MK_ADDR_CONST(0xd30048)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCR                        SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_RESET_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_READ_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0                    MK_ADDR_CONST(0xd3004c)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_RESET_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_READ_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0                       MK_ADDR_CONST(0xd30050)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCR                   0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_RESET_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_READ_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_RANGE                       16:8
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                     7:4
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                     3:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0                  MK_ADDR_CONST(0xd30054)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCR                      SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_RESET_VAL                        MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_RESET_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_READ_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_WRITE_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                    25:25
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                     19:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                      12:12
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_RANGE                        8:8
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0                  MK_ADDR_CONST(0xd30058)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCR                      SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                       29:28
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                       23:20
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                 12:4
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                 3:2
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                      1:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0                  MK_ADDR_CONST(0xd3005c)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCR                      SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_RESET_MASK                       MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_READ_MASK                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                  3:3
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xd30060

// Reserved address 0xd30064

// Reserved address 0xd30068

// Register CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0                        MK_ADDR_CONST(0xd3006c)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCR                    SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_RESET_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_READ_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_WRITE_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_RANGE                       31:28
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                     27:27
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_RANGE                  25:25
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_RANGE                        24:24
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                      19:16
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                   15:15
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                  2:0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0                       MK_ADDR_CONST(0xd30070)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCR                   SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_FIELD                      MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0                       MK_ADDR_CONST(0xd30074)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCR                   SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xd30078

// Register CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0                        MK_ADDR_CONST(0xd3007c)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCR                    0
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_RANGE                        3:3
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_INIT_ENUM                    DFLL_SCE_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_DFLL_SCE_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_NAFLLSCE_PTO_ROOT_CLK_SEL_DFLL_SCE_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_RANGE                  2:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_DEFAULT                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_INIT_ENUM                      CLK_NULL
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_DFLL_SCE_CLK                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_DFLL_SCE_PRE_SKP_CLK                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_DFLL_SCE_FLL_UPD_CLK                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_ADC_SOC_REF_SCE_CLK                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_CLK_NULL_2                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_OSC_DIV_CLK                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0_SCE_PTS_CLK_NULL                       MK_ENUM_CONST(7)


// Reserved address 0xd40000

// Reserved address 0xd50000

// Reserved address 0xd60000

// Reserved address 0xd70000

// Reserved address 0xd80000

// Reserved address 0xd90000

// Reserved address 0xda0000

// Reserved address 0xdb0000

// Reserved address 0xdc0000

// Reserved address 0xdd0000

// Register CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0                       MK_ADDR_CONST(0xde0000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0_CLK_SPARE_REG_SCE_SHARED_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0                      MK_ADDR_CONST(0xde1000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_SCR                  SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0_CLK_SPARE_REG_SCE_PRIVATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0                 MK_ADDR_CONST(0xde2000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_SCR                     SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0_CLK_SPARE_REG_SCE_DVFS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0                 MK_ADDR_CONST(0xde3000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_SCR                     SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0_CLK_SPARE_REG_SCE_FMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0                     MK_ADDR_CONST(0xdef000)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SCR                         0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0                    MK_ADDR_CONST(0xdef004)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SCR                        0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0                       MK_ADDR_CONST(0xdef008)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SCR                   0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0                   MK_ADDR_CONST(0xdef00c)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0                   MK_ADDR_CONST(0xe10000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_RESET_VAL                         MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_RESET_MASK                        MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_READ_MASK                         MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_WRITE_MASK                        MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                   17:17
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                     4:4
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0                  MK_ADDR_CONST(0xe10004)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_RESET_VAL                        MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_RESET_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_READ_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_WRITE_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                    31:28
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                  MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                    27:24
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_RANGE                     20:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_RANGE                     4:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_DEFAULT                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0                   MK_ADDR_CONST(0xe10008)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_RESET_VAL                         MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_RESET_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_READ_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_WRITE_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                   20:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                 MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0                   MK_ADDR_CONST(0xe1000c)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                     31:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0                  MK_ADDR_CONST(0xe10010)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_RESET_VAL                        MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_RANGE                    31:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0                  MK_ADDR_CONST(0xe10014)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_RESET_VAL                        MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_RESET_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_READ_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_WRITE_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                      31:28
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                  27:24
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                      23:20
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                       19:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_RANGE                        11:8
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0                   MK_ADDR_CONST(0xe10018)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_RESET_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_READ_MASK                         MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0                      MK_ADDR_CONST(0xe1001c)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_RESET_VAL                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_RESET_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_READ_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_WRITE_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_RANGE                  31:24
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_RANGE                 23:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0                       MK_ADDR_CONST(0xe10020)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                  7:3
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                   2:1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0                      MK_ADDR_CONST(0xe10024)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_RESET_VAL                    MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_RESET_MASK                   MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_READ_MASK                    MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_WRITE_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                  13:13
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                   12:12
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_FIELD                        MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_RANGE                        11:3
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_DEFAULT                      MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                        2:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0_NVDEC_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xe10028

// Reserved address 0xe1002c

// Reserved address 0xe10030

// Reserved address 0xe10034

// Reserved address 0xe10038

// Reserved address 0xe1003c

// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0                 MK_ADDR_CONST(0xe10040)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0                 MK_ADDR_CONST(0xe10044)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_READ_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0                  MK_ADDR_CONST(0xe10048)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_RESET_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_READ_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0                  MK_ADDR_CONST(0xe1004c)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_RESET_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_READ_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0                     MK_ADDR_CONST(0xe10050)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_RESET_MASK                  MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_READ_MASK                   MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_RANGE                   16:8
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                 7:4
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                 3:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0                        MK_ADDR_CONST(0xe10054)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_RESET_VAL                      MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_RESET_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_READ_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_WRITE_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                        25:25
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                 19:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                  12:12
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_RANGE                    8:8
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_RANGE                     2:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0                        MK_ADDR_CONST(0xe10058)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                   29:28
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                   23:20
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                     12:4
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                     3:2
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                  1:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0                        MK_ADDR_CONST(0xe1005c)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_RESET_MASK                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_READ_MASK                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xe10060

// Reserved address 0xe10064

// Reserved address 0xe10068

// Register CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0                      MK_ADDR_CONST(0xe1006c)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_RESET_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_READ_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_RANGE                   31:28
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                 27:27
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_RANGE                      25:25
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_RANGE                    24:24
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_MSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                  19:16
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                       15:15
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0                     MK_ADDR_CONST(0xe10070)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0                     MK_ADDR_CONST(0xe10074)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xe10078

// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0                      MK_ADDR_CONST(0xe1007c)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_RANGE                    3:3
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_INIT_ENUM                        DFLL_NVDEC_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_DFLL_NVDEC_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NAFLLNVDEC_PTO_ROOT_CLK_SEL_DFLL_NVDEC_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_DEFAULT                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_INIT_ENUM                  CLK_NULL
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_DFLL_NVDEC_CLK                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_DFLL_NVDEC_PRE_SKP_CLK                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_DFLL_NVDEC_FLL_UPD_CLK                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_ADC_SOC_REF_NVDEC_CLK                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_AVFS_2_CAR_PCLK                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_OSC_DIV_CLK                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0_NVDEC_PTS_CLK_NULL                   MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0                   MK_ADDR_CONST(0xe20000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_SCR                       0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_RESET_VAL                         MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_RESET_MASK                        MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_READ_MASK                         MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_WRITE_MASK                        MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                   17:17
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                     4:4
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0                  MK_ADDR_CONST(0xe20004)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_RESET_VAL                        MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_RESET_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_READ_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_WRITE_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                    31:28
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                  MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                    27:24
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_RANGE                     20:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_RANGE                     4:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_DEFAULT                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0                   MK_ADDR_CONST(0xe20008)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_SCR                       0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_RESET_VAL                         MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_RESET_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_READ_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_WRITE_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                   20:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                 MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0                   MK_ADDR_CONST(0xe2000c)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_SCR                       0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                     31:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0                  MK_ADDR_CONST(0xe20010)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_RESET_VAL                        MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_RANGE                    31:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0                  MK_ADDR_CONST(0xe20014)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_RESET_VAL                        MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_RESET_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_READ_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_WRITE_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                      31:28
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                  27:24
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                      23:20
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                       19:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_RANGE                        11:8
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0                   MK_ADDR_CONST(0xe20018)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_RESET_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_READ_MASK                         MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0                      MK_ADDR_CONST(0xe2001c)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_SCR                  0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_RESET_VAL                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_RESET_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_READ_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_WRITE_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_RANGE                  31:24
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_RANGE                 23:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0                       MK_ADDR_CONST(0xe20020)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                  7:3
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                   2:1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0                      MK_ADDR_CONST(0xe20024)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_SCR                  0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_RESET_VAL                    MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_RESET_MASK                   MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_READ_MASK                    MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_WRITE_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                  13:13
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                   12:12
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_FIELD                        MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_RANGE                        11:3
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_DEFAULT                      MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                        2:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0_NVJPG_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xe20028

// Reserved address 0xe2002c

// Reserved address 0xe20030

// Reserved address 0xe20034

// Reserved address 0xe20038

// Reserved address 0xe2003c

// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0                 MK_ADDR_CONST(0xe20040)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0                 MK_ADDR_CONST(0xe20044)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_READ_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0                  MK_ADDR_CONST(0xe20048)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_RESET_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_READ_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0                  MK_ADDR_CONST(0xe2004c)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_RESET_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_READ_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0                     MK_ADDR_CONST(0xe20050)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_SCR                         0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_RESET_MASK                  MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_READ_MASK                   MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_RANGE                   16:8
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                 7:4
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                 3:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0                        MK_ADDR_CONST(0xe20054)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_RESET_VAL                      MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_RESET_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_READ_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_WRITE_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                        25:25
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                 19:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                  12:12
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_RANGE                    8:8
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_RANGE                     2:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0                        MK_ADDR_CONST(0xe20058)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_SCR                    0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                   29:28
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                   23:20
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                     12:4
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                     3:2
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                  1:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0                        MK_ADDR_CONST(0xe2005c)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_SCR                    0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_RESET_MASK                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_READ_MASK                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xe20060

// Reserved address 0xe20064

// Reserved address 0xe20068

// Register CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0                      MK_ADDR_CONST(0xe2006c)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_RESET_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_READ_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_RANGE                   31:28
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                 27:27
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_RANGE                      25:25
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_RANGE                    24:24
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_MSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                  19:16
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                       15:15
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0                     MK_ADDR_CONST(0xe20070)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_SCR                         0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0                     MK_ADDR_CONST(0xe20074)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_SCR                         0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xe20078

// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0                      MK_ADDR_CONST(0xe2007c)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_RANGE                    3:3
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_INIT_ENUM                        DFLL_NVJPG_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_DFLL_NVJPG_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NAFLLNVJPG_PTO_ROOT_CLK_SEL_DFLL_NVJPG_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_DEFAULT                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_INIT_ENUM                  CLK_NULL
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_DFLL_NVJPG_CLK                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_DFLL_NVJPG_PRE_SKP_CLK                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_DFLL_NVJPG_FLL_UPD_CLK                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_ADC_SOC_REF_NVJPG_CLK                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_AVFS_3_CAR_PCLK                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_OSC_DIV_CLK                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0_NVJPG_PTS_CLK_NULL                   MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0                    MK_ADDR_CONST(0xe30000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_SCR                        0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_RESET_VAL                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_RESET_MASK                         MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_READ_MASK                  MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_WRITE_MASK                         MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                     17:17
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_RANGE                     16:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_RANGE                        6:6
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                        5:5
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                       4:4
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_RANGE                    3:3
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0                   MK_ADDR_CONST(0xe30004)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_RESET_VAL                         MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_RESET_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_READ_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_WRITE_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                      31:28
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                    MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                      27:24
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_RANGE                       20:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_RANGE                       4:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_DEFAULT                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0                    MK_ADDR_CONST(0xe30008)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_SCR                        0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_RESET_VAL                  MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_RESET_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_READ_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_WRITE_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                     20:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                   MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                       15:8
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_RANGE                     7:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0                    MK_ADDR_CONST(0xe3000c)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_SCR                        0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                       31:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0                   MK_ADDR_CONST(0xe30010)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_RESET_VAL                         MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_RANGE                      31:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_RANGE                   15:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0                   MK_ADDR_CONST(0xe30014)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_RESET_VAL                         MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_RESET_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_READ_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_WRITE_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                        31:28
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                    27:24
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                        23:20
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                 19:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                       7:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0                    MK_ADDR_CONST(0xe30018)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_SCR                        0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_RESET_MASK                         MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_READ_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_RANGE                   15:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0                       MK_ADDR_CONST(0xe3001c)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_SCR                   0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_RESET_VAL                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_RESET_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_READ_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_WRITE_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_RANGE                    31:24
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_RANGE                   23:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0                        MK_ADDR_CONST(0xe30020)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_SCR                    0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                    MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                    7:3
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                     2:1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_RANGE                       0:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0                       MK_ADDR_CONST(0xe30024)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_SCR                   0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_READ_MASK                     MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                    13:13
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                     12:12
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_RANGE                  11:3
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_DEFAULT                        MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                  2:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0_TSEC_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xe30028

// Reserved address 0xe3002c

// Reserved address 0xe30030

// Reserved address 0xe30034

// Reserved address 0xe30038

// Reserved address 0xe3003c

// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0                  MK_ADDR_CONST(0xe30040)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0                  MK_ADDR_CONST(0xe30044)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_READ_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0                   MK_ADDR_CONST(0xe30048)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_RESET_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_READ_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0                   MK_ADDR_CONST(0xe3004c)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_RESET_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_READ_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0                      MK_ADDR_CONST(0xe30050)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_SCR                  0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_RESET_MASK                   MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_READ_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_RANGE                     16:8
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                   7:4
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0                 MK_ADDR_CONST(0xe30054)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_RESET_VAL                       MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_RESET_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_READ_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_WRITE_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                  25:25
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                   19:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                    12:12
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_RANGE                      8:8
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_RANGE                       2:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0                 MK_ADDR_CONST(0xe30058)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_SCR                     0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                     29:28
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                     23:20
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                       12:4
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                       3:2
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                    1:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0                 MK_ADDR_CONST(0xe3005c)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_SCR                     0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_RESET_MASK                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_READ_MASK                       MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                        3:3
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xe30060

// Reserved address 0xe30064

// Reserved address 0xe30068

// Register CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0                       MK_ADDR_CONST(0xe3006c)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_RESET_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_READ_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_RANGE                     31:28
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                   27:27
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_RANGE                        25:25
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_RANGE                      24:24
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                    19:16
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                 15:15
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                        2:0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0                      MK_ADDR_CONST(0xe30070)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_SCR                  0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_FIELD                    MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0                      MK_ADDR_CONST(0xe30074)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_SCR                  0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_RANGE                    3:0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xe30078

// Register CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0                       MK_ADDR_CONST(0xe3007c)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_SCR                   0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_RANGE                      3:3
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_INIT_ENUM                  DFLL_TSEC_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_DFLL_TSEC_CLK_OUT_PTO_OBS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_NAFLLTSEC_PTO_ROOT_CLK_SEL_DFLL_TSEC_CLK_OUT_PTO_DIV2                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_RANGE                        2:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_DEFAULT                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_INIT_ENUM                    CLK_NULL
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_DFLL_TSEC_CLK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_DFLL_TSEC_PRE_SKP_CLK                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_DFLL_TSEC_FLL_UPD_CLK                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_ADC_SOC_REF_TSEC_CLK                 MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_AVFS_4_CAR_PCLK                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_OSC_DIV_CLK                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0_TSEC_PTS_CLK_NULL                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0                   MK_ADDR_CONST(0xe40000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_SCR                       0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_RESET_VAL                         MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_RESET_MASK                        MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_READ_MASK                         MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_WRITE_MASK                        MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                   17:17
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_RANGE                   16:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_RANGE                      6:6
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                      5:5
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                     4:4
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_RANGE                  3:3
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0                  MK_ADDR_CONST(0xe40004)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_RESET_VAL                        MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_RESET_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_READ_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_WRITE_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                    31:28
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                  MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                    27:24
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_RANGE                     20:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_RANGE                     4:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_DEFAULT                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0                   MK_ADDR_CONST(0xe40008)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_SCR                       0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_RESET_VAL                         MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_RESET_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_READ_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_WRITE_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                   20:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                 MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                     15:8
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_RANGE                   7:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0                   MK_ADDR_CONST(0xe4000c)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_SCR                       0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                     31:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0                  MK_ADDR_CONST(0xe40010)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_RESET_VAL                        MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_RANGE                    31:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0                  MK_ADDR_CONST(0xe40014)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_RESET_VAL                        MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_RESET_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_READ_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_WRITE_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                      31:28
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                  27:24
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                      23:20
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                       19:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_RANGE                        11:8
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                     7:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0                   MK_ADDR_CONST(0xe40018)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_RESET_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_READ_MASK                         MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_RANGE                 15:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0                      MK_ADDR_CONST(0xe4001c)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_SCR                  0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_RESET_VAL                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_RESET_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_READ_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_WRITE_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_RANGE                  31:24
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_RANGE                 23:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0                       MK_ADDR_CONST(0xe40020)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                  7:3
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                   2:1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_RANGE                     0:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0                      MK_ADDR_CONST(0xe40024)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_SCR                  0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_RESET_VAL                    MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_RESET_MASK                   MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_READ_MASK                    MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_WRITE_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                  13:13
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                   12:12
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_FIELD                        MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_RANGE                        11:3
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_DEFAULT                      MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                        2:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0_TSECB_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xe40028

// Reserved address 0xe4002c

// Reserved address 0xe40030

// Reserved address 0xe40034

// Reserved address 0xe40038

// Reserved address 0xe4003c

// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0                 MK_ADDR_CONST(0xe40040)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0                 MK_ADDR_CONST(0xe40044)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_READ_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0                  MK_ADDR_CONST(0xe40048)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_RESET_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_READ_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0                  MK_ADDR_CONST(0xe4004c)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_RESET_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_READ_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0                     MK_ADDR_CONST(0xe40050)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_SCR                         0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_RESET_MASK                  MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_READ_MASK                   MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_RANGE                   16:8
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                 7:4
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                 3:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0                        MK_ADDR_CONST(0xe40054)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_RESET_VAL                      MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_RESET_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_READ_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_WRITE_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                        25:25
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                 19:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                  12:12
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_RANGE                    8:8
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_RANGE                     2:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0                        MK_ADDR_CONST(0xe40058)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_SCR                    0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                   29:28
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                   23:20
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                     12:4
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                     3:2
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                  1:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0                        MK_ADDR_CONST(0xe4005c)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_SCR                    0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_RESET_MASK                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_READ_MASK                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                      3:3
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xe40060

// Reserved address 0xe40064

// Reserved address 0xe40068

// Register CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0                      MK_ADDR_CONST(0xe4006c)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_RESET_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_READ_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_RANGE                   31:28
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                 27:27
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_RANGE                      25:25
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_RANGE                    24:24
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_MSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                  19:16
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                       15:15
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                      2:0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0                     MK_ADDR_CONST(0xe40070)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_SCR                         0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0                     MK_ADDR_CONST(0xe40074)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_SCR                         0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xe40078

// Register CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0                      MK_ADDR_CONST(0xe4007c)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_RANGE                    3:3
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_INIT_ENUM                        DFLL_TSECB_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_DFLL_TSECB_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_NAFLLTSECB_PTO_ROOT_CLK_SEL_DFLL_TSECB_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_RANGE                      2:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_DEFAULT                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_INIT_ENUM                  CLK_NULL
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_DFLL_TSECB_CLK                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_DFLL_TSECB_PRE_SKP_CLK                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_DFLL_TSECB_FLL_UPD_CLK                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_ADC_SOC_REF_TSECB_CLK                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_AVFS_5_CAR_PCLK                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_OSC_DIV_CLK                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0_TSECB_PTS_CLK_NULL                   MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0                      MK_ADDR_CONST(0xe50000)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_SCR                  0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_RESET_VAL                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_RESET_MASK                   MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_READ_MASK                    MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_WRITE_MASK                   MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                 17:17
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_RANGE                 16:16
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_RANGE                    6:6
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                    5:5
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                   4:4
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_RANGE                        3:3
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0                     MK_ADDR_CONST(0xe50004)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_RESET_VAL                   MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_RESET_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_READ_MASK                   MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_WRITE_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                  31:28
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                  27:24
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_RANGE                   20:16
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_RANGE                   4:0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0                      MK_ADDR_CONST(0xe50008)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_SCR                  0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_RESET_VAL                    MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_RESET_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_READ_MASK                    MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_WRITE_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                 20:16
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                       MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                   15:8
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_RANGE                 7:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0                      MK_ADDR_CONST(0xe5000c)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_SCR                  0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                   31:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0                     MK_ADDR_CONST(0xe50010)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_RANGE                  31:16
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_RANGE                       15:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0                     MK_ADDR_CONST(0xe50014)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                    31:28
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                        27:24
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                    23:20
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                     19:16
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_RANGE                      11:8
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                   7:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0                      MK_ADDR_CONST(0xe50018)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_SCR                  0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_RESET_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_READ_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_RANGE                       15:0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0                 MK_ADDR_CONST(0xe5001c)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_SCR                     0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_RESET_VAL                       MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_RESET_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_READ_MASK                       MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_WRITE_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_RANGE                        31:24
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_RANGE                       23:16
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0                  MK_ADDR_CONST(0xe50020)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_SCR                      0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                        7:3
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                 2:1
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_RANGE                   0:0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0                 MK_ADDR_CONST(0xe50024)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_SCR                     0
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_RESET_VAL                       MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_RESET_MASK                      MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_READ_MASK                       MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_WRITE_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                        13:13
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                 12:12
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_FIELD                      MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_RANGE                      11:3
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_DEFAULT                    MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                      2:0
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0_VI_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xe50028

// Reserved address 0xe5002c

// Reserved address 0xe50030

// Reserved address 0xe50034

// Reserved address 0xe50038

// Reserved address 0xe5003c

// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0                    MK_ADDR_CONST(0xe50040)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0                    MK_ADDR_CONST(0xe50044)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_READ_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0                     MK_ADDR_CONST(0xe50048)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_RESET_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_READ_MASK                   MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0                     MK_ADDR_CONST(0xe5004c)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_RESET_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_READ_MASK                   MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0                        MK_ADDR_CONST(0xe50050)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_SCR                    0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_RESET_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_READ_MASK                      MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_RANGE                 16:8
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                       7:4
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                       3:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0                   MK_ADDR_CONST(0xe50054)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_SCR                       0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_RESET_VAL                         MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_RESET_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_READ_MASK                         MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_WRITE_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                      25:25
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                       19:16
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                        12:12
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_RANGE                  8:8
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_RANGE                   2:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0                   MK_ADDR_CONST(0xe50058)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_SCR                       0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                         MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                 29:28
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                 23:20
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                   12:4
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                   3:2
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                        1:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0                   MK_ADDR_CONST(0xe5005c)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_SCR                       0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_RESET_MASK                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_READ_MASK                         MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                    3:3
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xe50060

// Reserved address 0xe50064

// Reserved address 0xe50068

// Register CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0                 MK_ADDR_CONST(0xe5006c)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_RESET_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_READ_MASK                       MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_WRITE_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_RANGE                 31:28
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                       27:27
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_RANGE                    25:25
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_RANGE                  24:24
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                        19:16
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                     15:15
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                    2:0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0                        MK_ADDR_CONST(0xe50070)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_SCR                    0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_FIELD                        MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0                        MK_ADDR_CONST(0xe50074)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_SCR                    0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_RANGE                        3:0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xe50078

// Register CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0                 MK_ADDR_CONST(0xe5007c)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_SCR                     0
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_RANGE                  3:3
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_INIT_ENUM                      DFLL_VI_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_DFLL_VI_CLK_OUT_PTO_OBS                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_NAFLLVI_PTO_ROOT_CLK_SEL_DFLL_VI_CLK_OUT_PTO_DIV2                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_RANGE                    2:0
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_DEFAULT                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_INIT_ENUM                        CLK_NULL
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_DFLL_VI_CLK                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_DFLL_VI_PRE_SKP_CLK                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_DFLL_VI_FLL_UPD_CLK                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_ADC_SOC_REF_VI_CLK                       MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_AVFS_6_CAR_PCLK                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_OSC_DIV_CLK                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0_VI_PTS_CLK_NULL                 MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0                      MK_ADDR_CONST(0xe60000)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SCR                  0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_RESET_VAL                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_RESET_MASK                   MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_READ_MASK                    MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_WRITE_MASK                   MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                 17:17
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_RANGE                 16:16
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_RANGE                    6:6
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                    5:5
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                   4:4
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_RANGE                        3:3
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0                     MK_ADDR_CONST(0xe60004)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_RESET_VAL                   MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_RESET_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_READ_MASK                   MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_WRITE_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                  31:28
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                  27:24
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_RANGE                   20:16
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_RANGE                   4:0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0                      MK_ADDR_CONST(0xe60008)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SCR                  0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_RESET_VAL                    MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_RESET_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_READ_MASK                    MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_WRITE_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                 20:16
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                       MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                   15:8
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_RANGE                 7:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0                      MK_ADDR_CONST(0xe6000c)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SCR                  0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                   31:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0                     MK_ADDR_CONST(0xe60010)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_RANGE                  31:16
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_RANGE                       15:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0                     MK_ADDR_CONST(0xe60014)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                    31:28
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                        27:24
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                    23:20
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                     19:16
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_RANGE                      11:8
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                   7:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0                      MK_ADDR_CONST(0xe60018)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SCR                  0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_RESET_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_READ_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_RANGE                       15:0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0                 MK_ADDR_CONST(0xe6001c)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SCR                     0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_RESET_VAL                       MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_RESET_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_READ_MASK                       MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_WRITE_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_RANGE                        31:24
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_RANGE                       23:16
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0                  MK_ADDR_CONST(0xe60020)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SCR                      0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                        7:3
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                 2:1
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_RANGE                   0:0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0                 MK_ADDR_CONST(0xe60024)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SCR                     0
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_RESET_VAL                       MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_RESET_MASK                      MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_READ_MASK                       MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_WRITE_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                        13:13
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                 12:12
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_FIELD                      MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_RANGE                      11:3
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_DEFAULT                    MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                      2:0
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0_SE_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xe60028

// Reserved address 0xe6002c

// Reserved address 0xe60030

// Reserved address 0xe60034

// Reserved address 0xe60038

// Reserved address 0xe6003c

// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0                    MK_ADDR_CONST(0xe60040)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0                    MK_ADDR_CONST(0xe60044)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_READ_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0                     MK_ADDR_CONST(0xe60048)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_RESET_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_READ_MASK                   MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0                     MK_ADDR_CONST(0xe6004c)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_RESET_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_READ_MASK                   MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0                        MK_ADDR_CONST(0xe60050)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SCR                    0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_RESET_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_READ_MASK                      MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_RANGE                 16:8
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                       7:4
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                       3:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0                   MK_ADDR_CONST(0xe60054)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SCR                       0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_RESET_VAL                         MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_RESET_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_READ_MASK                         MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_WRITE_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                      25:25
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                       19:16
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                        12:12
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_RANGE                  8:8
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_RANGE                   2:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0                   MK_ADDR_CONST(0xe60058)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SCR                       0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                         MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                 29:28
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                 23:20
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                   12:4
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                   3:2
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                        1:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0                   MK_ADDR_CONST(0xe6005c)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SCR                       0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_RESET_MASK                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_READ_MASK                         MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                    3:3
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xe60060

// Reserved address 0xe60064

// Reserved address 0xe60068

// Register CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0                 MK_ADDR_CONST(0xe6006c)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_RESET_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_READ_MASK                       MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_WRITE_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_RANGE                 31:28
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                       27:27
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_RANGE                    25:25
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_RANGE                  24:24
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                        19:16
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                     15:15
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                    2:0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0                        MK_ADDR_CONST(0xe60070)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SCR                    0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_FIELD                        MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0                        MK_ADDR_CONST(0xe60074)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SCR                    0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_RANGE                        3:0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xe60078

// Register CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0                 MK_ADDR_CONST(0xe6007c)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SCR                     0
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_RANGE                  3:3
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_INIT_ENUM                      DFLL_SE_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_DFLL_SE_CLK_OUT_PTO_OBS                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_NAFLLSE_PTO_ROOT_CLK_SEL_DFLL_SE_CLK_OUT_PTO_DIV2                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_RANGE                    2:0
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_DEFAULT                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_INIT_ENUM                        CLK_NULL
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_DFLL_SE_CLK                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_DFLL_SE_PRE_SKP_CLK                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_DFLL_SE_FLL_UPD_CLK                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_ADC_SOC_REF_SE_CLK                       MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_AVFS_7_CAR_PCLK                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_OSC_DIV_CLK                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0_SE_PTS_CLK_NULL                 MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0                   MK_ADDR_CONST(0xe70000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_SCR                       0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_RESET_VAL                         MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_RESET_MASK                        MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_READ_MASK                         MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_WRITE_MASK                        MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                   17:17
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                     4:4
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0                  MK_ADDR_CONST(0xe70004)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_RESET_VAL                        MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_RESET_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_READ_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_WRITE_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                    31:28
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                  MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                    27:24
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_RANGE                     20:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_RANGE                     4:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_DEFAULT                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0                   MK_ADDR_CONST(0xe70008)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_SCR                       0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_RESET_VAL                         MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_RESET_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_READ_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_WRITE_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                   20:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                 MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0                   MK_ADDR_CONST(0xe7000c)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_SCR                       0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                     31:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0                  MK_ADDR_CONST(0xe70010)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_RESET_VAL                        MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_RANGE                    31:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0                  MK_ADDR_CONST(0xe70014)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_RESET_VAL                        MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_RESET_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_READ_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_WRITE_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                      31:28
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                  27:24
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                      23:20
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                       19:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_RANGE                        11:8
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0                   MK_ADDR_CONST(0xe70018)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_RESET_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_READ_MASK                         MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0                      MK_ADDR_CONST(0xe7001c)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_SCR                  0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_RESET_VAL                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_RESET_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_READ_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_WRITE_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_RANGE                  31:24
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_RANGE                 23:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0                       MK_ADDR_CONST(0xe70020)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                  7:3
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                   2:1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0                      MK_ADDR_CONST(0xe70024)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_SCR                  0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_RESET_VAL                    MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_RESET_MASK                   MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_READ_MASK                    MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_WRITE_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                  13:13
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                   12:12
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_FIELD                        MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_RANGE                        11:3
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_DEFAULT                      MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                        2:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0_NVENC_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xe70028

// Reserved address 0xe7002c

// Reserved address 0xe70030

// Reserved address 0xe70034

// Reserved address 0xe70038

// Reserved address 0xe7003c

// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0                 MK_ADDR_CONST(0xe70040)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0                 MK_ADDR_CONST(0xe70044)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_READ_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0                  MK_ADDR_CONST(0xe70048)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_RESET_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_READ_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0                  MK_ADDR_CONST(0xe7004c)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_RESET_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_READ_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0                     MK_ADDR_CONST(0xe70050)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_RESET_MASK                  MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_READ_MASK                   MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_RANGE                   16:8
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                 7:4
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                 3:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0                        MK_ADDR_CONST(0xe70054)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_RESET_VAL                      MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_RESET_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_READ_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_WRITE_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                        25:25
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                 19:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                  12:12
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_RANGE                    8:8
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_RANGE                     2:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0                        MK_ADDR_CONST(0xe70058)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_SCR                    0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                   29:28
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                   23:20
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                     12:4
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                     3:2
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                  1:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0                        MK_ADDR_CONST(0xe7005c)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_SCR                    0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_RESET_MASK                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_READ_MASK                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xe70060

// Reserved address 0xe70064

// Reserved address 0xe70068

// Register CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0                      MK_ADDR_CONST(0xe7006c)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_RESET_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_READ_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_RANGE                   31:28
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                 27:27
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_RANGE                      25:25
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_RANGE                    24:24
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_MSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                  19:16
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                       15:15
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0                     MK_ADDR_CONST(0xe70070)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0                     MK_ADDR_CONST(0xe70074)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xe70078

// Register CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0                      MK_ADDR_CONST(0xe7007c)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_RANGE                    3:3
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_INIT_ENUM                        DFLL_NVENC_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_DFLL_NVENC_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NAFLLNVENC_PTO_ROOT_CLK_SEL_DFLL_NVENC_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_DEFAULT                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_INIT_ENUM                  CLK_NULL
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_DFLL_NVENC_CLK                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_DFLL_NVENC_PRE_SKP_CLK                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_DFLL_NVENC_FLL_UPD_CLK                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_ADC_SOC_REF_NVENC_CLK                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_AVFS_8_CAR_PCLK                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_OSC_DIV_CLK                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0_NVENC_PTS_CLK_NULL                   MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0                     MK_ADDR_CONST(0xe80000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_SCR                         0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_RESET_VAL                   MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_RESET_MASK                  MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_READ_MASK                   MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_WRITE_MASK                  MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                       17:17
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_RANGE                       16:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_RANGE                  6:6
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                  5:5
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                 4:4
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_RANGE                      3:3
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0                    MK_ADDR_CONST(0xe80004)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_RESET_VAL                  MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_RESET_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_READ_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_WRITE_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                        31:28
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                        27:24
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_RANGE                 20:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_RANGE                 4:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0                     MK_ADDR_CONST(0xe80008)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_SCR                         0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_RESET_VAL                   MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_RESET_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_READ_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_WRITE_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                       20:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                     MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                 15:8
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_RANGE                       7:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0                     MK_ADDR_CONST(0xe8000c)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_SCR                         0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                 31:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0                    MK_ADDR_CONST(0xe80010)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_RESET_VAL                  MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_RANGE                        31:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_RANGE                     15:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0                    MK_ADDR_CONST(0xe80014)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_RESET_VAL                  MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_RESET_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_READ_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_WRITE_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                  31:28
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                      27:24
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                  23:20
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                   19:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_RANGE                    11:8
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                 7:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0                     MK_ADDR_CONST(0xe80018)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_SCR                         0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_RESET_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_READ_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_RANGE                     15:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0                        MK_ADDR_CONST(0xe8001c)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_SCR                    0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_RESET_VAL                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_RESET_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_READ_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_WRITE_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_RANGE                      31:24
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_RANGE                     23:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0                 MK_ADDR_CONST(0xe80020)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_SCR                     0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                      7:3
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                       2:1
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_RANGE                 0:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0                        MK_ADDR_CONST(0xe80024)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_SCR                    0
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_RESET_VAL                      MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_RESET_MASK                     MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_READ_MASK                      MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                      13:13
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                       12:12
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_FIELD                    MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_RANGE                    11:3
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_DEFAULT                  MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                    2:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0_ISP_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xe80028

// Reserved address 0xe8002c

// Reserved address 0xe80030

// Reserved address 0xe80034

// Reserved address 0xe80038

// Reserved address 0xe8003c

// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0                   MK_ADDR_CONST(0xe80040)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_SCR                       0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0                   MK_ADDR_CONST(0xe80044)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_READ_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0                    MK_ADDR_CONST(0xe80048)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_RESET_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_READ_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0                    MK_ADDR_CONST(0xe8004c)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_RESET_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_READ_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0                       MK_ADDR_CONST(0xe80050)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_SCR                   0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_RESET_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_READ_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_RANGE                       16:8
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                     7:4
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                     3:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0                  MK_ADDR_CONST(0xe80054)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_SCR                      0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_RESET_VAL                        MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_RESET_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_READ_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_WRITE_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                    25:25
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                     19:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                      12:12
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_RANGE                        8:8
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0                  MK_ADDR_CONST(0xe80058)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_SCR                      0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                       29:28
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                       23:20
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                 12:4
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                 3:2
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                      1:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0                  MK_ADDR_CONST(0xe8005c)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_SCR                      0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_RESET_MASK                       MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_READ_MASK                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                  3:3
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xe80060

// Reserved address 0xe80064

// Reserved address 0xe80068

// Register CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0                        MK_ADDR_CONST(0xe8006c)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_RESET_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_READ_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_WRITE_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_RANGE                       31:28
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                     27:27
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_RANGE                  25:25
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_RANGE                        24:24
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                      19:16
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                   15:15
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                  2:0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0                       MK_ADDR_CONST(0xe80070)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_SCR                   0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_FIELD                      MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0                       MK_ADDR_CONST(0xe80074)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_SCR                   0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xe80078

// Register CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0                        MK_ADDR_CONST(0xe8007c)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_SCR                    0
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_RANGE                        3:3
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_INIT_ENUM                    DFLL_ISP_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_DFLL_ISP_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_NAFLLISP_PTO_ROOT_CLK_SEL_DFLL_ISP_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_RANGE                  2:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_DEFAULT                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_INIT_ENUM                      CLK_NULL
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_DFLL_ISP_CLK                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_DFLL_ISP_PRE_SKP_CLK                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_DFLL_ISP_FLL_UPD_CLK                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_ADC_SOC_REF_ISP_CLK                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_AVFS_9_CAR_PCLK                        MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_OSC_DIV_CLK                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0_ISP_PTS_CLK_NULL                       MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0                     MK_ADDR_CONST(0xe90000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_SCR                         0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_RESET_VAL                   MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_RESET_MASK                  MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_READ_MASK                   MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_WRITE_MASK                  MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                       17:17
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_RANGE                       16:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_RANGE                  6:6
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                  5:5
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                 4:4
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_RANGE                      3:3
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0                    MK_ADDR_CONST(0xe90004)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_RESET_VAL                  MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_RESET_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_READ_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_WRITE_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                        31:28
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                        27:24
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_RANGE                 20:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_RANGE                 4:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0                     MK_ADDR_CONST(0xe90008)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_SCR                         0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_RESET_VAL                   MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_RESET_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_READ_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_WRITE_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                       20:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                     MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                 15:8
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_RANGE                       7:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0                     MK_ADDR_CONST(0xe9000c)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_SCR                         0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                 31:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0                    MK_ADDR_CONST(0xe90010)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_RESET_VAL                  MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_RANGE                        31:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_RANGE                     15:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0                    MK_ADDR_CONST(0xe90014)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_RESET_VAL                  MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_RESET_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_READ_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_WRITE_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                  31:28
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                      27:24
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                  23:20
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                   19:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_RANGE                    11:8
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                 7:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0                     MK_ADDR_CONST(0xe90018)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_SCR                         0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_RESET_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_READ_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_RANGE                     15:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0                        MK_ADDR_CONST(0xe9001c)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_SCR                    0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_RESET_VAL                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_RESET_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_READ_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_WRITE_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_RANGE                      31:24
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_RANGE                     23:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0                 MK_ADDR_CONST(0xe90020)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_SCR                     0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                      7:3
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                       2:1
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_RANGE                 0:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0                        MK_ADDR_CONST(0xe90024)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_SCR                    0
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_RESET_VAL                      MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_RESET_MASK                     MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_READ_MASK                      MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                      13:13
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                       12:12
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_FIELD                    MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_RANGE                    11:3
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_DEFAULT                  MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                    2:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0_VIC_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xe90028

// Reserved address 0xe9002c

// Reserved address 0xe90030

// Reserved address 0xe90034

// Reserved address 0xe90038

// Reserved address 0xe9003c

// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0                   MK_ADDR_CONST(0xe90040)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_SCR                       0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0                   MK_ADDR_CONST(0xe90044)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_READ_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0                    MK_ADDR_CONST(0xe90048)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_RESET_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_READ_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0                    MK_ADDR_CONST(0xe9004c)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_RESET_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_READ_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0                       MK_ADDR_CONST(0xe90050)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_SCR                   0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_RESET_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_READ_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_RANGE                       16:8
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                     7:4
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                     3:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0                  MK_ADDR_CONST(0xe90054)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_SCR                      0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_RESET_VAL                        MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_RESET_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_READ_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_WRITE_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                    25:25
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                     19:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                      12:12
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_RANGE                        8:8
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0                  MK_ADDR_CONST(0xe90058)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_SCR                      0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                       29:28
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                       23:20
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                 12:4
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                 3:2
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                      1:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0                  MK_ADDR_CONST(0xe9005c)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_SCR                      0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_RESET_MASK                       MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_READ_MASK                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                  3:3
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xe90060

// Reserved address 0xe90064

// Reserved address 0xe90068

// Register CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0                        MK_ADDR_CONST(0xe9006c)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_RESET_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_READ_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_WRITE_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_RANGE                       31:28
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                     27:27
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_RANGE                  25:25
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_RANGE                        24:24
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                      19:16
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                   15:15
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                  2:0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0                       MK_ADDR_CONST(0xe90070)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_SCR                   0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_FIELD                      MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0                       MK_ADDR_CONST(0xe90074)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_SCR                   0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xe90078

// Register CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0                        MK_ADDR_CONST(0xe9007c)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_SCR                    0
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_RANGE                        3:3
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_INIT_ENUM                    DFLL_VIC_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_DFLL_VIC_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_NAFLLVIC_PTO_ROOT_CLK_SEL_DFLL_VIC_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_RANGE                  2:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_DEFAULT                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_INIT_ENUM                      CLK_NULL
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_DFLL_VIC_CLK                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_DFLL_VIC_PRE_SKP_CLK                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_DFLL_VIC_FLL_UPD_CLK                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_ADC_SOC_REF_VIC_CLK                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_AVFS_10_CAR_PCLK                       MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_OSC_DIV_CLK                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0_VIC_PTS_CLK_NULL                       MK_ENUM_CONST(7)


// Reserved address 0xea0000

// Reserved address 0xeb0000

// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0                    MK_ADDR_CONST(0xec0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_RESET_VAL                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_RESET_MASK                         MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_READ_MASK                  MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_WRITE_MASK                         MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                     17:17
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_RANGE                     16:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_RANGE                        6:6
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                        5:5
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                       4:4
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_RANGE                    3:3
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0                   MK_ADDR_CONST(0xec0004)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_RESET_VAL                         MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_RESET_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_READ_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_WRITE_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                      31:28
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                    MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                      27:24
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_RANGE                       20:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_RANGE                       4:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_DEFAULT                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0                    MK_ADDR_CONST(0xec0008)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_RESET_VAL                  MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_RESET_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_READ_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_WRITE_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                     20:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                   MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                       15:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0                    MK_ADDR_CONST(0xec000c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                       31:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0                   MK_ADDR_CONST(0xec0010)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_RESET_VAL                         MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_RANGE                      31:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_RANGE                   15:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0                   MK_ADDR_CONST(0xec0014)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_RESET_VAL                         MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_RESET_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_READ_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_WRITE_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                        31:28
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                    27:24
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                        23:20
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                 19:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                       7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0                    MK_ADDR_CONST(0xec0018)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_RESET_MASK                         MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_READ_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_RANGE                   15:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0                       MK_ADDR_CONST(0xec001c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_RESET_VAL                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_RESET_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_READ_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_WRITE_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_RANGE                    31:24
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_RANGE                   23:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0                        MK_ADDR_CONST(0xec0020)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                    MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                    7:3
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                     2:1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_RANGE                       0:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0                       MK_ADDR_CONST(0xec0024)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_RESET_VAL                     MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_RESET_MASK                    MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_READ_MASK                     MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_WRITE_MASK                    MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                    13:13
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                     12:12
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_RANGE                  11:3
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_DEFAULT                        MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                  2:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0_NVDISPLAYHUB_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xec0028

// Reserved address 0xec002c

// Reserved address 0xec0030

// Reserved address 0xec0034

// Reserved address 0xec0038

// Reserved address 0xec003c

// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0                  MK_ADDR_CONST(0xec0040)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0                  MK_ADDR_CONST(0xec0044)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_READ_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0                   MK_ADDR_CONST(0xec0048)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_RESET_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_READ_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0                   MK_ADDR_CONST(0xec004c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_RESET_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_READ_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0                      MK_ADDR_CONST(0xec0050)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_RESET_MASK                   MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_READ_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_RANGE                     16:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                   7:4
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0                 MK_ADDR_CONST(0xec0054)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_RESET_VAL                       MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_RESET_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_READ_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_WRITE_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                  25:25
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                   19:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                    12:12
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_RANGE                       2:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0                 MK_ADDR_CONST(0xec0058)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                     29:28
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                     23:20
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                       12:4
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                       3:2
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                    1:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0                 MK_ADDR_CONST(0xec005c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_RESET_MASK                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_READ_MASK                       MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                        3:3
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xec0060

// Reserved address 0xec0064

// Reserved address 0xec0068

// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0                       MK_ADDR_CONST(0xec006c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_RESET_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_READ_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_WRITE_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_RANGE                     31:28
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                   27:27
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_RANGE                        25:25
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_RANGE                      24:24
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                    19:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                 15:15
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                        2:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0                      MK_ADDR_CONST(0xec0070)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_FIELD                    MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0                      MK_ADDR_CONST(0xec0074)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_RANGE                    3:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xec0078

// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0                       MK_ADDR_CONST(0xec007c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_INIT_ENUM                  DFLL_NVDISPLAYHUB_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_DFLL_NVDISPLAYHUB_CLK_OUT_PTO_OBS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NAFLLNVDISPLAYHUB_PTO_ROOT_CLK_SEL_DFLL_NVDISPLAYHUB_CLK_OUT_PTO_DIV2                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_RANGE                        2:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_DEFAULT                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_INIT_ENUM                    CLK_NULL
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_DFLL_NVDISPLAYHUB_CLK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_DFLL_NVDISPLAYHUB_PRE_SKP_CLK                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_DFLL_NVDISPLAYHUB_FLL_UPD_CLK                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_ADC_SOC_REF_NVDISPLAYHUB_CLK                 MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_AVFS_13_CAR_PCLK                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_OSC_DIV_CLK                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0_NVDISPLAYHUB_PTS_CLK_NULL                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0                  MK_ADDR_CONST(0xed0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_SCR                      0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_RESET_VAL                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_RESET_MASK                       MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_READ_MASK                        MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_WRITE_MASK                       MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                 17:17
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_RANGE                 16:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_RANGE                    6:6
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                    5:5
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                   4:4
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_RANGE                        3:3
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0                 MK_ADDR_CONST(0xed0004)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_RESET_VAL                       MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_RESET_MASK                      MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_READ_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_WRITE_MASK                      MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                  31:28
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                  27:24
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_RANGE                   20:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_RANGE                   4:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0                  MK_ADDR_CONST(0xed0008)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_SCR                      0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_RESET_VAL                        MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_RESET_MASK                       MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_READ_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_WRITE_MASK                       MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                 20:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                       MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                   15:8
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_RANGE                 7:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0                  MK_ADDR_CONST(0xed000c)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_SCR                      0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                   31:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0                 MK_ADDR_CONST(0xed0010)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_RESET_VAL                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_RANGE                  31:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_RANGE                       15:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0                 MK_ADDR_CONST(0xed0014)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_RESET_VAL                       MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_RESET_MASK                      MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_READ_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_WRITE_MASK                      MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                    31:28
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                        27:24
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                    23:20
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                     19:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_RANGE                      11:8
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                   7:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0                  MK_ADDR_CONST(0xed0018)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_RANGE                       15:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0                     MK_ADDR_CONST(0xed001c)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_SCR                         0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_RESET_VAL                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_RESET_MASK                  MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_READ_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_WRITE_MASK                  MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_RANGE                        31:24
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_RANGE                       23:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0                      MK_ADDR_CONST(0xed0020)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                        7:3
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                 2:1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_RANGE                   0:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0                     MK_ADDR_CONST(0xed0024)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_SCR                         0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_RESET_VAL                   MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_RESET_MASK                  MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_READ_MASK                   MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_WRITE_MASK                  MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                        13:13
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                 12:12
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_FIELD                      MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_RANGE                      11:3
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_DEFAULT                    MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                      2:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0_AXICBB_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xed0028

// Reserved address 0xed002c

// Reserved address 0xed0030

// Reserved address 0xed0034

// Reserved address 0xed0038

// Reserved address 0xed003c

// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0                        MK_ADDR_CONST(0xed0040)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_SCR                    0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0                        MK_ADDR_CONST(0xed0044)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_SCR                    0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                     MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_READ_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                     MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0                 MK_ADDR_CONST(0xed0048)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0                 MK_ADDR_CONST(0xed004c)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_RESET_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_READ_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0                    MK_ADDR_CONST(0xed0050)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_SCR                        0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_RESET_MASK                         MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_READ_MASK                  MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_RANGE                 16:8
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                       7:4
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                       3:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0                       MK_ADDR_CONST(0xed0054)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_RESET_VAL                     MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_RESET_MASK                    MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_READ_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_WRITE_MASK                    MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                      25:25
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                       19:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                        12:12
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_RANGE                  8:8
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_RANGE                   2:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0                       MK_ADDR_CONST(0xed0058)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_SCR                   0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                    MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                    MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                 29:28
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                 23:20
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                   12:4
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                   3:2
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                        1:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0                       MK_ADDR_CONST(0xed005c)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_SCR                   0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_RESET_MASK                    MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_READ_MASK                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                    3:3
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xed0060

// Reserved address 0xed0064

// Reserved address 0xed0068

// Register CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0                     MK_ADDR_CONST(0xed006c)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_SCR                         0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_RESET_MASK                  MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_READ_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_WRITE_MASK                  MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_RANGE                 31:28
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                       27:27
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_RANGE                    25:25
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_RANGE                  24:24
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                        19:16
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                     15:15
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                    2:0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0                    MK_ADDR_CONST(0xed0070)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_SCR                        0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_FIELD                        MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0                    MK_ADDR_CONST(0xed0074)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_SCR                        0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_RANGE                        3:0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xed0078

// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0                     MK_ADDR_CONST(0xed007c)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_RANGE                  3:3
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_INIT_ENUM                      DFLL_AXICBB_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_DFLL_AXICBB_CLK_OUT_PTO_OBS                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_NAFLLAXICBB_PTO_ROOT_CLK_SEL_DFLL_AXICBB_CLK_OUT_PTO_DIV2                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_RANGE                    2:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_DEFAULT                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_INIT_ENUM                        CLK_NULL
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_DFLL_AXICBB_CLK                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_DFLL_AXICBB_PRE_SKP_CLK                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_DFLL_AXICBB_FLL_UPD_CLK                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_ADC_SOC_REF_AXICBB_CLK                   MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_AVFS_14_CAR_PCLK                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_OSC_DIV_CLK                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0_AXICBB_PTS_CLK_NULL                 MK_ENUM_CONST(7)


// Reserved address 0xee0000

// Reserved address 0xef0000

// Reserved address 0xf00000

// Reserved address 0xf10000

// Reserved address 0xf20000

// Reserved address 0xf30000

// Reserved address 0xf40000

// Reserved address 0xf50000

// Reserved address 0xf60000

// Reserved address 0xf70000

// Reserved address 0xf80000

// Reserved address 0xf90000

// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0                  MK_ADDR_CONST(0xfc0000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0                      MK_ADDR_CONST(0xfc0004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0                      MK_ADDR_CONST(0xfc0008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0                      MK_ADDR_CONST(0xfc1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0                  MK_ADDR_CONST(0xfc1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0                  MK_ADDR_CONST(0xfc1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0                      MK_ADDR_CONST(0xfc2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0                       MK_ADDR_CONST(0xfc3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_RESET_VAL                     MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_CLK_M                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Reserved address 0xfd0000

// Reserved address 0xfe0000

// Reserved address 0xff0000

// Reserved address 0xff0004

// Reserved address 0xff0008

// Reserved address 0xff000c

// Reserved address 0xff0010

// Reserved address 0xff0014

// Reserved address 0xff0018

// Reserved address 0xff001c

// Reserved address 0xff0020

// Reserved address 0xff0024

// Reserved address 0xff0028

// Reserved address 0xff002c

// Reserved address 0xff0030

// Reserved address 0xff0034

// Reserved address 0xff0038

// Reserved address 0xff003c

// Reserved address 0xff0040

// Reserved address 0xff0044

// Reserved address 0xff0048

// Reserved address 0xff004c

// Reserved address 0xff0050

// Reserved address 0xff0054

// Reserved address 0xff0058

// Reserved address 0xff005c

// Reserved address 0xff0060

// Reserved address 0xff0064

// Reserved address 0xff0068

// Reserved address 0xff006c

// Reserved address 0xff0070

// Reserved address 0xff0074

// Reserved address 0xff0078

// Reserved address 0xff007c

// Reserved address 0xff0080

// Reserved address 0xff0084

// Reserved address 0xff0088

// Reserved address 0xff008c

// Register CLK_RST_CONTROLLER_SOC_ADC_CTRL_0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0                       MK_ADDR_CONST(0xff0090)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_RESET_VAL                     MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_RESET_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_READ_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_RANGE                 23:23
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CLOCK_GATE_DISABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_RANGE                        22:22
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_CAPTURE_ACC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_RANGE                 21:21
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_RANGE                    20:20
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ACC_CLR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_RANGE                      19:4
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_RANGE                        3:3
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SEL_ADC_LSB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_RANGE                     2:2
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CTRL_RESET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_RANGE                     1:1
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_CFG_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_RANGE                   0:0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0                      MK_ADDR_CONST(0xff0094)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SCR                  0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_RANGE                 31:0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0_SOC_ADC_CTRL2_ADC_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0                      MK_ADDR_CONST(0xff0098)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SCR                  0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_RANGE                   31:0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0_SOC_ADC_CTRL3_SETUP2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0                    MK_ADDR_CONST(0xff009c)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SCR                        0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_RESET_MASK                         MK_MASK_CONST(0xff13fc)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_READ_MASK                  MK_MASK_CONST(0xff13fc)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_WRITE_MASK                         MK_MASK_CONST(0x1000)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_RANGE                     23:16
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_STAT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_RANGE                     12:12
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_CAPTURE_ADC_DOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_RANGE                     9:2
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0                   MK_ADDR_CONST(0xff00a0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SCR                       0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_RESET_MASK                        MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_READ_MASK                         MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_WRITE_MASK                        MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_FIELD                   MK_FIELD_CONST(0x7f, CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_RANGE                   7:1
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOC_ADC_ACC_0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0                        MK_ADDR_CONST(0xff00a4)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SCR                    0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_FIELD                        MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0                        MK_ADDR_CONST(0xff00a8)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SCR                    0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_FIELD                        MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0                        MK_ADDR_CONST(0xff00ac)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_RESET_VAL                      MK_MASK_CONST(0xe03)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_RESET_MASK                     MK_MASK_CONST(0xff03)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_READ_MASK                      MK_MASK_CONST(0xff03)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_WRITE_MASK                     MK_MASK_CONST(0xff03)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_RANGE                      15:8
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_DEFAULT                    MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_RANGE                  1:1
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_INIT_ENUM                      OSC_DIV
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_PLLP_OUT0                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_OSC_DIV                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_M_DIVIDE_0
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0                       MK_ADDR_CONST(0x1100000)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_RESET_MASK                    MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_READ_MASK                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_WRITE_MASK                    MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_RANGE                   3:2
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR__PROD                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_QSPI1_0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0                      MK_ADDR_CONST(0x1110000)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_0_SWR_QSPI1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0                  MK_ADDR_CONST(0x1110004)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0_SET_SWR_QSPI1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0                  MK_ADDR_CONST(0x1110008)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0_CLR_SWR_QSPI1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0                  MK_ADDR_CONST(0x1111000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0_CLK_ENB_QSPI1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0                      MK_ADDR_CONST(0x1111004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0_SET_CLK_ENB_QSPI1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0                      MK_ADDR_CONST(0x1111008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0_CLR_CLK_ENB_QSPI1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0                  MK_ADDR_CONST(0x1112000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0_BOND_OUT_QSPI1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0                   MK_ADDR_CONST(0x1113000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_RESET_MASK                        MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_READ_MASK                         MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_WRITE_MASK                        MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_PLLC2_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_PLLC_OUT0                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_PLLC3_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_PLLC4_MUXED                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_RANGE                  8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIV2_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0_QSPI1_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_DLA0_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0                       MK_ADDR_CONST(0x1130000)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SCR                   DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_0_SWR_DLA0_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0                   MK_ADDR_CONST(0x1130004)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SCR                       DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0_SET_SWR_DLA0_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0                   MK_ADDR_CONST(0x1130008)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_SCR                       DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0_CLR_SWR_DLA0_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0                   MK_ADDR_CONST(0x1131000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_SCR                       DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_CORE_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_RANGE                 0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0_CLK_ENB_DLA0_FALCON_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0                       MK_ADDR_CONST(0x1131004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SCR                   DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_CORE_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_RANGE                 0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0_SET_CLK_ENB_DLA0_FALCON_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0                       MK_ADDR_CONST(0x1131008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_SCR                   DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_CORE_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_RANGE                 0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0_CLR_CLK_ENB_DLA0_FALCON_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0                   MK_ADDR_CONST(0x1132000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_SCR                       DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_CORE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_RANGE                        0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0_BOND_OUT_DLA0_FALCON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0                     MK_ADDR_CONST(0x1133000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_SCR                         DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_RESET_VAL                   MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_DFLL_DLA_FALCON                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_PLLCV_OUT0                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_PLLCV2_OUT0                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_PLLCV3_OUT0                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_SRC_CLK_M                   MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0_DLA0_FALCON_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0                      MK_ADDR_CONST(0x1133004)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SCR                  DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_RESET_VAL                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_RESET_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_READ_MASK                    MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_WRITE_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_ENB_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA0_FALCON_DIV_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0                       MK_ADDR_CONST(0x1134000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_SCR                   DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_RESET_VAL                     MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_DFLL_DLA                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_PLLCV_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_PLLCV2_OUT0                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_PLLCV3_OUT0                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0_DLA0_CORE_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x1134004)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SCR                    DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA0_CORE_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0                      MK_ADDR_CONST(0x1138000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_SCR                  DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0                       MK_ADDR_CONST(0x1138004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_SCR                   DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0                    MK_ADDR_CONST(0x1138008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_SCR                        DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0                   MK_ADDR_CONST(0x113800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_SCR                       DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0                        MK_ADDR_CONST(0x1138010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_SCR                    DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0_DLA0_CORE_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0                      MK_ADDR_CONST(0x1138014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_SCR                  DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_RESET_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_READ_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0                       MK_ADDR_CONST(0x1138018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_SCR                   DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0                        MK_ADDR_CONST(0x113801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_SCR                    DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_RESET_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_READ_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_WRITE_MASK                     MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0_DLA0_CORE_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0                      MK_ADDR_CONST(0x1138020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_SCR                  DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_RESET_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_READ_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_WRITE_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0                  MK_ADDR_CONST(0x1138024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_SCR                      DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0                  MK_ADDR_CONST(0x1138028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_SCR                      DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0                  MK_ADDR_CONST(0x113802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_SCR                      DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0_DLA0_CORE_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0                       MK_ADDR_CONST(0x1138030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_SCR                   DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0_DLA0_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0                        MK_ADDR_CONST(0x1138034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_SCR                    DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0_DLA0_CORE_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0                    MK_ADDR_CONST(0x1138038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_SCR                        DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0                     MK_ADDR_CONST(0x113803c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_SCR                         DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0                  MK_ADDR_CONST(0x1138040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_SCR                      DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0                 MK_ADDR_CONST(0x1138044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_SCR                     DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0                      MK_ADDR_CONST(0x1138048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_SCR                  DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0_DLA0_FALCON_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0                    MK_ADDR_CONST(0x113804c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_SCR                        DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0                     MK_ADDR_CONST(0x1138050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_SCR                         DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0                      MK_ADDR_CONST(0x1138054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_SCR                  DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0_DLA0_FALCON_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0                    MK_ADDR_CONST(0x1138058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_SCR                        DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0                        MK_ADDR_CONST(0x113805c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_SCR                    DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0                        MK_ADDR_CONST(0x1138060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_SCR                    DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0                        MK_ADDR_CONST(0x1138064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_SCR                    DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0_DLA0_FALCON_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0                     MK_ADDR_CONST(0x1138068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_SCR                         DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0_DLA0_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0                      MK_ADDR_CONST(0x113806c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_SCR                  DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0_DLA0_FALCON_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0                        MK_ADDR_CONST(0x1139000)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_SCR                    DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0_CLK_SPARE_REG_DLA0_FUNC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0                   MK_ADDR_CONST(0x113a000)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_SCR                       DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0_CLK_SPARE_REG_DLA0_CORE_FMON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0                 MK_ADDR_CONST(0x113b000)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_SCR                     DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0_CLK_SPARE_REG_DLA0_FALCON_FMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0                      MK_ADDR_CONST(0x113f000)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0                    MK_ADDR_CONST(0x113f004)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SCR                        0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0                  MK_ADDR_CONST(0x113f008)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_DLA1_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0                       MK_ADDR_CONST(0x1140000)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SCR                   DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_0_SWR_DLA1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0                   MK_ADDR_CONST(0x1140004)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SCR                       DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0_SET_SWR_DLA1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0                   MK_ADDR_CONST(0x1140008)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_SCR                       DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0_CLR_SWR_DLA1_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0                   MK_ADDR_CONST(0x1141000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_SCR                       DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_CORE_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_RANGE                 0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0_CLK_ENB_DLA1_FALCON_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0                       MK_ADDR_CONST(0x1141004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SCR                   DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_CORE_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_RANGE                 0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0_SET_CLK_ENB_DLA1_FALCON_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0                       MK_ADDR_CONST(0x1141008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_SCR                   DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_CORE_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_RANGE                 0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0_CLR_CLK_ENB_DLA1_FALCON_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0                   MK_ADDR_CONST(0x1142000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_SCR                       DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_CORE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_RANGE                        0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0_BOND_OUT_DLA1_FALCON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0                     MK_ADDR_CONST(0x1143000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_SCR                         DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_RESET_VAL                   MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_DFLL_DLA_FALCON                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_PLLCV_OUT0                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_PLLCV2_OUT0                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_PLLCV3_OUT0                     MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_SRC_CLK_M                   MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0_DLA1_FALCON_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0                      MK_ADDR_CONST(0x1143004)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SCR                  DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_RESET_VAL                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_RESET_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_READ_MASK                    MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_WRITE_MASK                   MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_ENB_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0_SUPER_DLA1_FALCON_DIV_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0                       MK_ADDR_CONST(0x1144000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_SCR                   DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_RESET_VAL                     MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_DFLL_DLA                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_PLLCV_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_PLLCV2_OUT0                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_PLLCV3_OUT0                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0_DLA1_CORE_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x1144004)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SCR                    DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0_SUPER_DLA1_CORE_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0                      MK_ADDR_CONST(0x1148000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_SCR                  DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0                       MK_ADDR_CONST(0x1148004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_SCR                   DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0                    MK_ADDR_CONST(0x1148008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_SCR                        DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0                   MK_ADDR_CONST(0x114800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_SCR                       DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0                        MK_ADDR_CONST(0x1148010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_SCR                    DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0_DLA1_CORE_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0                      MK_ADDR_CONST(0x1148014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_SCR                  DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_RESET_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_READ_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0                       MK_ADDR_CONST(0x1148018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_SCR                   DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0                        MK_ADDR_CONST(0x114801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_SCR                    DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_RESET_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_READ_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_WRITE_MASK                     MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0_DLA1_CORE_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0                      MK_ADDR_CONST(0x1148020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_SCR                  DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_RESET_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_READ_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_WRITE_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0                  MK_ADDR_CONST(0x1148024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_SCR                      DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0                  MK_ADDR_CONST(0x1148028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_SCR                      DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0                  MK_ADDR_CONST(0x114802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_SCR                      DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0_DLA1_CORE_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0                       MK_ADDR_CONST(0x1148030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_SCR                   DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0_DLA1_CORE_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0                        MK_ADDR_CONST(0x1148034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_SCR                    DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0_DLA1_CORE_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0                    MK_ADDR_CONST(0x1148038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_SCR                        DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0                     MK_ADDR_CONST(0x114803c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_SCR                         DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0                  MK_ADDR_CONST(0x1148040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_SCR                      DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0                 MK_ADDR_CONST(0x1148044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_SCR                     DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0                      MK_ADDR_CONST(0x1148048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_SCR                  DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0_DLA1_FALCON_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0                    MK_ADDR_CONST(0x114804c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_SCR                        DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0                     MK_ADDR_CONST(0x1148050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_SCR                         DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0                      MK_ADDR_CONST(0x1148054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_SCR                  DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0_DLA1_FALCON_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0                    MK_ADDR_CONST(0x1148058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_SCR                        DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0                        MK_ADDR_CONST(0x114805c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_SCR                    DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0                        MK_ADDR_CONST(0x1148060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_SCR                    DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0                        MK_ADDR_CONST(0x1148064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_SCR                    DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0_DLA1_FALCON_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0                     MK_ADDR_CONST(0x1148068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_SCR                         DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0_DLA1_FALCON_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0                      MK_ADDR_CONST(0x114806c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_SCR                  DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0_DLA1_FALCON_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0                        MK_ADDR_CONST(0x1149000)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_SCR                    DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0_CLK_SPARE_REG_DLA1_FUNC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0                   MK_ADDR_CONST(0x114a000)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_SCR                       DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0_CLK_SPARE_REG_DLA1_CORE_FMON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0                 MK_ADDR_CONST(0x114b000)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_SCR                     DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0_CLK_SPARE_REG_DLA1_FALCON_FMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0                      MK_ADDR_CONST(0x114f000)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0                    MK_ADDR_CONST(0x114f004)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SCR                        0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0                  MK_ADDR_CONST(0x114f008)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0                     MK_ADDR_CONST(0xee0000)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_SCR                         0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_RESET_VAL                   MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_RESET_MASK                  MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_READ_MASK                   MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_WRITE_MASK                  MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                       17:17
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_RANGE                       16:16
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_RANGE                  6:6
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                  5:5
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                 4:4
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_RANGE                      3:3
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0_DLA_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0                    MK_ADDR_CONST(0xee0004)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_SCR                        0
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_RESET_VAL                  MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_RESET_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_READ_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_WRITE_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                        31:28
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                        27:24
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_RANGE                 20:16
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_RANGE                 4:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0_DLA_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0                     MK_ADDR_CONST(0xee0008)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_SCR                         0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_RESET_VAL                   MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_RESET_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_READ_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_WRITE_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                       20:16
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                     MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                 15:8
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_RANGE                       7:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0_DLA_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0                     MK_ADDR_CONST(0xee000c)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_SCR                         0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                 31:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0_DLA_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0                    MK_ADDR_CONST(0xee0010)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_RESET_VAL                  MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_RANGE                        31:16
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_RANGE                     15:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0_DLA_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0                    MK_ADDR_CONST(0xee0014)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_SCR                        0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_RESET_VAL                  MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_RESET_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_READ_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_WRITE_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                  31:28
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                      27:24
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                  23:20
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                   19:16
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_RANGE                    11:8
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                 7:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0_DLA_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0                     MK_ADDR_CONST(0xee0018)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_SCR                         0
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_RESET_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_READ_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_RANGE                     15:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0_DLA_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0                        MK_ADDR_CONST(0xee001c)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_SCR                    0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_RESET_VAL                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_RESET_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_READ_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_WRITE_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_RANGE                      31:24
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_RANGE                     23:16
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0_DLA_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0                 MK_ADDR_CONST(0xee0020)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_SCR                     0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                      7:3
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                       2:1
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_RANGE                 0:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0_DLA_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0                        MK_ADDR_CONST(0xee0024)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_SCR                    0
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_RESET_VAL                      MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_RESET_MASK                     MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_READ_MASK                      MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                      13:13
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                       12:12
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_FIELD                    MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_RANGE                    11:3
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_DEFAULT                  MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                    2:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0_DLA_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xee0028

// Reserved address 0xee002c

// Reserved address 0xee0030

// Reserved address 0xee0034

// Reserved address 0xee0038

// Reserved address 0xee003c

// Register CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0                   MK_ADDR_CONST(0xee0040)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_SCR                       0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0_DLA_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0                   MK_ADDR_CONST(0xee0044)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_READ_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0_DLA_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0                    MK_ADDR_CONST(0xee0048)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_RESET_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_READ_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0_DLA_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0                    MK_ADDR_CONST(0xee004c)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_RESET_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_READ_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0_DLA_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0                       MK_ADDR_CONST(0xee0050)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_SCR                   0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_RESET_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_READ_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_RANGE                       16:8
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                     7:4
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                     3:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0_DLA_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0                  MK_ADDR_CONST(0xee0054)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_SCR                      0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_RESET_VAL                        MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_RESET_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_READ_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_WRITE_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                    25:25
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                     19:16
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                      12:12
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_RANGE                        8:8
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0_DLA_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0                  MK_ADDR_CONST(0xee0058)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_SCR                      0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                       29:28
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                       23:20
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                 12:4
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                 3:2
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                      1:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0_DLA_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0                  MK_ADDR_CONST(0xee005c)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_SCR                      0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_RESET_MASK                       MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_READ_MASK                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                  3:3
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0_DLA_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xee0060

// Reserved address 0xee0064

// Reserved address 0xee0068

// Register CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0                        MK_ADDR_CONST(0xee006c)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_RESET_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_READ_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_WRITE_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_RANGE                       31:28
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                     27:27
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_RANGE                  25:25
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_RANGE                        24:24
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                      19:16
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                   15:15
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                  2:0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0_DLA_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0                       MK_ADDR_CONST(0xee0070)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_SCR                   0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_FIELD                      MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0_DLA_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0                       MK_ADDR_CONST(0xee0074)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_SCR                   0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0_DLA_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xee0078

// Register CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0                        MK_ADDR_CONST(0xee007c)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_SCR                    0
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_RANGE                        3:3
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_INIT_ENUM                    DFLL_DLA_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_DFLL_DLA_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_NAFLLDLA_PTO_ROOT_CLK_SEL_DFLL_DLA_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_SHIFT)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_RANGE                  2:0
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_DEFAULT                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_INIT_ENUM                      CLK_NULL
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_DFLL_DLA_CLK                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_DFLL_DLA_PRE_SKP_CLK                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_DFLL_DLA_FLL_UPD_CLK                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_ADC_SOC_REF_DLA_CLK                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_AVFS_2_CAR_PCLK                        MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_OSC_DIV_CLK                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0_DLA_PTS_CLK_NULL                       MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0                        MK_ADDR_CONST(0xef0000)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_SCR                    0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_RESET_VAL                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_RESET_MASK                     MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_READ_MASK                      MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_WRITE_MASK                     MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                     17:17
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_RANGE                     16:16
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_RANGE                        6:6
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                        5:5
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                       4:4
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_RANGE                    3:3
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0_PVA_CORE_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0                       MK_ADDR_CONST(0xef0004)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_SCR                   0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_RESET_VAL                     MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_RESET_MASK                    MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_READ_MASK                     MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_WRITE_MASK                    MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                      31:28
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                    MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                      27:24
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_RANGE                       20:16
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_RANGE                       4:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_DEFAULT                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0_PVA_CORE_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0                        MK_ADDR_CONST(0xef0008)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_SCR                    0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_RESET_VAL                      MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_RESET_MASK                     MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_READ_MASK                      MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_WRITE_MASK                     MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                     20:16
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                   MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                       15:8
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_RANGE                     7:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0_PVA_CORE_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0                        MK_ADDR_CONST(0xef000c)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_SCR                    0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                       31:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0_PVA_CORE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0                       MK_ADDR_CONST(0xef0010)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_SCR                   0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_RESET_VAL                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_RANGE                      31:16
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_RANGE                   15:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0_PVA_CORE_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0                       MK_ADDR_CONST(0xef0014)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_SCR                   0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_RESET_VAL                     MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_RESET_MASK                    MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_READ_MASK                     MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_WRITE_MASK                    MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                        31:28
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                    27:24
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                        23:20
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                 19:16
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                       7:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0_PVA_CORE_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0                        MK_ADDR_CONST(0xef0018)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_SCR                    0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_RESET_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_READ_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_RANGE                   15:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0_PVA_CORE_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0                   MK_ADDR_CONST(0xef001c)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_SCR                       0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_RESET_VAL                         MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_RESET_MASK                        MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_READ_MASK                         MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_WRITE_MASK                        MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_RANGE                    31:24
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_RANGE                   23:16
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0_PVA_CORE_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0                    MK_ADDR_CONST(0xef0020)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                    MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                    7:3
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                     2:1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_RANGE                       0:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0_PVA_CORE_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0                   MK_ADDR_CONST(0xef0024)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_SCR                       0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_RESET_VAL                         MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_RESET_MASK                        MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_READ_MASK                         MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_WRITE_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                    13:13
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                     12:12
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_RANGE                  11:3
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_DEFAULT                        MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                  2:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0_PVA_CORE_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xef0028

// Reserved address 0xef002c

// Reserved address 0xef0030

// Reserved address 0xef0034

// Reserved address 0xef0038

// Reserved address 0xef003c

// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0                      MK_ADDR_CONST(0xef0040)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_SCR                  0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                   MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                    MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                   MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0_PVA_CORE_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0                      MK_ADDR_CONST(0xef0044)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_SCR                  0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                   MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_READ_MASK                    MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                   MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0_PVA_CORE_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0                       MK_ADDR_CONST(0xef0048)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_SCR                   0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_RESET_MASK                    MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_READ_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0_PVA_CORE_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0                       MK_ADDR_CONST(0xef004c)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_SCR                   0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_RESET_MASK                    MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_READ_MASK                     MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0_PVA_CORE_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0                  MK_ADDR_CONST(0xef0050)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_SCR                      0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_RESET_MASK                       MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_READ_MASK                        MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_RANGE                     16:8
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                   7:4
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0_PVA_CORE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0                     MK_ADDR_CONST(0xef0054)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_SCR                         0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_RESET_VAL                   MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_RESET_MASK                  MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_READ_MASK                   MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_WRITE_MASK                  MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                  25:25
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                   19:16
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                    12:12
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_RANGE                      8:8
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_RANGE                       2:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0_PVA_CORE_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0                     MK_ADDR_CONST(0xef0058)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_SCR                         0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                  MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                   MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                  MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                     29:28
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                     23:20
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                       12:4
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                       3:2
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                    1:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0                     MK_ADDR_CONST(0xef005c)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_SCR                         0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_RESET_MASK                  MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_READ_MASK                   MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                        3:3
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0_PVA_CORE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xef0060

// Reserved address 0xef0064

// Reserved address 0xef0068

// Register CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0                   MK_ADDR_CONST(0xef006c)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_SCR                       0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_RESET_MASK                        MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_READ_MASK                         MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_WRITE_MASK                        MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_RANGE                     31:28
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                   27:27
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_RANGE                        25:25
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_RANGE                      24:24
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                    19:16
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                 15:15
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                        2:0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0_PVA_CORE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0                  MK_ADDR_CONST(0xef0070)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_SCR                      0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_FIELD                    MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0_PVA_CORE_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0                  MK_ADDR_CONST(0xef0074)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_SCR                      0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_READ_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_RANGE                    3:0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0_PVA_CORE_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xef0078

// Register CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0                   MK_ADDR_CONST(0xef007c)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_SCR                       0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_RANGE                      3:3
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_INIT_ENUM                  DFLL_PVA_CORE_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_DFLL_PVA_CORE_CLK_OUT_PTO_OBS                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_NAFLLPVA_CORE_PTO_ROOT_CLK_SEL_DFLL_PVA_CORE_CLK_OUT_PTO_DIV2                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_RANGE                        2:0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_DEFAULT                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_INIT_ENUM                    CLK_NULL
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_DFLL_PVA_CORE_CLK                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_DFLL_PVA_CORE_PRE_SKP_CLK                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_DFLL_PVA_CORE_FLL_UPD_CLK                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_ADC_SOC_REF_PVA_CORE_CLK                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_AVFS_2_CAR_PCLK                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_OSC_DIV_CLK                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0_PVA_CORE_PTS_CLK_NULL                     MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0                 MK_ADDR_CONST(0xf00000)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_SCR                     0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_RESET_VAL                       MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_RESET_MASK                      MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_READ_MASK                       MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_WRITE_MASK                      MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                       17:17
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_RANGE                       16:16
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_RANGE                  6:6
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                  5:5
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                 4:4
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_RANGE                      3:3
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0_PVA_VPS_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0                        MK_ADDR_CONST(0xf00004)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_SCR                    0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_RESET_VAL                      MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_RESET_MASK                     MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_READ_MASK                      MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_WRITE_MASK                     MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                        31:28
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                        27:24
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_RANGE                 20:16
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_RANGE                 4:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0_PVA_VPS_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0                 MK_ADDR_CONST(0xf00008)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_SCR                     0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_RESET_VAL                       MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_RESET_MASK                      MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_READ_MASK                       MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_WRITE_MASK                      MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                       20:16
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                     MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                 15:8
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_RANGE                       7:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0_PVA_VPS_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0                 MK_ADDR_CONST(0xf0000c)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_SCR                     0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                 31:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0_PVA_VPS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0                        MK_ADDR_CONST(0xf00010)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_SCR                    0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_RESET_VAL                      MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_RANGE                        31:16
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_RANGE                     15:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0_PVA_VPS_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0                        MK_ADDR_CONST(0xf00014)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_SCR                    0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_RESET_VAL                      MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_RESET_MASK                     MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_READ_MASK                      MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_WRITE_MASK                     MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                  31:28
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                      27:24
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                  23:20
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                   19:16
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_RANGE                    11:8
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                 7:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0_PVA_VPS_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0                 MK_ADDR_CONST(0xf00018)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_RANGE                     15:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0_PVA_VPS_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0                    MK_ADDR_CONST(0xf0001c)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_SCR                        0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_RESET_VAL                  MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_RESET_MASK                         MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_READ_MASK                  MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_WRITE_MASK                         MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_RANGE                      31:24
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_RANGE                     23:16
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0_PVA_VPS_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0                     MK_ADDR_CONST(0xf00020)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_SCR                         0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                      7:3
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                       2:1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_RANGE                 0:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0_PVA_VPS_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0                    MK_ADDR_CONST(0xf00024)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_SCR                        0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_RESET_VAL                  MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_RESET_MASK                         MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_READ_MASK                  MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_WRITE_MASK                         MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                      13:13
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                       12:12
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_FIELD                    MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_RANGE                    11:3
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_DEFAULT                  MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                    2:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0_PVA_VPS_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xf00028

// Reserved address 0xf0002c

// Reserved address 0xf00030

// Reserved address 0xf00034

// Reserved address 0xf00038

// Reserved address 0xf0003c

// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0                       MK_ADDR_CONST(0xf00040)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_SCR                   0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                    MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0_PVA_VPS_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0                       MK_ADDR_CONST(0xf00044)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_SCR                   0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                    MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_READ_MASK                     MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                    MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0_PVA_VPS_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0                        MK_ADDR_CONST(0xf00048)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_SCR                    0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_RESET_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_READ_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0_PVA_VPS_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0                        MK_ADDR_CONST(0xf0004c)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_SCR                    0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_RESET_MASK                     MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_READ_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0_PVA_VPS_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0                   MK_ADDR_CONST(0xf00050)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_SCR                       0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_RESET_MASK                        MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_READ_MASK                         MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_RANGE                       16:8
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                     7:4
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                     3:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0_PVA_VPS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0                      MK_ADDR_CONST(0xf00054)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_RESET_VAL                    MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_RESET_MASK                   MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_READ_MASK                    MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_WRITE_MASK                   MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                    25:25
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                     19:16
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                      12:12
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_RANGE                        8:8
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0_PVA_VPS_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0                      MK_ADDR_CONST(0xf00058)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_SCR                  0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                   MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                    MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                   MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                       29:28
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                       23:20
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                 12:4
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                 3:2
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                      1:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0                      MK_ADDR_CONST(0xf0005c)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_SCR                  0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_RESET_MASK                   MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_READ_MASK                    MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                  3:3
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0_PVA_VPS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xf00060

// Reserved address 0xf00064

// Reserved address 0xf00068

// Register CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0                    MK_ADDR_CONST(0xf0006c)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_SCR                        0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_RESET_MASK                         MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_READ_MASK                  MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_WRITE_MASK                         MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_RANGE                       31:28
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                     27:27
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_RANGE                  25:25
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_RANGE                        24:24
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                      19:16
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                   15:15
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                  2:0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0_PVA_VPS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0                   MK_ADDR_CONST(0xf00070)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_SCR                       0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_FIELD                      MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0_PVA_VPS_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0                   MK_ADDR_CONST(0xf00074)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_SCR                       0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0_PVA_VPS_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xf00078

// Register CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0                    MK_ADDR_CONST(0xf0007c)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_RESET_VAL                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_RANGE                        3:3
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_INIT_ENUM                    DFLL_PVA_VPS_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_DFLL_PVA_VPS_CLK_OUT_PTO_OBS                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_NAFLLPVA_VPS_PTO_ROOT_CLK_SEL_DFLL_PVA_VPS_CLK_OUT_PTO_DIV2                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_RANGE                  2:0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_DEFAULT                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_INIT_ENUM                      CLK_NULL
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_DFLL_PVA_VPS_CLK                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_DFLL_PVA_VPS_PRE_SKP_CLK                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_DFLL_PVA_VPS_FLL_UPD_CLK                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_ADC_SOC_REF_PVA_VPS_CLK                        MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_AVFS_2_CAR_PCLK                        MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_OSC_DIV_CLK                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0_PVA_VPS_PTS_CLK_NULL                       MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0                    MK_ADDR_CONST(0x1150000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_SCR                        PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_RESET_VAL                  MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_DFLL_PVA_CORE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_PLLCV_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_PLLCV2_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_PLLCV3_OUT0                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0_PVA0_CPU_AXI_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0                   MK_ADDR_CONST(0x1150004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0_CLK_ENB_PVA0_CPU_AXI_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0                       MK_ADDR_CONST(0x1150008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0_SET_CLK_ENB_PVA0_CPU_AXI_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0                       MK_ADDR_CONST(0x115000c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA0_CPU_AXI_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0                 MK_ADDR_CONST(0x1150010)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_SCR                     PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_RESET_VAL                       MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_RANGE                   4:0
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_DEFAULT                 MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0_PVA0_NRESET_CYCLE_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0                      MK_ADDR_CONST(0x1150014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0_CLK_ENB_PVA0_DMA0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0                  MK_ADDR_CONST(0x1150018)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0_SET_CLK_ENB_PVA0_DMA0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0                  MK_ADDR_CONST(0x115001c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0_CLR_CLK_ENB_PVA0_DMA0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0                      MK_ADDR_CONST(0x1150020)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0_CLK_ENB_PVA0_DMA1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0                  MK_ADDR_CONST(0x1150024)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0_SET_CLK_ENB_PVA0_DMA1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0                  MK_ADDR_CONST(0x1150028)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0_CLR_CLK_ENB_PVA0_DMA1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0                       MK_ADDR_CONST(0x115002c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0_CLK_ENB_PVA0_CPU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0                   MK_ADDR_CONST(0x1150030)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0_SET_CLK_ENB_PVA0_CPU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0                   MK_ADDR_CONST(0x1150034)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0_CLR_CLK_ENB_PVA0_CPU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0                       MK_ADDR_CONST(0x1150038)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0_CLK_ENB_PVA0_APB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0                   MK_ADDR_CONST(0x115003c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0_SET_CLK_ENB_PVA0_APB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0                   MK_ADDR_CONST(0x1150040)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0_CLR_CLK_ENB_PVA0_APB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0                   MK_ADDR_CONST(0x1150044)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0_BOND_OUT_PVA0_CPU_AXI_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0                      MK_ADDR_CONST(0x1150048)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0_BOND_OUT_PVA0_DMA0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0                      MK_ADDR_CONST(0x115004c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0_BOND_OUT_PVA0_DMA1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0                       MK_ADDR_CONST(0x1150050)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0_BOND_OUT_PVA0_CPU_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0                       MK_ADDR_CONST(0x1150054)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0_BOND_OUT_PVA0_APB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0                 MK_ADDR_CONST(0x1150058)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SCR                     PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_RESET_VAL                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_RESET_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_READ_MASK                       MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_WRITE_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA0_CPU_DIV_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0                 MK_ADDR_CONST(0x115005c)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SCR                     PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_RESET_VAL                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_RESET_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_READ_MASK                       MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_WRITE_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA0_AXI_DIV_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0                 MK_ADDR_CONST(0x1150060)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SCR                     PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_RESET_VAL                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_RESET_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_READ_MASK                       MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_WRITE_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA0_APB_DIV_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0                       MK_ADDR_CONST(0x1150064)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_WRITE_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL1_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_EARLYL2_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_RANGE                     0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_0_SWR_PVA0_PREBOOTL2_WARM_RST_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0                   MK_ADDR_CONST(0x1150068)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL1_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_EARLYL2_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_RANGE                     0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0_SET_SWR_PVA0_PREBOOTL2_WARM_RST_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0                   MK_ADDR_CONST(0x115006c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL1_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_EARLYL2_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_RANGE                     0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0_CLR_SWR_PVA0_PREBOOTL2_WARM_RST_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0                  MK_ADDR_CONST(0x1150070)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0_SWR_PVA0_DMA0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0                      MK_ADDR_CONST(0x1150074)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0_SET_SWR_PVA0_DMA0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0                      MK_ADDR_CONST(0x1150078)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0_CLR_SWR_PVA0_DMA0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0                  MK_ADDR_CONST(0x115007c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0_SWR_PVA0_DMA1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0                      MK_ADDR_CONST(0x1150080)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0_SET_SWR_PVA0_DMA1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0                      MK_ADDR_CONST(0x1150084)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0_CLR_SWR_PVA0_DMA1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0                       MK_ADDR_CONST(0x1150088)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0_SWR_PVA0_PROCCFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0                   MK_ADDR_CONST(0x115008c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0_SET_SWR_PVA0_PROCCFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0                   MK_ADDR_CONST(0x1150090)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0_CLR_SWR_PVA0_PROCCFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0                    MK_ADDR_CONST(0x1150094)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SCR                        PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0_SWR_PVA0_PM_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0                        MK_ADDR_CONST(0x1150098)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SCR                    PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0_SET_SWR_PVA0_PM_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0                        MK_ADDR_CONST(0x115009c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_SCR                    PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0_CLR_SWR_PVA0_PM_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0                       MK_ADDR_CONST(0x11500a0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_RESET_VAL                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NSYSPORESET_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_NRESET_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_DBGRESETN_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0_SWR_PVA0_PRESETDBGN_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0                   MK_ADDR_CONST(0x11500a4)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_RESET_VAL                         MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NSYSPORESET_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_NRESET_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_DBGRESETN_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0_SET_SWR_PVA0_PRESETDBGN_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0                   MK_ADDR_CONST(0x11500a8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_RESET_VAL                         MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_RESET_MASK                        MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_READ_MASK                         MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_NSYSPORESET_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_DBGRESETN_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0_CLR_SWR_PVA0_PRESETDBGN_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0                        MK_ADDR_CONST(0x11500ac)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_SCR                    PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_RESET_VAL                      MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_DFLL_PVA_VPS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_PLLCV_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_PLLCV2_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_PLLCV3_OUT0                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0_PVA0_VPS_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0                       MK_ADDR_CONST(0x11500b0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0_CLK_ENB_PVA0_VPS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0                   MK_ADDR_CONST(0x11500b4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0_SET_CLK_ENB_PVA0_VPS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0                   MK_ADDR_CONST(0x11500b8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0_CLR_CLK_ENB_PVA0_VPS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0                      MK_ADDR_CONST(0x11500bc)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0_CLK_ENB_PVA0_VPS0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0                  MK_ADDR_CONST(0x11500c0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0_SET_CLK_ENB_PVA0_VPS0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0                  MK_ADDR_CONST(0x11500c4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0_CLR_CLK_ENB_PVA0_VPS0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0                      MK_ADDR_CONST(0x11500c8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0_CLK_ENB_PVA0_VPS1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0                  MK_ADDR_CONST(0x11500cc)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0_SET_CLK_ENB_PVA0_VPS1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0                  MK_ADDR_CONST(0x11500d0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0_CLR_CLK_ENB_PVA0_VPS1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0                       MK_ADDR_CONST(0x11500d4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0_BOND_OUT_PVA0_VPS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0                      MK_ADDR_CONST(0x11500d8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0_BOND_OUT_PVA0_VPS0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0                      MK_ADDR_CONST(0x11500dc)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0_BOND_OUT_PVA0_VPS1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x11500e0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SCR                    PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS0_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x11500e4)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SCR                    PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA0_VPS1_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0                  MK_ADDR_CONST(0x11500e8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0_SWR_PVA0_VPS0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0                      MK_ADDR_CONST(0x11500ec)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0_SET_SWR_PVA0_VPS0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0                      MK_ADDR_CONST(0x11500f0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0_CLR_SWR_PVA0_VPS0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0                  MK_ADDR_CONST(0x11500f4)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SCR                      PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0_SWR_PVA0_VPS1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0                      MK_ADDR_CONST(0x11500f8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0_SET_SWR_PVA0_VPS1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0                      MK_ADDR_CONST(0x11500fc)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_SCR                  PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0_CLR_SWR_PVA0_VPS1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0                   MK_ADDR_CONST(0x1150100)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0_SWR_PVA0_CFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0                       MK_ADDR_CONST(0x1150104)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0_SET_SWR_PVA0_CFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0                       MK_ADDR_CONST(0x1150108)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0_CLR_SWR_PVA0_CFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0                   MK_ADDR_CONST(0x115010c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0_SWR_PVA0_H1X_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0                       MK_ADDR_CONST(0x1150110)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0_SET_SWR_PVA0_H1X_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0                       MK_ADDR_CONST(0x1150114)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0_CLR_SWR_PVA0_H1X_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0                   MK_ADDR_CONST(0x1150118)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0_SWR_PVA0_SEC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0                       MK_ADDR_CONST(0x115011c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0_SET_SWR_PVA0_SEC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0                       MK_ADDR_CONST(0x1150120)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0_CLR_SWR_PVA0_SEC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0                 MK_ADDR_CONST(0x1150124)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SCR                     PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0_SWR_PVA0_RAMIC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0                     MK_ADDR_CONST(0x1150128)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SCR                         PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0_SET_SWR_PVA0_RAMIC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0                     MK_ADDR_CONST(0x115012c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_SCR                         PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0_CLR_SWR_PVA0_RAMIC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0                        MK_ADDR_CONST(0x1150130)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SCR                    PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0_SWR_PVA0_ACTMON_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0                    MK_ADDR_CONST(0x1150134)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SCR                        PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0_SET_SWR_PVA0_ACTMON_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0                    MK_ADDR_CONST(0x1150138)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_SCR                        PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0_CLR_SWR_PVA0_ACTMON_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0                   MK_ADDR_CONST(0x115013c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0_SWR_PVA0_TKE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0                       MK_ADDR_CONST(0x1150140)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0_SET_SWR_PVA0_TKE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0                       MK_ADDR_CONST(0x1150144)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0_CLR_SWR_PVA0_TKE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0                 MK_ADDR_CONST(0x1150148)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SCR                     PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0_SWR_PVA0_TSCTN_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0                     MK_ADDR_CONST(0x115014c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SCR                         PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0_SET_SWR_PVA0_TSCTN_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0                     MK_ADDR_CONST(0x1150150)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_SCR                         PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0_CLR_SWR_PVA0_TSCTN_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0                   MK_ADDR_CONST(0x1150154)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SCR                       PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0_SWR_PVA0_GTE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0                       MK_ADDR_CONST(0x1150158)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0_SET_SWR_PVA0_GTE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0                       MK_ADDR_CONST(0x115015c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_SCR                   PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0_CLR_SWR_PVA0_GTE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0                   MK_ADDR_CONST(0x1158000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_SCR                       PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0                    MK_ADDR_CONST(0x1158004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_SCR                        PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0                 MK_ADDR_CONST(0x1158008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_SCR                     PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0                        MK_ADDR_CONST(0x115800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_SCR                    PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0                     MK_ADDR_CONST(0x1158010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_SCR                         PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0                   MK_ADDR_CONST(0x1158014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_SCR                       PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0                    MK_ADDR_CONST(0x1158018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_SCR                        PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0                     MK_ADDR_CONST(0x115801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_SCR                         PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0                   MK_ADDR_CONST(0x1158020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_SCR                       PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0                       MK_ADDR_CONST(0x1158024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_SCR                   PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0                       MK_ADDR_CONST(0x1158028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_SCR                   PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0                       MK_ADDR_CONST(0x115802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_SCR                   PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0                    MK_ADDR_CONST(0x1158030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_SCR                        PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0                     MK_ADDR_CONST(0x1158034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_SCR                         PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0_PVA0_CPU_AXI_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0                       MK_ADDR_CONST(0x1158038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_SCR                   PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0                        MK_ADDR_CONST(0x115803c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_SCR                    PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0                     MK_ADDR_CONST(0x1158040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_SCR                         PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0                    MK_ADDR_CONST(0x1158044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_SCR                        PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0                 MK_ADDR_CONST(0x1158048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_SCR                     PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0_PVA0_VPS_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0                       MK_ADDR_CONST(0x115804c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_SCR                   PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0                        MK_ADDR_CONST(0x1158050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_SCR                    PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0                 MK_ADDR_CONST(0x1158054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_SCR                     PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_RESET_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_READ_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_WRITE_MASK                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0_PVA0_VPS_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0                       MK_ADDR_CONST(0x1158058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_SCR                   PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_RESET_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_READ_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_WRITE_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0                   MK_ADDR_CONST(0x115805c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_SCR                       PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0                   MK_ADDR_CONST(0x1158060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_SCR                       PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0                   MK_ADDR_CONST(0x1158064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_SCR                       PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0_PVA0_VPS_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0                        MK_ADDR_CONST(0x1158068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_SCR                    PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0_PVA0_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0                 MK_ADDR_CONST(0x115806c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_SCR                     PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0_PVA0_VPS_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0                        MK_ADDR_CONST(0x1159000)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_SCR                    PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0_CLK_SPARE_REG_PVA0_FMON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0                    MK_ADDR_CONST(0x1159004)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_SCR                        PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0_CLK_SPARE_REG_PVA0_VPS_FMON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0                        MK_ADDR_CONST(0x115a000)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_SCR                    PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0_CLK_SPARE_REG_PVA0_FUNC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0                      MK_ADDR_CONST(0x115f000)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA0_SCR_FMON_0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0                      MK_ADDR_CONST(0x115f004)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0                  MK_ADDR_CONST(0x115f008)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0                    MK_ADDR_CONST(0x1160000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_SCR                        PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_RESET_VAL                  MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_DFLL_PVA_CORE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_PLLCV_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_PLLCV2_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_PLLCV3_OUT0                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0_PVA1_CPU_AXI_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0                   MK_ADDR_CONST(0x1160004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0_CLK_ENB_PVA1_CPU_AXI_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0                       MK_ADDR_CONST(0x1160008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0_SET_CLK_ENB_PVA1_CPU_AXI_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0                       MK_ADDR_CONST(0x116000c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0_CLR_CLK_ENB_PVA1_CPU_AXI_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0                 MK_ADDR_CONST(0x1160010)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_SCR                     PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_RESET_VAL                       MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_RANGE                   4:0
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_DEFAULT                 MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0_PVA1_NRESET_CYCLE_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0                      MK_ADDR_CONST(0x1160014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0_CLK_ENB_PVA1_DMA0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0                  MK_ADDR_CONST(0x1160018)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0_SET_CLK_ENB_PVA1_DMA0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0                  MK_ADDR_CONST(0x116001c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0_CLR_CLK_ENB_PVA1_DMA0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0                      MK_ADDR_CONST(0x1160020)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0_CLK_ENB_PVA1_DMA1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0                  MK_ADDR_CONST(0x1160024)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0_SET_CLK_ENB_PVA1_DMA1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0                  MK_ADDR_CONST(0x1160028)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0_CLR_CLK_ENB_PVA1_DMA1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0                       MK_ADDR_CONST(0x116002c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0_CLK_ENB_PVA1_CPU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0                   MK_ADDR_CONST(0x1160030)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0_SET_CLK_ENB_PVA1_CPU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0                   MK_ADDR_CONST(0x1160034)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0_CLR_CLK_ENB_PVA1_CPU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0                       MK_ADDR_CONST(0x1160038)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0_CLK_ENB_PVA1_APB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0                   MK_ADDR_CONST(0x116003c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0_SET_CLK_ENB_PVA1_APB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0                   MK_ADDR_CONST(0x1160040)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0_CLR_CLK_ENB_PVA1_APB_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0                   MK_ADDR_CONST(0x1160044)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0_BOND_OUT_PVA1_CPU_AXI_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0                      MK_ADDR_CONST(0x1160048)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0_BOND_OUT_PVA1_DMA0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0                      MK_ADDR_CONST(0x116004c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0_BOND_OUT_PVA1_DMA1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0                       MK_ADDR_CONST(0x1160050)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0_BOND_OUT_PVA1_CPU_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0                       MK_ADDR_CONST(0x1160054)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0_BOND_OUT_PVA1_APB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0                 MK_ADDR_CONST(0x1160058)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SCR                     PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_RESET_VAL                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_RESET_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_READ_MASK                       MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_WRITE_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0_SUPER_PVA1_CPU_DIV_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0                 MK_ADDR_CONST(0x116005c)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SCR                     PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_RESET_VAL                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_RESET_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_READ_MASK                       MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_WRITE_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0_SUPER_PVA1_AXI_DIV_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0                 MK_ADDR_CONST(0x1160060)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SCR                     PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_RESET_VAL                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_RESET_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_READ_MASK                       MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_WRITE_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_SHIFT                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_LSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_ENB_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0_SUPER_PVA1_APB_DIV_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0                       MK_ADDR_CONST(0x1160064)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_RESET_VAL                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_WRITE_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL1_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_EARLYL2_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_RANGE                     0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_0_SWR_PVA1_PREBOOTL2_WARM_RST_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0                   MK_ADDR_CONST(0x1160068)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL1_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_EARLYL2_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_RANGE                     0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0_SET_SWR_PVA1_PREBOOTL2_WARM_RST_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0                   MK_ADDR_CONST(0x116006c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_RESET_VAL                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL1_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_EARLYL2_WARM_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_RANGE                     0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0_CLR_SWR_PVA1_PREBOOTL2_WARM_RST_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0                  MK_ADDR_CONST(0x1160070)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0_SWR_PVA1_DMA0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0                      MK_ADDR_CONST(0x1160074)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0_SET_SWR_PVA1_DMA0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0                      MK_ADDR_CONST(0x1160078)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0_CLR_SWR_PVA1_DMA0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0                  MK_ADDR_CONST(0x116007c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0_SWR_PVA1_DMA1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0                      MK_ADDR_CONST(0x1160080)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0_SET_SWR_PVA1_DMA1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0                      MK_ADDR_CONST(0x1160084)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0_CLR_SWR_PVA1_DMA1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0                       MK_ADDR_CONST(0x1160088)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0_SWR_PVA1_PROCCFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0                   MK_ADDR_CONST(0x116008c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0_SET_SWR_PVA1_PROCCFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0                   MK_ADDR_CONST(0x1160090)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0_CLR_SWR_PVA1_PROCCFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0                    MK_ADDR_CONST(0x1160094)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SCR                        PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0_SWR_PVA1_PM_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0                        MK_ADDR_CONST(0x1160098)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SCR                    PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0_SET_SWR_PVA1_PM_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0                        MK_ADDR_CONST(0x116009c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_SCR                    PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0_CLR_SWR_PVA1_PM_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0                       MK_ADDR_CONST(0x11600a0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_RESET_VAL                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NSYSPORESET_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_NRESET_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_DBGRESETN_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0_SWR_PVA1_PRESETDBGN_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0                   MK_ADDR_CONST(0x11600a4)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_RESET_VAL                         MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NSYSPORESET_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_NRESET_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_DBGRESETN_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0_SET_SWR_PVA1_PRESETDBGN_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0                   MK_ADDR_CONST(0x11600a8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_RESET_VAL                         MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_RESET_MASK                        MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_READ_MASK                         MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_NSYSPORESET_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_DBGRESETN_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0_CLR_SWR_PVA1_PRESETDBGN_RST_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0                        MK_ADDR_CONST(0x11600ac)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_SCR                    PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_RESET_VAL                      MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_DFLL_PVA_VPS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_PLLCV_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_PLLCV2_OUT0                   MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_PLLCV3_OUT0                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_SRC_CLK_M                 MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0_PVA1_VPS_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0                       MK_ADDR_CONST(0x11600b0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0_CLK_ENB_PVA1_VPS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0                   MK_ADDR_CONST(0x11600b4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0_SET_CLK_ENB_PVA1_VPS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0                   MK_ADDR_CONST(0x11600b8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0_CLR_CLK_ENB_PVA1_VPS_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0                      MK_ADDR_CONST(0x11600bc)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0_CLK_ENB_PVA1_VPS0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0                  MK_ADDR_CONST(0x11600c0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0_SET_CLK_ENB_PVA1_VPS0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0                  MK_ADDR_CONST(0x11600c4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0_CLR_CLK_ENB_PVA1_VPS0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0                      MK_ADDR_CONST(0x11600c8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0_CLK_ENB_PVA1_VPS1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0                  MK_ADDR_CONST(0x11600cc)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0_SET_CLK_ENB_PVA1_VPS1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0                  MK_ADDR_CONST(0x11600d0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0_CLR_CLK_ENB_PVA1_VPS1_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0                       MK_ADDR_CONST(0x11600d4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0_BOND_OUT_PVA1_VPS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0                      MK_ADDR_CONST(0x11600d8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0_BOND_OUT_PVA1_VPS0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0                      MK_ADDR_CONST(0x11600dc)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0_BOND_OUT_PVA1_VPS1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x11600e0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SCR                    PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS0_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x11600e4)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SCR                    PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0_SUPER_PVA1_VPS1_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0                  MK_ADDR_CONST(0x11600e8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0_SWR_PVA1_VPS0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0                      MK_ADDR_CONST(0x11600ec)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0_SET_SWR_PVA1_VPS0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0                      MK_ADDR_CONST(0x11600f0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0_CLR_SWR_PVA1_VPS0_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0                  MK_ADDR_CONST(0x11600f4)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SCR                      PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0_SWR_PVA1_VPS1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0                      MK_ADDR_CONST(0x11600f8)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0_SET_SWR_PVA1_VPS1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0                      MK_ADDR_CONST(0x11600fc)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_SCR                  PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_PRESETDBGN_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0_CLR_SWR_PVA1_VPS1_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0                   MK_ADDR_CONST(0x1160100)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0_SWR_PVA1_CFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0                       MK_ADDR_CONST(0x1160104)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0_SET_SWR_PVA1_CFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0                       MK_ADDR_CONST(0x1160108)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0_CLR_SWR_PVA1_CFG_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0                   MK_ADDR_CONST(0x116010c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0_SWR_PVA1_H1X_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0                       MK_ADDR_CONST(0x1160110)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0_SET_SWR_PVA1_H1X_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0                       MK_ADDR_CONST(0x1160114)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0_CLR_SWR_PVA1_H1X_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0                   MK_ADDR_CONST(0x1160118)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0_SWR_PVA1_SEC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0                       MK_ADDR_CONST(0x116011c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0_SET_SWR_PVA1_SEC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0                       MK_ADDR_CONST(0x1160120)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0_CLR_SWR_PVA1_SEC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0                 MK_ADDR_CONST(0x1160124)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SCR                     PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0_SWR_PVA1_RAMIC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0                     MK_ADDR_CONST(0x1160128)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SCR                         PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0_SET_SWR_PVA1_RAMIC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0                     MK_ADDR_CONST(0x116012c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_SCR                         PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0_CLR_SWR_PVA1_RAMIC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0                        MK_ADDR_CONST(0x1160130)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SCR                    PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0_SWR_PVA1_ACTMON_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0                    MK_ADDR_CONST(0x1160134)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SCR                        PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0_SET_SWR_PVA1_ACTMON_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0                    MK_ADDR_CONST(0x1160138)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_SCR                        PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0_CLR_SWR_PVA1_ACTMON_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0                   MK_ADDR_CONST(0x116013c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0_SWR_PVA1_TKE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0                       MK_ADDR_CONST(0x1160140)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0_SET_SWR_PVA1_TKE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0                       MK_ADDR_CONST(0x1160144)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0_CLR_SWR_PVA1_TKE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0                 MK_ADDR_CONST(0x1160148)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SCR                     PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0_SWR_PVA1_TSCTN_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0                     MK_ADDR_CONST(0x116014c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SCR                         PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0_SET_SWR_PVA1_TSCTN_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0                     MK_ADDR_CONST(0x1160150)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_SCR                         PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0_CLR_SWR_PVA1_TSCTN_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0                   MK_ADDR_CONST(0x1160154)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SCR                       PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0_SWR_PVA1_GTE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0                       MK_ADDR_CONST(0x1160158)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0_SET_SWR_PVA1_GTE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0                       MK_ADDR_CONST(0x116015c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_SCR                   PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0_CLR_SWR_PVA1_GTE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0                   MK_ADDR_CONST(0x1168000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_SCR                       PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0                    MK_ADDR_CONST(0x1168004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_SCR                        PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0                 MK_ADDR_CONST(0x1168008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_SCR                     PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0                        MK_ADDR_CONST(0x116800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_SCR                    PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0                     MK_ADDR_CONST(0x1168010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_SCR                         PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0                   MK_ADDR_CONST(0x1168014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_SCR                       PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0                    MK_ADDR_CONST(0x1168018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_SCR                        PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0                     MK_ADDR_CONST(0x116801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_SCR                         PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0                   MK_ADDR_CONST(0x1168020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_SCR                       PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_READ_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0                       MK_ADDR_CONST(0x1168024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_SCR                   PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0                       MK_ADDR_CONST(0x1168028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_SCR                   PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0                       MK_ADDR_CONST(0x116802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_SCR                   PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0                    MK_ADDR_CONST(0x1168030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_SCR                        PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0                     MK_ADDR_CONST(0x1168034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_SCR                         PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0_PVA1_CPU_AXI_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0                       MK_ADDR_CONST(0x1168038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_SCR                   PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0                        MK_ADDR_CONST(0x116803c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_SCR                    PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0                     MK_ADDR_CONST(0x1168040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_SCR                         PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0                    MK_ADDR_CONST(0x1168044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_SCR                        PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0                 MK_ADDR_CONST(0x1168048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_SCR                     PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_FAULT_REPORT_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0_PVA1_VPS_FMON_ACTION_RESET_REQ_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0                       MK_ADDR_CONST(0x116804c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_SCR                   PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_RANGE                      6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_DC_FAULT_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                   5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REPORT_OVERFLOW_ERROR_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_CLK_WINDOW_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_COUNTER_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0                        MK_ADDR_CONST(0x1168050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_SCR                    PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                 0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0                 MK_ADDR_CONST(0x1168054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_SCR                     PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_RESET_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_READ_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_WRITE_MASK                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_CLEAR_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_RANGE                    4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_FAULT_OUT_STATUS_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_RANGE                      3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_OVERFLOW_ERROR_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                      2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0_PVA1_VPS_FMON_DC_FAULT_TRUE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0                       MK_ADDR_CONST(0x1168058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_SCR                   PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_RESET_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_READ_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_WRITE_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_RANGE                 31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_RANGE                     2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0                   MK_ADDR_CONST(0x116805c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_SCR                       PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_DONE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0                   MK_ADDR_CONST(0x1168060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_SCR                       PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_RANGE                  2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0                   MK_ADDR_CONST(0x1168064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_SCR                       PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0_PVA1_VPS_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0                        MK_ADDR_CONST(0x1168068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_SCR                    PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0_PVA1_VPS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0                 MK_ADDR_CONST(0x116806c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_SCR                     PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_RANGE                  1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_REF_WINDOW_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0_PVA1_VPS_FMON_ENABLE_DEBUG_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0                        MK_ADDR_CONST(0x1169000)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_SCR                    PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0_CLK_SPARE_REG_PVA1_FMON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0                    MK_ADDR_CONST(0x1169004)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_SCR                        PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0_CLK_SPARE_REG_PVA1_VPS_FMON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0                        MK_ADDR_CONST(0x116a000)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_SCR                    PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0_CLK_SPARE_REG_PVA1_FUNC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0                      MK_ADDR_CONST(0x116f000)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA1_SCR_FMON_0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0                      MK_ADDR_CONST(0x116f004)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0                  MK_ADDR_CONST(0x116f008)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SCR                      0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_CVNAS_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0                      MK_ADDR_CONST(0x1170000)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SCR                  CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_0_SWR_CVNAS_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0                  MK_ADDR_CONST(0x1170004)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SCR                      CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0_SET_SWR_CVNAS_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0                  MK_ADDR_CONST(0x1170008)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_SCR                      CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0_CLR_SWR_CVNAS_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0                  MK_ADDR_CONST(0x117000c)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SCR                      CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0_SWR_CVNAS_FCM_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0                      MK_ADDR_CONST(0x1170010)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SCR                  CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0_SET_SWR_CVNAS_FCM_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0                      MK_ADDR_CONST(0x1170014)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_SCR                  CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0_CLR_SWR_CVNAS_FCM_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0                   MK_ADDR_CONST(0x1170018)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SCR                       CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0_SWR_CV_SIMON_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0                       MK_ADDR_CONST(0x117001c)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SCR                   CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0_SET_SWR_CV_SIMON_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0                       MK_ADDR_CONST(0x1170020)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_SCR                   CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0_CLR_SWR_CV_SIMON_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0                        MK_ADDR_CONST(0x1170024)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SCR                    CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_0_SWR_PVA_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0                    MK_ADDR_CONST(0x1170028)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SCR                        CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0_SET_SWR_PVA_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0                    MK_ADDR_CONST(0x117002c)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_SCR                        CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0_CLR_SWR_PVA_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0                  MK_ADDR_CONST(0x1171000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_SCR                      CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0_CLK_ENB_CVNAS_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0                      MK_ADDR_CONST(0x1171004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SCR                  CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0_SET_CLK_ENB_CVNAS_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0                      MK_ADDR_CONST(0x1171008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_SCR                  CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0_CLR_CLK_ENB_CVNAS_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0                  MK_ADDR_CONST(0x117100c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_SCR                      CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0_BOND_OUT_CVNAS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0                   MK_ADDR_CONST(0x1172000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_SCR                       CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_RESET_VAL                         MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_DFLL_CVNAS                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_PLLCV_OUT0                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_PLLCV2_OUT0                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_PLLCV3_OUT0                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_SRC_CLK_M                       MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0_CVNAS_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0                    MK_ADDR_CONST(0x1172004)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SCR                        CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_RESET_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_READ_MASK                  MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_WRITE_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0_SUPER_CVNAS_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0                  MK_ADDR_CONST(0x1178000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_SCR                      CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0_CVNAS_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0                   MK_ADDR_CONST(0x1178004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_SCR                       CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0_CVNAS_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0                        MK_ADDR_CONST(0x1178008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_SCR                    CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0                       MK_ADDR_CONST(0x117800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_SCR                   CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_RESET_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_READ_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_WRITE_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0_CVNAS_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0                    MK_ADDR_CONST(0x1178010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_SCR                        CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0_CVNAS_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0                  MK_ADDR_CONST(0x1178014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_SCR                      CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_READ_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0                   MK_ADDR_CONST(0x1178018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_SCR                       CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0_CVNAS_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0                    MK_ADDR_CONST(0x117801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_SCR                        CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_RESET_MASK                         MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_READ_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_WRITE_MASK                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0_CVNAS_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0                  MK_ADDR_CONST(0x1178020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_SCR                      CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_RESET_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_READ_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_WRITE_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0                      MK_ADDR_CONST(0x1178024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_SCR                  CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0_CVNAS_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0                      MK_ADDR_CONST(0x1178028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_SCR                  CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0_CVNAS_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0                      MK_ADDR_CONST(0x117802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_SCR                  CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0_CVNAS_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0                   MK_ADDR_CONST(0x1178030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_SCR                       CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0_CVNAS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0                    MK_ADDR_CONST(0x1178034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_SCR                        CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0_CVNAS_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0                     MK_ADDR_CONST(0x117f000)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SCR                         0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0                       MK_ADDR_CONST(0x117f004)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SCR                   0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0                   MK_ADDR_CONST(0xf10000)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_SCR                       0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_RESET_VAL                         MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_RESET_MASK                        MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_READ_MASK                         MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_WRITE_MASK                        MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                   17:17
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_RANGE                   16:16
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_RANGE                      6:6
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                      5:5
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                     4:4
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_RANGE                  3:3
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0_CVNAS_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0                  MK_ADDR_CONST(0xf10004)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_SCR                      0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_RESET_VAL                        MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_RESET_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_READ_MASK                        MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_WRITE_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                    31:28
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                  MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                    27:24
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_RANGE                     20:16
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_FIELD                     MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_RANGE                     4:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_DEFAULT                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0_CVNAS_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0                   MK_ADDR_CONST(0xf10008)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_SCR                       0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_RESET_VAL                         MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_RESET_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_READ_MASK                         MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_WRITE_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                   20:16
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                 MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                     15:8
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_RANGE                   7:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0_CVNAS_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0                   MK_ADDR_CONST(0xf1000c)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_SCR                       0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                     31:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0_CVNAS_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0                  MK_ADDR_CONST(0xf10010)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_SCR                      0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_RESET_VAL                        MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_RANGE                    31:16
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0_CVNAS_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0                  MK_ADDR_CONST(0xf10014)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_SCR                      0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_RESET_VAL                        MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_RESET_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_READ_MASK                        MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_WRITE_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                      31:28
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                  27:24
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                      23:20
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                       19:16
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_RANGE                        11:8
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                     7:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0_CVNAS_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0                   MK_ADDR_CONST(0xf10018)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_RESET_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_READ_MASK                         MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_RANGE                 15:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0_CVNAS_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0                      MK_ADDR_CONST(0xf1001c)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_SCR                  0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_RESET_VAL                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_RESET_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_READ_MASK                    MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_WRITE_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_RANGE                  31:24
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_RANGE                 23:16
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0_CVNAS_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0                       MK_ADDR_CONST(0xf10020)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                  7:3
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                   2:1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_RANGE                     0:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0_CVNAS_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0                      MK_ADDR_CONST(0xf10024)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_SCR                  0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_RESET_VAL                    MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_RESET_MASK                   MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_READ_MASK                    MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_WRITE_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                  13:13
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                   12:12
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_FIELD                        MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_RANGE                        11:3
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_DEFAULT                      MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                        2:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0_CVNAS_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xf10028

// Reserved address 0xf1002c

// Reserved address 0xf10030

// Reserved address 0xf10034

// Reserved address 0xf10038

// Reserved address 0xf1003c

// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0                 MK_ADDR_CONST(0xf10040)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0_CVNAS_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0                 MK_ADDR_CONST(0xf10044)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_READ_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0_CVNAS_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0                  MK_ADDR_CONST(0xf10048)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_RESET_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_READ_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0_CVNAS_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0                  MK_ADDR_CONST(0xf1004c)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_RESET_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_READ_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_FIELD                     MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                      MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0_CVNAS_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0                     MK_ADDR_CONST(0xf10050)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_SCR                         0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_RESET_MASK                  MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_READ_MASK                   MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_RANGE                   16:8
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                 7:4
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                 3:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0_CVNAS_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0                        MK_ADDR_CONST(0xf10054)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_RESET_VAL                      MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_RESET_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_READ_MASK                      MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_WRITE_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                        25:25
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                 19:16
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                  12:12
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_RANGE                    8:8
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_RANGE                     2:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0_CVNAS_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0                        MK_ADDR_CONST(0xf10058)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_SCR                    0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                      MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                   29:28
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                   23:20
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                     MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                     12:4
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                     3:2
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                  1:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0_CVNAS_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0                        MK_ADDR_CONST(0xf1005c)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_SCR                    0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_RESET_MASK                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_READ_MASK                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                      3:3
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0_CVNAS_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xf10060

// Reserved address 0xf10064

// Reserved address 0xf10068

// Register CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0                      MK_ADDR_CONST(0xf1006c)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_RESET_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_READ_MASK                    MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_RANGE                   31:28
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                 27:27
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_RANGE                      25:25
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_RANGE                    24:24
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_MSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                  19:16
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                       15:15
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                      2:0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0_CVNAS_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0                     MK_ADDR_CONST(0xf10070)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_SCR                         0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0_CVNAS_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0                     MK_ADDR_CONST(0xf10074)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_SCR                         0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0_CVNAS_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0xf10078

// Register CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0                      MK_ADDR_CONST(0xf1007c)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_RESET_VAL                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_RANGE                    3:3
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_INIT_ENUM                        DFLL_CVNAS_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_DFLL_CVNAS_CLK_OUT_PTO_OBS                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_NAFLLCVNAS_PTO_ROOT_CLK_SEL_DFLL_CVNAS_CLK_OUT_PTO_DIV2                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_SHIFT)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_RANGE                      2:0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_DEFAULT                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_INIT_ENUM                  CLK_NULL
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_DFLL_CVNAS_CLK                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_DFLL_CVNAS_PRE_SKP_CLK                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_DFLL_CVNAS_FLL_UPD_CLK                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_ADC_SOC_REF_CVNAS_CLK                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_AVFS_2_CAR_PCLK                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_OSC_DIV_CLK                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0_CVNAS_PTS_CLK_NULL                   MK_ENUM_CONST(7)


// Reserved address 0x1180000

// Reserved address 0x1180004

// Reserved address 0x1180008

// Reserved address 0x118000c

// Reserved address 0x1180010

// Reserved address 0x1180014

// Reserved address 0x1180018

// Reserved address 0x118001c

// Reserved address 0x1180020

// Reserved address 0x1180024

// Reserved address 0x1180028

// Reserved address 0x118002c

// Reserved address 0x1180030

// Reserved address 0x1180034

// Reserved address 0x1180038

// Reserved address 0x118003c

// Reserved address 0x1180040

// Reserved address 0x1180044

// Reserved address 0x1180048

// Reserved address 0x118004c

// Reserved address 0x1180050

// Reserved address 0x1180054

// Reserved address 0x1180058

// Reserved address 0x118005c

// Reserved address 0x1180060

// Reserved address 0x1180064

// Reserved address 0x1180068

// Reserved address 0x118006c

// Reserved address 0x1180070

// Reserved address 0x1180074

// Reserved address 0x1180078

// Reserved address 0x118007c

// Reserved address 0x1180080

// Reserved address 0x1180084

// Reserved address 0x1180088

// Reserved address 0x118008c

// Register CLK_RST_CONTROLLER_CV_ADC_CTRL_0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0                        MK_ADDR_CONST(0x1180090)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_SCR                    0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_RESET_VAL                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_RANGE                   23:23
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CLOCK_GATE_DISABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_RANGE                  22:22
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_CAPTURE_ACC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_RANGE                   21:21
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_RANGE                      20:20
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ACC_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_RANGE                        19:4
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_RANGE                  3:3
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_SEL_ADC_LSB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_RANGE                       2:2
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CTRL_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_RANGE                       1:1
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_CFG_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_RANGE                     0:0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL_0_CV_ADC_CTRL_ADC_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_CTRL2_0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0                       MK_ADDR_CONST(0x1180094)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_SCR                   0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_RANGE                   31:0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL2_0_CV_ADC_CTRL2_ADC_CTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_CTRL3_0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0                       MK_ADDR_CONST(0x1180098)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_SCR                   0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_RANGE                     31:0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_CTRL3_0_CV_ADC_CTRL3_SETUP2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_MONITOR_0
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0                     MK_ADDR_CONST(0x118009c)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_SCR                         0
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_RESET_MASK                  MK_MASK_CONST(0xff13fc)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_READ_MASK                   MK_MASK_CONST(0xff13fc)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_WRITE_MASK                  MK_MASK_CONST(0x1000)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_RANGE                       23:16
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_STAT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_RANGE                       12:12
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_CAPTURE_ADC_DOUT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_RANGE                       9:2
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_MONITOR_0_CV_ADC_MONITOR_ADC_DOUT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0                    MK_ADDR_CONST(0x11800a0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_SCR                        0
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_RESET_MASK                         MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_READ_MASK                  MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_WRITE_MASK                         MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_RANGE                      16:16
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_SW_OVERRIDE_ADC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_FIELD                     MK_FIELD_CONST(0x7f, CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_RANGE                     7:1
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_DOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0_CV_ADC_OVERRIDE_ADC_SAMPLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_ACC_0
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0                 MK_ADDR_CONST(0x11800a4)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_SCR                     0
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_ACC_0_CV_ADC_ACC_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0                 MK_ADDR_CONST(0x11800a8)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_SCR                     0
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0_CV_ADC_NUM_SAMPLES_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0                 MK_ADDR_CONST(0x11800ac)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_RESET_VAL                       MK_MASK_CONST(0xe03)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_RESET_MASK                      MK_MASK_CONST(0xff03)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_READ_MASK                       MK_MASK_CONST(0xff03)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_WRITE_MASK                      MK_MASK_CONST(0xff03)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_RANGE                        15:8
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_DEFAULT                      MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_RANGE                    1:1
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_INIT_ENUM                        OSC_DIV
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_PLLP_OUT0                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_SEL_OSC_DIV                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0_CV_ADC_REF_CLK_CFG_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0                    MK_ADDR_CONST(0x1181000)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_RESET_MASK                         MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_READ_MASK                  MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_RANGE                        10:10
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_RESET_COUNTER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_RANGE                 9:7
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_ADC_DOUT_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_RANGE                 6:4
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_COUNTER_VALUE_UPDATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_RANGE                   3:1
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_RANGE                        0:0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0_CV_ADC_OBS_CTRL_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0                       MK_ADDR_CONST(0x1181004)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_SCR                   0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_RANGE                   31:16
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_TROUGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_RANGE                     15:0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0_CV_ADC_OBS_WAIT_TIME_WAIT_TIME_PEAK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0                    MK_ADDR_CONST(0x1181008)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_FIELD                       MK_FIELD_CONST(0x7f, CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_RANGE                       6:0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0_CV_ADC_OBS_DATA_ADC_DOUT_SAVED_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0                   MK_ADDR_CONST(0x118100c)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_SCR                       0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_FIELD                      MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0_CV_ADC_OBS_TSTAMP_SAVED0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0                   MK_ADDR_CONST(0x1181010)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_SCR                       0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0_CV_ADC_OBS_TSTAMP_SAVED1_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0                 MK_ADDR_CONST(0x1181014)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_SCR                     0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0_CV_ADC_OBS_TSTAMP_CURRENT0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0                 MK_ADDR_CONST(0x1181018)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_SCR                     0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0_CV_ADC_OBS_TSTAMP_CURRENT1_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0                        MK_ADDR_CONST(0x1000000)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NSYSPORESET_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_NRESET_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_DBGRESETN_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0_SWR_RCE_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0                    MK_ADDR_CONST(0x1000004)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SCR                        RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NSYSPORESET_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_NRESET_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_DBGRESETN_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0_SET_SWR_RCE_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0                    MK_ADDR_CONST(0x1000008)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_SCR                        RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_RESET_MASK                         MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_READ_MASK                  MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_NSYSPORESET_RST_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_DBGRESETN_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0_CLR_SWR_RCE_PRESETDBGN_RST_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0                 MK_ADDR_CONST(0x100000c)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SCR                     RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0_SWR_RCE_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0                     MK_ADDR_CONST(0x1000010)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SCR                         RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0_SET_SWR_RCE_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0                     MK_ADDR_CONST(0x1000014)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_SCR                         RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0_CLR_SWR_RCE_ACTMON_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0                     MK_ADDR_CONST(0x1000018)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SCR                         RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0_SWR_RCE_PM_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0                 MK_ADDR_CONST(0x100001c)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SCR                     RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0_SET_SWR_RCE_PM_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0                 MK_ADDR_CONST(0x1000020)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_SCR                     RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0_CLR_SWR_RCE_PM_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0                    MK_ADDR_CONST(0x1000024)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SCR                        RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0_SWR_RCE_DMA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0                        MK_ADDR_CONST(0x1000028)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0_SET_SWR_RCE_DMA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0                        MK_ADDR_CONST(0x100002c)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0_CLR_SWR_RCE_DMA_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0                   MK_ADDR_CONST(0x1000030)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SCR                       RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0_SWR_TSCTNRCE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0                       MK_ADDR_CONST(0x1000034)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SCR                   RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0_SET_SWR_TSCTNRCE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0                       MK_ADDR_CONST(0x1000038)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_SCR                   RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0_CLR_SWR_TSCTNRCE_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0                    MK_ADDR_CONST(0x100003c)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SCR                        RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0_SWR_RCE_TKE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0                        MK_ADDR_CONST(0x1000040)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0_SET_SWR_RCE_TKE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0                        MK_ADDR_CONST(0x1000044)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0_CLR_SWR_RCE_TKE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0                    MK_ADDR_CONST(0x1000048)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SCR                        RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0_SWR_RCE_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0                        MK_ADDR_CONST(0x100004c)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0_SET_SWR_RCE_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0                        MK_ADDR_CONST(0x1000050)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0_CLR_SWR_RCE_GTE_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0                    MK_ADDR_CONST(0x1000054)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SCR                        RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0_SWR_RCE_CFG_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0                        MK_ADDR_CONST(0x1000058)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0_SET_SWR_RCE_CFG_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0                        MK_ADDR_CONST(0x100005c)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0_CLR_SWR_RCE_CFG_RST_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0                    MK_ADDR_CONST(0x1001000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_SCR                        RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_RESET_VAL                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0_CLK_ENB_RCE_CPU_NIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0                        MK_ADDR_CONST(0x1001004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SCR                    RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_RESET_VAL                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0_SET_CLK_ENB_RCE_CPU_NIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0                        MK_ADDR_CONST(0x1001008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_SCR                    RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_RESET_VAL                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0_CLR_CLK_ENB_RCE_CPU_NIC_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0                    MK_ADDR_CONST(0x1002000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_RANGE                     1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0_BOND_OUT_RCE_CPU_NIC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0                     MK_ADDR_CONST(0x1003000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_SCR                         RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RESET_MASK                  MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_READ_MASK                   MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_PLLC_OUT0                       MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_PLLC2_OUT0                      MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_PLLC3_OUT0                      MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_CLK_DFLL_RCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_RANGE                        17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_SWITCH_DIVIDE_BUSY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0_RCE_CPU_NIC_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NIC_RATE_0
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0                       MK_ADDR_CONST(0x1003004)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_SCR                   RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RESET_VAL                     MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RESET_MASK                    MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_READ_MASK                     MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_WRITE_MASK                    MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_RANGE                  4:4
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_RANGE                    1:0
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NIC_RATE_0_RCE_NIC_RATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0                  MK_ADDR_CONST(0x1003008)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_SCR                      RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RESET_VAL                        MK_MASK_CONST(0x40)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_RANGE                     15:0
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_DEFAULT                   MK_MASK_CONST(0x40)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0_RCE_NRESET_CYCLE_COUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0                        MK_ADDR_CONST(0x1008000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_SCR                    RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0                 MK_ADDR_CONST(0x1008004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_SCR                     RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0_RCE_CPU_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0                      MK_ADDR_CONST(0x1008008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_SCR                  RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0                     MK_ADDR_CONST(0x100800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_SCR                         RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RESET_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_READ_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_WRITE_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0                  MK_ADDR_CONST(0x1008010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_SCR                      RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0_RCE_CPU_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0                        MK_ADDR_CONST(0x1008014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_SCR                    RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0                 MK_ADDR_CONST(0x1008018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_SCR                     RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0_RCE_CPU_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0                  MK_ADDR_CONST(0x100801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_SCR                      RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_WRITE_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0_RCE_CPU_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0                        MK_ADDR_CONST(0x1008020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_SCR                    RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RESET_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_READ_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_WRITE_MASK                     MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0                    MK_ADDR_CONST(0x1008024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_SCR                        RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0                    MK_ADDR_CONST(0x1008028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_SCR                        RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0                    MK_ADDR_CONST(0x100802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_SCR                        RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0_RCE_CPU_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0                 MK_ADDR_CONST(0x1008030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_SCR                     RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0_RCE_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0                  MK_ADDR_CONST(0x1008034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_SCR                      RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0_RCE_CPU_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Reserved address 0x1010000

// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0                      MK_ADDR_CONST(0x1020000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCR                  RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_READ_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_WRITE_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_DFLL_RCE                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0_RCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0                       MK_ADDR_CONST(0x1020004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                   RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                    MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_RCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0                        MK_ADDR_CONST(0x1020008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCR                    RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_RCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0                        MK_ADDR_CONST(0x102000c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCR                    RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_RCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0                     MK_ADDR_CONST(0x1020010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCR                         RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                   MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_RCE                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0                 MK_ADDR_CONST(0x1020014)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_SCR                     RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0_RCE_PLL_ACTIVE_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0                  MK_ADDR_CONST(0x1020018)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                      RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0                   MK_ADDR_CONST(0x102001c)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_SCR                       RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0_RCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0                   MK_ADDR_CONST(0x1020020)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_SCR                       RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0_RCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0                        MK_ADDR_CONST(0x1020024)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_SCR                    RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0_RCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0                  MK_ADDR_CONST(0x1020028)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_SCR                      RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RESET_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_READ_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_WRITE_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_CLK_DFLL_RCE                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0_RCE_APB_ACTIVE_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0                   MK_ADDR_CONST(0x102002c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                       RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                        MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_RCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0                    MK_ADDR_CONST(0x1020030)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCR                        RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_RCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0_RCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0                    MK_ADDR_CONST(0x1020034)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_SCR                        RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_READ_MASK                  MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                         MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_RCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0_RCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0                 MK_ADDR_CONST(0x1020038)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCR                     RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                       MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                      MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_RCE                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0                  MK_ADDR_CONST(0x102003c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_SCR                      RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_CLK_DFLL_RCE                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0_RCE_CPU_NIC_ACTIVE_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0                   MK_ADDR_CONST(0x1020040)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCR                       RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                         MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_RCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0                    MK_ADDR_CONST(0x1020044)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCR                        RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_RCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0                    MK_ADDR_CONST(0x1020048)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCR                        RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_DFLL_RCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0_RCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0                 MK_ADDR_CONST(0x102004c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCR                     RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_VAL                       MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_READ_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_WRITE_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_RCE                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0                     MK_ADDR_CONST(0x1020050)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_SCR                         RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_IDDQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0_RCE_PLL_ACTIVE_PLL_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0                      MK_ADDR_CONST(0x1020054)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_SCR                  RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0_RCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0                       MK_ADDR_CONST(0x1020058)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_SCR                   RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0_RCE_PLL_IDLE_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0                       MK_ADDR_CONST(0x102005c)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_SCR                   RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0_RCE_PLL_STBY_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0                    MK_ADDR_CONST(0x1020060)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_SCR                        RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0_RCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0                      MK_ADDR_CONST(0x1020064)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_SCR                  RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RESET_VAL                    MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RESET_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_READ_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_WRITE_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_CLK_DFLL_RCE                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0_RCE_APB_ACTIVE_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0                       MK_ADDR_CONST(0x1020068)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_SCR                   RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                     MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_READ_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                    MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_RCE                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0_RCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0                        MK_ADDR_CONST(0x102006c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_RCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0_RCE_APB_IDLE_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0                        MK_ADDR_CONST(0x1020070)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_SCR                    RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RESET_VAL                      MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RESET_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_READ_MASK                      MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_WRITE_MASK                     MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_CLK_DFLL_RCE                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0_RCE_APB_STBY_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0                     MK_ADDR_CONST(0x1020074)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_SCR                         RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RESET_VAL                   MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_RCE                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0_RCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0                   MK_ADDR_CONST(0x1020078)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_SCR                       RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RESET_MASK                        MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_READ_MASK                         MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_WRITE_MASK                        MK_MASK_CONST(0x40000007)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_RANGE                      31:31
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_SHIFT                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_RANGE                      30:30
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_MSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_LSB                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_RANGE                    2:0
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0_RCE_SW_TGT_STATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0                      MK_ADDR_CONST(0x102007c)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_SCR                  RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RESET_VAL                    MK_MASK_CONST(0xc20)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RESET_MASK                   MK_MASK_CONST(0xfef)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_READ_MASK                    MK_MASK_CONST(0xfef)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_WRITE_MASK                   MK_MASK_CONST(0xfef)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_RANGE                   11:11
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_ASYNC_OVR_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_RANGE                     10:10
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_DISABLE_PLL_HW_CONTROL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_RANGE                 9:9
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_CONFIG_PROPAGATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_RANGE                       8:8
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_BYP_PLL_CONFIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_RANGE                 7:7
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_SEQUENCER_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_RANGE                   6:6
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_PLL_SEQUENCER_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_RANGE                   5:5
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_CPU_NIC_SWDIV_DIS_HWCTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_RANGE                       3:3
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SEQUENCER_INTF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_SWDIV_RST_ACK_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_RANGE                    1:1
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_SWDIV_FSM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_RANGE                      0:0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0_RCE_RESET_PLL_FSM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0                        MK_ADDR_CONST(0x1020080)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_SCR                    RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RESET_VAL                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RESET_MASK                     MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_READ_MASK                      MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_WRITE_MASK                     MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_RANGE                  31:31
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_RANGE                  30:30
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_CAR_SEQ_INTR_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_RANGE                       29:29
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_ACK_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_FIELD                    MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_RANGE                    11:0
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_DEFAULT                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0_RCE_SEQ_TIMEOUT_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0                   MK_ADDR_CONST(0x1020084)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_SCR                       RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RESET_VAL                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RESET_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_READ_MASK                         MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_WRITE_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_RANGE                     31:31
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_FIELD                    MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_RANGE                    11:0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_DEFAULT                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_DEFAULT_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0_RCE_PLL_DLY_LOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0                  MK_ADDR_CONST(0x1020088)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCR                      RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_VAL                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_READ_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_WRITE_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_FIELD                  MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_RANGE                  11:0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_DEFAULT_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0_RCE_PLL_DLY_PWRUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0                       MK_ADDR_CONST(0x102008c)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCR                   RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_VAL                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_READ_MASK                     MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_WRITE_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_RANGE                      31:31
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_FIELD                  MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_RANGE                  11:0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_DEFAULT                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_DEFAULT_MASK                   MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RCE_SWDIV_DLY_SWDIVCFG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0                  MK_ADDR_CONST(0x1020090)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCR                      RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_VAL                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_READ_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_WRITE_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_RANGE                   31:31
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_FIELD                       MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_RANGE                       11:0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_DEFAULT                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_DEFAULT_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0_RCE_SWDIV_DLY_PLLCFG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0                    MK_ADDR_CONST(0x1020094)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_SCR                        RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RESET_VAL                  MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_WRITE_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_RANGE                        5:0
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT                      MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0_RCE_SEQUENCER_1USEC_OSC_CYCLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0                   MK_ADDR_CONST(0x1020098)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_SCR                       RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_RANGE                        3:3
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_RANGE                    2:0
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0_RCE_SEQ_MODE_SEL_OVR_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0                     MK_ADDR_CONST(0x102009c)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_SCR                         RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RESET_MASK                  MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_READ_MASK                   MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_RANGE                 31:31
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SM_SWDIV_BUSY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_RANGE                        30:30
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CONFIGURED_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_RANGE                        7:4
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_PLL_CURR_STATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_RANGE                      3:0
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0_RCE_SEQ_SWDIV_CURR_STATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0                      MK_ADDR_CONST(0x10200a0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_SCR                  0
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RESET_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_READ_MASK                    MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_RANGE                 31:31
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_EN_SEQ_DBG_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_FIELD                     MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_RANGE                     11:0
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_DEFAULT_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0_RCE_LAST_SEQ_COUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0                     MK_ADDR_CONST(0x1030000)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_SCR                         RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RESET_VAL                   MK_MASK_CONST(0x82)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RESET_MASK                  MK_MASK_CONST(0x300fb)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_READ_MASK                   MK_MASK_CONST(0x300fb)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_WRITE_MASK                  MK_MASK_CONST(0xfb)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                       17:17
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_RANGE                       16:16
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_RANGE                       7:7
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_RANGE                  6:6
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                  5:5
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                 4:4
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_RANGE                      3:3
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0_RCE_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0                    MK_ADDR_CONST(0x1030004)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_SCR                        RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RESET_VAL                  MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RESET_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_READ_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_WRITE_MASK                         MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                        31:28
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                        27:24
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                      MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_RANGE                 20:16
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_RANGE                 4:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0_RCE_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0                     MK_ADDR_CONST(0x1030008)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_SCR                         RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RESET_VAL                   MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RESET_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_READ_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_WRITE_MASK                  MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                       MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                       20:16
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                     MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                 15:8
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_RANGE                       7:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0_RCE_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0                     MK_ADDR_CONST(0x103000c)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_SCR                         RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                 31:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0_RCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0                    MK_ADDR_CONST(0x1030010)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_SCR                        RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RESET_VAL                  MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_RANGE                        31:16
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_RANGE                     15:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_DEFAULT                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0_RCE_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0                    MK_ADDR_CONST(0x1030014)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_SCR                        RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RESET_VAL                  MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RESET_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_READ_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_WRITE_MASK                         MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                  31:28
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                      27:24
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                  23:20
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                   MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                   19:16
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_RANGE                    11:8
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                 7:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0_RCE_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0                     MK_ADDR_CONST(0x1030018)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_SCR                         RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RESET_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_READ_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_RANGE                     15:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0_RCE_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0                        MK_ADDR_CONST(0x103001c)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_SCR                    RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RESET_VAL                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RESET_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_READ_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_WRITE_MASK                     MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_RANGE                      31:24
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_RANGE                     23:16
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0_RCE_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0                 MK_ADDR_CONST(0x1030020)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_SCR                     RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                      MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                      7:3
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                       2:1
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_RANGE                 0:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0_RCE_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0                        MK_ADDR_CONST(0x1030024)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_SCR                    0
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RESET_VAL                      MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RESET_MASK                     MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_READ_MASK                      MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                      13:13
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                       12:12
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_FIELD                    MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_RANGE                    11:3
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_DEFAULT                  MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                    2:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0_RCE_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0x1030028

// Reserved address 0x103002c

// Reserved address 0x1030030

// Reserved address 0x1030034

// Reserved address 0x1030038

// Reserved address 0x103003c

// Register CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0                   MK_ADDR_CONST(0x1030040)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_SCR                       RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                        MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0_RCE_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0                   MK_ADDR_CONST(0x1030044)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_SCR                       RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_READ_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                       MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                        MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0_RCE_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0                    MK_ADDR_CONST(0x1030048)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_SCR                        RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RESET_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_READ_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0_RCE_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0                    MK_ADDR_CONST(0x103004c)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RESET_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_READ_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0_RCE_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0                       MK_ADDR_CONST(0x1030050)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_SCR                   0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RESET_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_READ_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_RANGE                       16:8
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                     7:4
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                     3:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0_RCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0                  MK_ADDR_CONST(0x1030054)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_SCR                      RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RESET_VAL                        MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RESET_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_READ_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_WRITE_MASK                       MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                    25:25
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                     19:16
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                      12:12
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_RANGE                        8:8
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0_RCE_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0                  MK_ADDR_CONST(0x1030058)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_SCR                      RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                       MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                       29:28
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                       23:20
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                 12:4
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                 3:2
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                      1:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0_RCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0                  MK_ADDR_CONST(0x103005c)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_SCR                      RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RESET_MASK                       MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_READ_MASK                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                  3:3
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0_RCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x1030060

// Reserved address 0x1030064

// Reserved address 0x1030068

// Register CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0                        MK_ADDR_CONST(0x103006c)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_SCR                    RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RESET_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_READ_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_WRITE_MASK                     MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_RANGE                       31:28
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                     27:27
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_RANGE                  25:25
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_RANGE                        24:24
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                      19:16
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                   15:15
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                  2:0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0_RCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0                       MK_ADDR_CONST(0x1030070)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_SCR                   RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_FIELD                      MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0_RCE_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0                       MK_ADDR_CONST(0x1030074)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_SCR                   RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0_RCE_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1030078

// Register CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0                        MK_ADDR_CONST(0x103007c)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_SCR                    0
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_RANGE                        3:3
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_INIT_ENUM                    DFLL_RCE_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_DFLL_RCE_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_NAFLLRCE_PTO_ROOT_CLK_SEL_DFLL_RCE_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_SHIFT)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_RANGE                  2:0
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_DEFAULT                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_INIT_ENUM                      CLK_NULL
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_DFLL_RCE_CLK                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_DFLL_RCE_PRE_SKP_CLK                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_DFLL_RCE_FLL_UPD_CLK                   MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_ADC_SOC_REF_RCE_CLK                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_CLK_NULL_2                     MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_OSC_DIV_CLK                    MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0_RCE_PTS_CLK_NULL                       MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0                       MK_ADDR_CONST(0x1040000)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_SCR                   RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0_CLK_SPARE_REG_RCE_SHARED_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0                      MK_ADDR_CONST(0x1041000)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_SCR                  RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0_CLK_SPARE_REG_RCE_PRIVATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0                 MK_ADDR_CONST(0x1042000)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_SCR                     RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0_CLK_SPARE_REG_RCE_DVFS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0                 MK_ADDR_CONST(0x1043000)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_SCR                     RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0_CLK_SPARE_REG_RCE_FMON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0                     MK_ADDR_CONST(0x10ef000)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SCR                         0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_SHARED_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0                    MK_ADDR_CONST(0x10ef004)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SCR                        0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0                       MK_ADDR_CONST(0x10ef008)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SCR                   0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_SCR_DVFS_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0                   MK_ADDR_CONST(0x10ef00c)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0                  MK_ADDR_CONST(0xf30000)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_RESET_VAL                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_RESET_MASK                       MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_READ_MASK                        MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_WRITE_MASK                       MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                 17:17
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_RANGE                 16:16
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_RANGE                    6:6
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                    5:5
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                   4:4
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_RANGE                        3:3
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0_NVENC1_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0                 MK_ADDR_CONST(0xf30004)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_SCR                     0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_RESET_VAL                       MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_RESET_MASK                      MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_READ_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_WRITE_MASK                      MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                  31:28
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                  27:24
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_RANGE                   20:16
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_RANGE                   4:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0_NVENC1_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0                  MK_ADDR_CONST(0xf30008)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_RESET_VAL                        MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_RESET_MASK                       MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_READ_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_WRITE_MASK                       MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                 20:16
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                       MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                   15:8
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0_NVENC1_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0                  MK_ADDR_CONST(0xf3000c)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                   31:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0_NVENC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0                 MK_ADDR_CONST(0xf30010)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_SCR                     0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_RESET_VAL                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_RANGE                  31:16
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_RANGE                       15:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0_NVENC1_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0                 MK_ADDR_CONST(0xf30014)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_SCR                     0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_RESET_VAL                       MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_RESET_MASK                      MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_READ_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_WRITE_MASK                      MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                    31:28
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                        27:24
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                    23:20
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                     19:16
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_RANGE                      11:8
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0_NVENC1_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0                  MK_ADDR_CONST(0xf30018)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_RANGE                       15:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0_NVENC1_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0                     MK_ADDR_CONST(0xf3001c)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_RESET_VAL                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_RESET_MASK                  MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_READ_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_WRITE_MASK                  MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_RANGE                        31:24
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_RANGE                       23:16
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0_NVENC1_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0                      MK_ADDR_CONST(0xf30020)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                        7:3
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                 2:1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_RANGE                   0:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0_NVENC1_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0                     MK_ADDR_CONST(0xf30024)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_RESET_VAL                   MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_RESET_MASK                  MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_READ_MASK                   MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_WRITE_MASK                  MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                        13:13
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                 12:12
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_FIELD                      MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_RANGE                      11:3
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_DEFAULT                    MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0_NVENC1_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xf30028

// Reserved address 0xf3002c

// Reserved address 0xf30030

// Reserved address 0xf30034

// Reserved address 0xf30038

// Reserved address 0xf3003c

// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0                        MK_ADDR_CONST(0xf30040)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_SCR                    0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0_NVENC1_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0                        MK_ADDR_CONST(0xf30044)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_SCR                    0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                     MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_READ_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                     MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0_NVENC1_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0                 MK_ADDR_CONST(0xf30048)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0_NVENC1_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0                 MK_ADDR_CONST(0xf3004c)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_RESET_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_READ_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0_NVENC1_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0                    MK_ADDR_CONST(0xf30050)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_SCR                        0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_RESET_MASK                         MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_READ_MASK                  MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_RANGE                 16:8
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                       7:4
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                       3:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0_NVENC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0                       MK_ADDR_CONST(0xf30054)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_RESET_VAL                     MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_RESET_MASK                    MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_READ_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_WRITE_MASK                    MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                      25:25
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                       19:16
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                        12:12
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_RANGE                  8:8
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_RANGE                   2:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0_NVENC1_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0                       MK_ADDR_CONST(0xf30058)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_SCR                   0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                    MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                    MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                 29:28
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                 23:20
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                   12:4
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                   3:2
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                        1:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0_NVENC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0                       MK_ADDR_CONST(0xf3005c)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_SCR                   0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_RESET_MASK                    MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_READ_MASK                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                    3:3
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0_NVENC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xf30060

// Reserved address 0xf30064

// Reserved address 0xf30068

// Register CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0                     MK_ADDR_CONST(0xf3006c)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_RESET_MASK                  MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_READ_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_WRITE_MASK                  MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_RANGE                 31:28
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                       27:27
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_RANGE                    25:25
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_RANGE                  24:24
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                        19:16
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                     15:15
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                    2:0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0_NVENC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0                    MK_ADDR_CONST(0xf30070)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_SCR                        0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_FIELD                        MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0_NVENC1_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0                    MK_ADDR_CONST(0xf30074)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_SCR                        0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_RANGE                        3:0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0_NVENC1_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xf30078

// Register CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0                     MK_ADDR_CONST(0xf3007c)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_INIT_ENUM                      DFLL_NVENC1_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_DFLL_NVENC1_CLK_OUT_PTO_OBS                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NAFLLNVENC1_PTO_ROOT_CLK_SEL_DFLL_NVENC1_CLK_OUT_PTO_DIV2                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_RANGE                    2:0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_DEFAULT                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_INIT_ENUM                        CLK_NULL
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_DFLL_NVENC1_CLK                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_DFLL_NVENC1_PRE_SKP_CLK                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_DFLL_NVENC1_FLL_UPD_CLK                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_ADC_SOC_REF_NVENC1_CLK                   MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_AVFS_8_CAR_PCLK                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_OSC_DIV_CLK                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0_NVENC1_PTS_CLK_NULL                 MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0                    MK_ADDR_CONST(0x1120000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0_CLK_ENB_IST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0                        MK_ADDR_CONST(0x1120004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0_SET_CLK_ENB_IST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0                        MK_ADDR_CONST(0x1120008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0_CLR_CLK_ENB_IST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0                    MK_ADDR_CONST(0x1121000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_READ_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0_BOND_OUT_IST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_IST_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0                     MK_ADDR_CONST(0x1122000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_RESET_VAL                   MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_RESET_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_READ_MASK                   MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_WRITE_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_PLLP_OUT0                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_CLK_M                   MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_SRC_PLLC4_MUXED                     MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IST_0_IST_CLK_DIVISOR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0                  MK_ADDR_CONST(0x2f0000)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0_SWR_NVHS_RAIL_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0                      MK_ADDR_CONST(0x2f0004)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0_SET_SWR_NVHS_RAIL_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0                      MK_ADDR_CONST(0x2f0008)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0_CLR_SWR_NVHS_RAIL_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVLINK_0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0                     MK_ADDR_CONST(0x1260000)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SCR                         NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_0_SWR_NVLINK_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0                 MK_ADDR_CONST(0x1260004)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SCR                     NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0_SET_SWR_NVLINK_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0                 MK_ADDR_CONST(0x1260008)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_SCR                     NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0_CLR_SWR_NVLINK_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0                 MK_ADDR_CONST(0x1261000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_SCR                     NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_RESET_VAL                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_RESET_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_READ_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_WRITE_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_RANGE                 0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_TX_NVLINK_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0_CLK_ENB_RX_NVLINK_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0                     MK_ADDR_CONST(0x1261004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SCR                         NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_RESET_VAL                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_RANGE                 0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_TX_NVLINK_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0_SET_CLK_ENB_RX_NVLINK_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0                     MK_ADDR_CONST(0x1261008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_SCR                         NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_RESET_VAL                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_RESET_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_READ_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_RANGE                 0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_TX_NVLINK_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0_CLR_CLK_ENB_RX_NVLINK_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0                    MK_ADDR_CONST(0x1262000)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_SCR                        NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x100)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0x711)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0x711)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_RANGE                     10:8
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_INIT_ENUM                 TX
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_TX                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_RXL0                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_RXCLK_STS_RXL7                      MK_ENUM_CONST(4)

#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_RANGE                     4:4
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_INIT_ENUM                 OFF
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_OFF                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_STS_ON                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_RANGE                    0:0
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_INIT_ENUM                        OFF
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0_NVLINK_TXCLK_CTRL_ON                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0                  MK_ADDR_CONST(0x1263000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_SCR                      NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0_CLK_ENB_NVLINK_SYSCLK_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0                      MK_ADDR_CONST(0x1263004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SCR                  NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0_SET_CLK_ENB_NVLINK_SYSCLK_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0                      MK_ADDR_CONST(0x1263008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_SCR                  NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0_CLR_CLK_ENB_NVLINK_SYSCLK_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0                 MK_ADDR_CONST(0x1264000)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_SCR                     NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_RESET_MASK                      MK_MASK_CONST(0x60000003)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_READ_MASK                       MK_MASK_CONST(0x60000003)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_WRITE_MASK                      MK_MASK_CONST(0x60000003)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_RANGE                     30:29
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_MSB                       MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_PLLREFE_VCOCLK                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_SRC_CLK_M                     MK_ENUM_CONST(0)

#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_RANGE                 1:0
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0_NVLINK_SYSCLK_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0                  MK_ADDR_CONST(0x1264004)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_SCR                      NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_RESET_VAL                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_DEFAULT                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0_NVLINK_TX_DIV_CLK_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0                      MK_ADDR_CONST(0x1265000)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_SCR                  NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0_CLK_SPARE_REG_NVLINK_CORE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0                     MK_ADDR_CONST(0x1266000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_SCR                         NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0                      MK_ADDR_CONST(0x1266004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_SCR                  NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0                   MK_ADDR_CONST(0x1266008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_SCR                       NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0                  MK_ADDR_CONST(0x126600c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_SCR                      NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0                       MK_ADDR_CONST(0x1266010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_SCR                   NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_FAULT_REPORT_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0_NVLINK_SYS_FMON_ACTION_RESET_REQ_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0                     MK_ADDR_CONST(0x1266014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_SCR                         NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_RANGE                  6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_DC_FAULT_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                       5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REPORT_OVERFLOW_ERROR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_CLK_WINDOW_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_COUNTER_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0                      MK_ADDR_CONST(0x1266018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_SCR                  NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                     0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0                       MK_ADDR_CONST(0x126601c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_SCR                   NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_RESET_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_READ_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_WRITE_MASK                    MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_CLEAR_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_FAULT_OUT_STATUS_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_RANGE                  3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_OVERFLOW_ERROR_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                  2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0_NVLINK_SYS_FMON_DC_FAULT_TRUE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0                     MK_ADDR_CONST(0x1266020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_SCR                         NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_RESET_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_READ_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_WRITE_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_RANGE                 2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0                 MK_ADDR_CONST(0x1266024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_SCR                     NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_DONE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0                 MK_ADDR_CONST(0x1266028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_SCR                     NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_RANGE                      2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0                 MK_ADDR_CONST(0x126602c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_SCR                     NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0_NVLINK_SYS_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0                      MK_ADDR_CONST(0x1266030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_SCR                  NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_READ_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0_NVLINK_SYS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0                       MK_ADDR_CONST(0x1266034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_SCR                   NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_READ_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_RANGE                      1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_REF_WINDOW_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0_NVLINK_SYS_FMON_ENABLE_DEBUG_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0                  MK_ADDR_CONST(0x1266038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_SCR                      LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0                   MK_ADDR_CONST(0x126603c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_SCR                       LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0                        MK_ADDR_CONST(0x1266040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_SCR                    LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0                       MK_ADDR_CONST(0x1266044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_SCR                   LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_RESET_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_READ_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_WRITE_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0                    MK_ADDR_CONST(0x1266048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_SCR                        LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0                  MK_ADDR_CONST(0x126604c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_SCR                      LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_READ_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0                   MK_ADDR_CONST(0x1266050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_SCR                       LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0                    MK_ADDR_CONST(0x1266054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_SCR                        LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_RESET_MASK                         MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_READ_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_WRITE_MASK                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0                  MK_ADDR_CONST(0x1266058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_SCR                      LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_RESET_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_READ_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_WRITE_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0                      MK_ADDR_CONST(0x126605c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_SCR                  LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0                      MK_ADDR_CONST(0x1266060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_SCR                  LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0                      MK_ADDR_CONST(0x1266064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_SCR                  LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0                   MK_ADDR_CONST(0x1266068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_SCR                       LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0                    MK_ADDR_CONST(0x126606c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_SCR                        LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0_LINK_0_TXLINK_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0                  MK_ADDR_CONST(0x1266070)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_SCR                      LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0                   MK_ADDR_CONST(0x1266074)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_SCR                       LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0                        MK_ADDR_CONST(0x1266078)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_SCR                    LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_READ_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0                       MK_ADDR_CONST(0x126607c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_SCR                   LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_RESET_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_READ_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_WRITE_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0                    MK_ADDR_CONST(0x1266080)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_SCR                        LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0                  MK_ADDR_CONST(0x1266084)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_SCR                      LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_READ_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0                   MK_ADDR_CONST(0x1266088)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_SCR                       LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0                    MK_ADDR_CONST(0x126608c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_SCR                        LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_RESET_MASK                         MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_READ_MASK                  MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_WRITE_MASK                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0                  MK_ADDR_CONST(0x1266090)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_SCR                      LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_RESET_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_READ_MASK                        MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_WRITE_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0                      MK_ADDR_CONST(0x1266094)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_SCR                  LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0                      MK_ADDR_CONST(0x1266098)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_SCR                  LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_RESET_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_READ_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0                      MK_ADDR_CONST(0x126609c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_SCR                  LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0                   MK_ADDR_CONST(0x12660a0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_SCR                       LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0                    MK_ADDR_CONST(0x12660a4)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_SCR                        LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0_LINK_0_RXLINK_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0                    MK_ADDR_CONST(0x126f000)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SCR                        0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0                        MK_ADDR_CONST(0x126f004)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SCR                    0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0                     MK_ADDR_CONST(0x126f008)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SCR                         0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0                     MK_ADDR_CONST(0x126f00c)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SCR                         0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0                  MK_ADDR_CONST(0x11b0000)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_RESET_MASK                       MK_MASK_CONST(0xff0081)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_READ_MASK                        MK_MASK_CONST(0xff0081)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_WRITE_MASK                       MK_MASK_CONST(0xff0081)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_RANGE                       23:23
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L7_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_RANGE                       22:22
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L6_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_RANGE                       21:21
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L5_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_RANGE                       20:20
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L4_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_RANGE                       19:19
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L3_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_RANGE                       18:18
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L2_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_RANGE                       17:17
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L1_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_RANGE                       16:16
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_L0_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_RANGE                     7:7
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_PLL0_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0_SWR_NVHS_UPHY_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0                      MK_ADDR_CONST(0x11b0004)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_RESET_MASK                   MK_MASK_CONST(0xff0081)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_READ_MASK                    MK_MASK_CONST(0xff0081)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_WRITE_MASK                   MK_MASK_CONST(0xff0081)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_RANGE                       23:23
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L7_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_RANGE                       22:22
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L6_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_RANGE                       21:21
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L5_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_RANGE                       20:20
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L4_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_RANGE                       19:19
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L3_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_RANGE                       18:18
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L2_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_RANGE                       17:17
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L1_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_RANGE                       16:16
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_L0_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_RANGE                     7:7
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_PLL0_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0_SET_SWR_NVHS_UPHY_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0                      MK_ADDR_CONST(0x11b0008)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_RESET_MASK                   MK_MASK_CONST(0xff0081)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_READ_MASK                    MK_MASK_CONST(0xff0081)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xff0081)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_RANGE                       23:23
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L7_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_RANGE                       22:22
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L6_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_RANGE                       21:21
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L5_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_RANGE                       20:20
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L4_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_RANGE                       19:19
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L3_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_RANGE                       18:18
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L2_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_RANGE                       17:17
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L1_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_RANGE                       16:16
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_L0_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_RANGE                     7:7
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_PLL0_RST_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0_CLR_SWR_NVHS_UPHY_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0                       MK_ADDR_CONST(0x11b000c)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0_SWR_NVHS_UPHY_PM_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0                   MK_ADDR_CONST(0x11b0010)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0_SET_SWR_NVHS_UPHY_PM_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0                   MK_ADDR_CONST(0x11b0014)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0_CLR_SWR_NVHS_UPHY_PM_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0                     MK_ADDR_CONST(0x11b0018)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_RESET_VAL                   MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_RESET_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_READ_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_WRITE_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_RANGE                 8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_CE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_DEFAULT                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0_NVHS_RX_BYP_REFCLK_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0                  MK_ADDR_CONST(0x11b001c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_RESET_VAL                        MK_MASK_CONST(0x206)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_RESET_MASK                       MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_READ_MASK                        MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_WRITE_MASK                       MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_RANGE                    9:9
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_INIT_ENUM                        RESET_DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_RESET_ENABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_SWR_NVHS_PLL0_MGMT_RSTN_RESET_DISABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_RANGE                      8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_CE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0_NVHS_PLL0_MGMT_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0                        MK_ADDR_CONST(0x11b0020)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_SCR                    0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_RESET_VAL                      MK_MASK_CONST(0x6083803)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_RESET_MASK                     MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_READ_MASK                      MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_WRITE_MASK                     MK_MASK_CONST(0xf33efff7)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_RANGE                    31:28
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_SHIFT                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_RANGE                 27:26
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_LSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_INIT_ENUM                     SEQ_ON
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_SEQ_OFF                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_SEQ_ON                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_STATE_SEQ_BUSY                      MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_RANGE                   25:25
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_MSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_INIT_ENUM                       SEQ_ON
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_SEQ_OFF                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_START_STATE_SEQ_ON                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_RANGE                        24:24
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_ENABLE_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RANGE                        22:22
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_RANGE                    21:21
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_VALID_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_RANGE                     20:20
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_RANGE                   19:18
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_LOCAL_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_RANGE                    17:17
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_MASTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RANGE                 16:16
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_RANGE                       15:15
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_BYPASS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_RANGE                  14:14
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RCAL_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_RANGE                        13:13
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_RANGE                 12:11
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SLEEP_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_RANGE                     10:10
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_VALID_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_RANGE                     9:9
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_RESET_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_RANGE                   8:8
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_CAL_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_RANGE                     7:7
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_RANGE                    6:6
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_RANGE                  5:5
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_RANGE                      4:4
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_SEQ_IN_SWCTL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_RANGE                       2:2
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_USE_LOCKDET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_RANGE                      1:1
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_RANGE                       0:0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0_NVHS_UPHY_PLL0_RESET_SWCTL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0                        MK_ADDR_CONST(0x11b0024)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_SCR                    0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_RESET_VAL                      MK_MASK_CONST(0x16400)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_RANGE                  31:24
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_RANGE                        23:16
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_RANGE                   15:8
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_DEFAULT                 MK_MASK_CONST(0x64)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_PLL_PU_POST_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0_NVHS_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0                        MK_ADDR_CONST(0x11b0028)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_SCR                    0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_RESET_VAL                      MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_RESET_MASK                     MK_MASK_CONST(0x7c)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_READ_MASK                      MK_MASK_CONST(0x7c)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_WRITE_MASK                     MK_MASK_CONST(0x7c)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_RANGE                 6:6
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_RANGE                       5:5
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_SEQ_STATUS_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_RANGE                        4:4
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_FORCE_SOURCEPLL_PD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_RANGE                        3:2
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0_NVHS_UPHY_PLL0_RATE_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0                        MK_ADDR_CONST(0x11b002c)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_SCR                    0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_RESET_VAL                      MK_MASK_CONST(0x104)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_RESET_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_READ_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_RANGE                        11:8
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_PD_RECHECK_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_RANGE                  7:0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_DEFAULT                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0_NVHS_UPHY_PLL0_PLL_CAL_WAIT_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0                     MK_ADDR_CONST(0x11b0030)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_SCR                         0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_RESET_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_READ_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_WRITE_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_RANGE                       4:4
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_VALID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_RANGE                     3:0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0_NVHS_UPHY_PLL_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0                      MK_ADDR_CONST(0x11b0034)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_RESET_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_READ_MASK                    MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_RANGE                        15:15
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_RANGE                       14:14
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_RANGE                     13:12
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_RANGE                    11:11
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_RANGE                       10:10
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_RANGE                      9:9
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_RANGE                 3:3
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_RANGE                        2:2
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0_NVHS_UPHY_C5_FSM_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0                   MK_ADDR_CONST(0x11b0038)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_SCR                       0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_RANGE                  0:0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0_NVHS_UPHY_C5_TX_BYP_REFCLK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0                     MK_ADDR_CONST(0x11b003c)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_SCR                         0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_RESET_MASK                  MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_READ_MASK                   MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_WRITE_MASK                  MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_RANGE                      15:15
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_RANGE                     14:14
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_RANGE                   13:12
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_RANGE                  11:11
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_RANGE                     10:10
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_RANGE                    9:9
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0_NVHS_UPHY_NVL_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0                    MK_ADDR_CONST(0x11b0040)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_RANGE                    15:15
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_RANGE                   14:14
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_RANGE                 13:12
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_RANGE                        11:11
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_RANGE                   10:10
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_RANGE                  9:9
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0_NVHS_UPHY_SLVS_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0                        MK_ADDR_CONST(0x11c0000)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_RESET_VAL                      MK_MASK_CONST(0x6083803)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_RESET_MASK                     MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x1100004)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x1100005)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_READ_MASK                      MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_WRITE_MASK                     MK_MASK_CONST(0xf33efff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_RANGE                    31:28
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_IDDQ2_PLL_RCAL_DLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_SHIFT                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_RANGE                 27:26
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_LSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_INIT_ENUM                     SEQ_ON
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_SEQ_OFF                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_SEQ_ON                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_STATE_SEQ_BUSY                      MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_RANGE                   25:25
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_MSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_INIT_ENUM                       SEQ_ON
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_SEQ_OFF                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_START_STATE_SEQ_ON                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_RANGE                        24:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE_ENABLE                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_ENABLE__PROD                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RANGE                        22:22
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_RANGE                    21:21
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_VALID_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_RANGE                     20:20
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_SW_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SET__PROD                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_RANGE                   19:18
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_LOCAL_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_RANGE                    17:17
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_MASTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RANGE                 16:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_RANGE                       15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_BYPASS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_RANGE                  14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RCAL_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_RANGE                        13:13
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_RANGE                 12:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SLEEP_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_RANGE                     10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_VALID_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_RANGE                     9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_RESET_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_RANGE                   8:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_CAL_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_RANGE                     7:7
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_RANGE                    6:6
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_LANE_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_RANGE                  5:5
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_PLL_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_RANGE                      4:4
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_SEQ_IN_SWCTL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_RANGE                       2:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_SW_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_USE_LOCKDET__PROD                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_RANGE                      1:1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_RANGE                       0:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0_HSIO_UPHY_PLL0_RESET_SWCTL__PROD                       MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0                        MK_ADDR_CONST(0x11c0004)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_RESET_VAL                      MK_MASK_CONST(0x16400)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_RANGE                  31:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_RESET_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_RANGE                        23:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_IDDQ2_LANE_SLUMBER_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_RANGE                   15:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_DEFAULT                 MK_MASK_CONST(0x64)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_PLL_PU_POST_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_RANGE                   7:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0_HSIO_UPHY_PLL0_LANE_IDDQ2_PLL_IDDQ_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0                        MK_ADDR_CONST(0x11c0008)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_RESET_VAL                      MK_MASK_CONST(0x9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_RANGE                 6:6
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_VALUE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_RANGE                       5:5
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SEQ_STATUS_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_RANGE                        4:4
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_FORCE_SOURCEPLL_PD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_RANGE                        3:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_RATE_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_RANGE                       1:1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0_HSIO_UPHY_PLL0_SPEED_ARBITER_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0                        MK_ADDR_CONST(0x11c000c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_RESET_VAL                      MK_MASK_CONST(0x104)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_RESET_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_READ_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_RANGE                        11:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_PD_RECHECK_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_RANGE                  7:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_DEFAULT                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0_HSIO_UPHY_PLL0_PLL_CAL_WAIT_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0                        MK_ADDR_CONST(0x11c0010)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_RESET_VAL                      MK_MASK_CONST(0x6083803)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_RESET_MASK                     MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x1121004)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x1123805)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_READ_MASK                      MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_WRITE_MASK                     MK_MASK_CONST(0xf33efff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_RANGE                    31:28
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_IDDQ2_PLL_RCAL_DLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_SHIFT                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_RANGE                 27:26
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_LSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_INIT_ENUM                     SEQ_ON
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_SEQ_OFF                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_SEQ_ON                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_STATE_SEQ_BUSY                      MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_RANGE                   25:25
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_MSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_INIT_ENUM                       SEQ_ON
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_SEQ_OFF                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_START_STATE_SEQ_ON                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_RANGE                        24:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE_ENABLE                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_ENABLE__PROD                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RANGE                        22:22
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_RANGE                    21:21
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_VALID_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_RANGE                     20:20
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_SW_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SET__PROD                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_RANGE                   19:18
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_LOCAL_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_RANGE                    17:17
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_SW_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_MASTER__PROD                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RANGE                 16:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_RANGE                       15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_BYPASS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_RANGE                  14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RCAL_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_RANGE                        13:13
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_IDDQ__PROD                        MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_RANGE                 12:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_SW_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SLEEP_VAL__PROD                 MK_MASK_CONST(0x2)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_RANGE                     10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_VALID_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_RANGE                     9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_RESET_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_RANGE                   8:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_CAL_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_RANGE                     7:7
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_RANGE                    6:6
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_LANE_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_RANGE                  5:5
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_PLL_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_RANGE                      4:4
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_SEQ_IN_SWCTL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_RANGE                       2:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_SW_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_USE_LOCKDET__PROD                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_RANGE                      1:1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_RANGE                       0:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0_HSIO_UPHY_PLL1_RESET_SWCTL__PROD                       MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0                        MK_ADDR_CONST(0x11c0014)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_RESET_VAL                      MK_MASK_CONST(0x16400)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_RANGE                  31:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_RESET_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_RANGE                        23:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_IDDQ2_LANE_SLUMBER_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_RANGE                   15:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_DEFAULT                 MK_MASK_CONST(0x64)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_PLL_PU_POST_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_RANGE                   7:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0_HSIO_UPHY_PLL1_LANE_IDDQ2_PLL_IDDQ_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0                        MK_ADDR_CONST(0x11c0018)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_RESET_VAL                      MK_MASK_CONST(0x9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_RANGE                 6:6
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_VALUE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_RANGE                       5:5
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SEQ_STATUS_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_RANGE                        4:4
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_FORCE_SOURCEPLL_PD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_RANGE                        3:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_RATE_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_RANGE                       1:1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0_HSIO_UPHY_PLL1_SPEED_ARBITER_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0                        MK_ADDR_CONST(0x11c001c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_RESET_VAL                      MK_MASK_CONST(0x104)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_RESET_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_READ_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_RANGE                        11:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_PD_RECHECK_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_RANGE                  7:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_DEFAULT                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0_HSIO_UPHY_PLL1_PLL_CAL_WAIT_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0                        MK_ADDR_CONST(0x11c0020)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_RESET_VAL                      MK_MASK_CONST(0x6083803)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_RESET_MASK                     MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x1100004)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x1100005)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_READ_MASK                      MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_WRITE_MASK                     MK_MASK_CONST(0xf33efff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_RANGE                    31:28
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_IDDQ2_PLL_RCAL_DLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_SHIFT                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_RANGE                 27:26
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_LSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_INIT_ENUM                     SEQ_ON
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_SEQ_OFF                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_SEQ_ON                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_STATE_SEQ_BUSY                      MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_RANGE                   25:25
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_MSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_INIT_ENUM                       SEQ_ON
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_SEQ_OFF                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_START_STATE_SEQ_ON                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_RANGE                        24:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE_ENABLE                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_ENABLE__PROD                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RANGE                        22:22
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_RANGE                    21:21
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_VALID_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_RANGE                     20:20
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_SW_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SET__PROD                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_RANGE                   19:18
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_LOCAL_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_RANGE                    17:17
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_MASTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RANGE                 16:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_RANGE                       15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_BYPASS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_RANGE                  14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RCAL_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_RANGE                        13:13
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_RANGE                 12:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SLEEP_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_RANGE                     10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_VALID_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_RANGE                     9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_RESET_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_RANGE                   8:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_CAL_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_RANGE                     7:7
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_RANGE                    6:6
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_LANE_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_RANGE                  5:5
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_PLL_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_RANGE                      4:4
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_SEQ_IN_SWCTL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_RANGE                       2:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_SW_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_USE_LOCKDET__PROD                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_RANGE                      1:1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_RANGE                       0:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0_HSIO_UPHY_PLL2_RESET_SWCTL__PROD                       MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0                        MK_ADDR_CONST(0x11c0024)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_RESET_VAL                      MK_MASK_CONST(0x16400)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_RANGE                  31:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_RESET_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_RANGE                        23:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_IDDQ2_LANE_SLUMBER_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_RANGE                   15:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_DEFAULT                 MK_MASK_CONST(0x64)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_PLL_PU_POST_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_RANGE                   7:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0_HSIO_UPHY_PLL2_LANE_IDDQ2_PLL_IDDQ_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0                        MK_ADDR_CONST(0x11c0028)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_RESET_VAL                      MK_MASK_CONST(0x9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_RANGE                 6:6
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_VALUE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_RANGE                       5:5
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SEQ_STATUS_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_RANGE                        4:4
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_FORCE_SOURCEPLL_PD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_RANGE                        3:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_RATE_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_RANGE                       1:1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0_HSIO_UPHY_PLL2_SPEED_ARBITER_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0                        MK_ADDR_CONST(0x11c002c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_RESET_VAL                      MK_MASK_CONST(0x104)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_RESET_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_READ_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_RANGE                        11:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_PD_RECHECK_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_RANGE                  7:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_DEFAULT                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0_HSIO_UPHY_PLL2_PLL_CAL_WAIT_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0                        MK_ADDR_CONST(0x11c0030)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_RESET_VAL                      MK_MASK_CONST(0x6083803)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_RESET_MASK                     MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x1121004)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x1123805)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_READ_MASK                      MK_MASK_CONST(0xff7ffff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_WRITE_MASK                     MK_MASK_CONST(0xf33efff7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_RANGE                    31:28
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_IDDQ2_PLL_RCAL_DLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_SHIFT                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_RANGE                 27:26
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_LSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_INIT_ENUM                     SEQ_ON
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_SEQ_OFF                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_SEQ_ON                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_STATE_SEQ_BUSY                      MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_SHIFT                   MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_RANGE                   25:25
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_MSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_LSB                     MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_INIT_ENUM                       SEQ_ON
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_SEQ_OFF                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_START_STATE_SEQ_ON                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_RANGE                        24:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_MSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE_ENABLE                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_ENABLE__PROD                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RANGE                        22:22
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_RANGE                    21:21
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_VALID_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_RANGE                     20:20
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_SW_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SET__PROD                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_SHIFT                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_RANGE                   19:18
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_MSB                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_LSB                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_LOCAL_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_RANGE                    17:17
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_SW_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_MASTER__PROD                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RANGE                 16:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_RANGE                       15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_BYPASS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_RANGE                  14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RCAL_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_RANGE                        13:13
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_IDDQ__PROD                        MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_RANGE                 12:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_SW_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SLEEP_VAL__PROD                 MK_MASK_CONST(0x2)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_RANGE                     10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_VALID_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_RANGE                     9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_RESET_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_RANGE                   8:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_CAL_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_RANGE                     7:7
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_RANGE                    6:6
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_LANE_PD_OVERRIDE_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_RANGE                  5:5
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_PLL_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_RANGE                      4:4
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_SEQ_IN_SWCTL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_RANGE                       2:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_SW_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_USE_LOCKDET__PROD                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_RANGE                      1:1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_OVERRIDE_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_RANGE                       0:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0_HSIO_UPHY_PLL3_RESET_SWCTL__PROD                       MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0                        MK_ADDR_CONST(0x11c0034)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_RESET_VAL                      MK_MASK_CONST(0x16400)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_RANGE                  31:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_RESET_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_RANGE                        23:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_IDDQ2_LANE_SLUMBER_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_RANGE                   15:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_DEFAULT                 MK_MASK_CONST(0x64)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_PLL_PU_POST_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_RANGE                   7:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0_HSIO_UPHY_PLL3_LANE_IDDQ2_PLL_IDDQ_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0                        MK_ADDR_CONST(0x11c0038)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_RESET_VAL                      MK_MASK_CONST(0x9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_RANGE                 6:6
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_VALUE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_RANGE                       5:5
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SEQ_STATUS_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_RANGE                        4:4
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_FORCE_SOURCEPLL_PD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_RANGE                        3:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_RATE_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_RANGE                       1:1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0_HSIO_UPHY_PLL3_SPEED_ARBITER_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0                        MK_ADDR_CONST(0x11c003c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_SCR                    0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_RESET_VAL                      MK_MASK_CONST(0x104)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_RESET_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_READ_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_RANGE                        11:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_PD_RECHECK_DLY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_RANGE                  7:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_DEFAULT                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0_HSIO_UPHY_PLL3_PLL_CAL_WAIT_DLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0                     MK_ADDR_CONST(0x11c0040)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_SCR                         0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_RESET_MASK                  MK_MASK_CONST(0xf0f0f0f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_READ_MASK                   MK_MASK_CONST(0xf0f0f0f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_WRITE_MASK                  MK_MASK_CONST(0xf0f0f0f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_RANGE                  27:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L3_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_RANGE                  19:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L2_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L1_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_RANGE                  3:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0_HSIO_UPHY_L0_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0                     MK_ADDR_CONST(0x11c0044)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_SCR                         0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_RESET_MASK                  MK_MASK_CONST(0xf0f0f0f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_READ_MASK                   MK_MASK_CONST(0xf0f0f0f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_WRITE_MASK                  MK_MASK_CONST(0xf0f0f0f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_RANGE                  27:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L7_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_RANGE                  19:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L6_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L5_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_RANGE                  3:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0_HSIO_UPHY_L4_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0                     MK_ADDR_CONST(0x11c0048)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_SCR                         0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_RESET_MASK                  MK_MASK_CONST(0xf0f0f0f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_READ_MASK                   MK_MASK_CONST(0xf0f0f0f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_WRITE_MASK                  MK_MASK_CONST(0xf0f0f0f)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_RANGE                 27:24
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L11_PLL_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_RANGE                 19:16
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L10_PLL_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L9_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_RANGE                  3:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0_HSIO_UPHY_L8_PLL_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0                     MK_ADDR_CONST(0x11c004c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_SCR                         0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_RANGE                       0:0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0_HSIO_UPHY_PLL_SEL_VALID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0                      MK_ADDR_CONST(0x11c0050)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_RESET_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_READ_MASK                    MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_RANGE                        15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_RANGE                       14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_RANGE                     13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_RANGE                    11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_RANGE                       10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_RANGE                      9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_RANGE                 3:3
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_RANGE                        2:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0_HSIO_UPHY_C0_FSM_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0                      MK_ADDR_CONST(0x11c0054)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_RESET_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_READ_MASK                    MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_RANGE                        15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_RANGE                       14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_RANGE                     13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_RANGE                    11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_RANGE                       10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_RANGE                      9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_RANGE                 3:3
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_RANGE                        2:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0_HSIO_UPHY_C1_FSM_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0                      MK_ADDR_CONST(0x11c0058)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_RESET_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_READ_MASK                    MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_RANGE                        15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_RANGE                       14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_RANGE                     13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_RANGE                    11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_RANGE                       10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_RANGE                      9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_RANGE                 3:3
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_RANGE                        2:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0_HSIO_UPHY_C2_FSM_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0                      MK_ADDR_CONST(0x11c005c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_RESET_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_READ_MASK                    MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_RANGE                        15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_RANGE                       14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_RANGE                     13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_RANGE                    11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_RANGE                       10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_RANGE                      9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_RANGE                 3:3
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_RANGE                        2:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0_HSIO_UPHY_C3_FSM_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0                      MK_ADDR_CONST(0x11c0060)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_RESET_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_READ_MASK                    MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0xfe0c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_RANGE                        15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_RANGE                       14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_RANGE                     13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_RANGE                    11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_RANGE                       10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_RANGE                      9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_RANGE                 3:3
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_RANGE                        2:2
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0_HSIO_UPHY_C4_FSM_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0                    MK_ADDR_CONST(0x11c0064)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_RANGE                    15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_RANGE                   14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_RANGE                 13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_RANGE                        11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_RANGE                   10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_RANGE                  9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0_HSIO_UPHY_SSP0_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0                    MK_ADDR_CONST(0x11c0068)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_RANGE                    15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_RANGE                   14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_RANGE                 13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_RANGE                        11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_RANGE                   10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_RANGE                  9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0_HSIO_UPHY_SSP1_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0                    MK_ADDR_CONST(0x11c006c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_RANGE                    15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_RANGE                   14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_RANGE                 13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_RANGE                        11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_RANGE                   10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_RANGE                  9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0_HSIO_UPHY_SSP2_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0                    MK_ADDR_CONST(0x11c0070)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_RANGE                    15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_RANGE                   14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_RANGE                 13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_RANGE                        11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_RANGE                   10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_RANGE                  9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0_HSIO_UPHY_SSP3_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0                    MK_ADDR_CONST(0x11c0074)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0xfe00)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_RANGE                    15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_RANGE                   14:14
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_ENABLE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_RANGE                 13:12
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_RANGE                        11:11
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_RANGE                   10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_RANGE                  9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0_HSIO_UPHY_SATA_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0                    MK_ADDR_CONST(0x11c0078)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0x8600)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0x8600)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0x8600)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_RANGE                    15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_RANGE                   10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_RANGE                  9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0_HSIO_UPHY_IST0_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0                    MK_ADDR_CONST(0x11c007c)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_RESET_MASK                         MK_MASK_CONST(0x8600)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_READ_MASK                  MK_MASK_CONST(0x8600)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0x8600)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_RANGE                    15:15
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_RANGE                   10:10
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_RANGE                  9:9
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0_HSIO_UPHY_IST1_CLK_SRC_SEL_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0                  MK_ADDR_CONST(0x11d0000)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SCR                      PEX0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_RESET_VAL                        MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_RESET_MASK                       MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_READ_MASK                        MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_WRITE_MASK                       MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_RANGE                    10:10
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_COMMON_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_RANGE                    9:9
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_RANGE                    8:8
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_RANGE                    7:7
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_RANGE                    6:6
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_RANGE                    5:5
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_RANGE                        4:4
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_4_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_3_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_RANGE                        2:2
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_2_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_1_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0_SWR_PEX0_CORE_0_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0                      MK_ADDR_CONST(0x11d0004)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SCR                  PEX0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_RESET_VAL                    MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_RESET_MASK                   MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_READ_MASK                    MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_WRITE_MASK                   MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_RANGE                    10:10
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_COMMON_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_RANGE                    9:9
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_RANGE                    8:8
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_RANGE                    7:7
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_RANGE                    6:6
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_RANGE                    5:5
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_RANGE                        4:4
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_4_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_3_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_RANGE                        2:2
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_2_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_1_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0_SET_SWR_PEX0_CORE_0_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0                      MK_ADDR_CONST(0x11d0008)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_SCR                  PEX0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_RESET_VAL                    MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_RESET_MASK                   MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_READ_MASK                    MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x7ff)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_RANGE                    10:10
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_COMMON_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_RANGE                    9:9
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_RANGE                    8:8
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_RANGE                    7:7
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_RANGE                    6:6
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_RANGE                    5:5
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_RANGE                        4:4
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_4_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_3_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_RANGE                        2:2
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_2_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_1_RST_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0_CLR_SWR_PEX0_CORE_0_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0                      MK_ADDR_CONST(0x11d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_SCR                  PEX0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_RESET_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_READ_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_WRITE_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_RANGE                    4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_4_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_RANGE                    3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_3_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_2_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_1_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0_CLK_ENB_PEX0_CORE_0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0                  MK_ADDR_CONST(0x11d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SCR                      PEX0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_READ_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_RANGE                    4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_4_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_RANGE                    3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_3_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_2_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_1_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0_SET_CLK_ENB_PEX0_CORE_0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0                  MK_ADDR_CONST(0x11d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_SCR                      PEX0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_READ_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_RANGE                    4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_4_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_RANGE                    3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_3_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_2_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_1_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0_CLR_CLK_ENB_PEX0_CORE_0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0                  MK_ADDR_CONST(0x11d2000)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_SCR                      PEX0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_RESET_MASK                       MK_MASK_CONST(0x3ffffff)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_READ_MASK                        MK_MASK_CONST(0x3ffffff)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0x3ffffff)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_SHIFT                       MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_RANGE                       25:25
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_MSB                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_LSB                 MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_P2U_CLK_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_RANGE                      24:24
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_MSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L11_CLK_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_RANGE                       23:23
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_P2U_CLK_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_RANGE                      22:22
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L10_CLK_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_RANGE                        21:21
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_RANGE                       20:20
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L9_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_RANGE                        19:19
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_RANGE                       18:18
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L8_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_RANGE                        17:16
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_RANGE                       15:15
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L7_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_RANGE                        14:13
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_RANGE                       12:12
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L6_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_RANGE                        11:11
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_RANGE                       10:10
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L5_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_RANGE                        9:9
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_RANGE                       8:8
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L4_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_RANGE                        7:7
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_RANGE                       6:6
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L3_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_RANGE                        5:5
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_RANGE                       4:4
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L2_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_RANGE                        3:3
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_RANGE                       2:2
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L1_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_RANGE                        1:1
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0_PEX0_L0_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0                    MK_ADDR_CONST(0x11d3000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0                     MK_ADDR_CONST(0x11d3004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0                  MK_ADDR_CONST(0x11d3008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_SCR                      PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0                 MK_ADDR_CONST(0x11d300c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_SCR                     PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0                      MK_ADDR_CONST(0x11d3010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0                    MK_ADDR_CONST(0x11d3014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0                     MK_ADDR_CONST(0x11d3018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0                      MK_ADDR_CONST(0x11d301c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0_PEX0_CORE_0_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0                    MK_ADDR_CONST(0x11d3020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0                        MK_ADDR_CONST(0x11d3024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0                        MK_ADDR_CONST(0x11d3028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0                        MK_ADDR_CONST(0x11d302c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0_PEX0_CORE_0_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0                     MK_ADDR_CONST(0x11d3030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0_PEX0_CORE_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0                      MK_ADDR_CONST(0x11d3034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0_PEX0_CORE_0_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0                    MK_ADDR_CONST(0x11d3038)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0                     MK_ADDR_CONST(0x11d303c)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0                  MK_ADDR_CONST(0x11d3040)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_SCR                      PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0                 MK_ADDR_CONST(0x11d3044)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_SCR                     PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0                      MK_ADDR_CONST(0x11d3048)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0                    MK_ADDR_CONST(0x11d304c)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0                     MK_ADDR_CONST(0x11d3050)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0                      MK_ADDR_CONST(0x11d3054)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0_PEX0_CORE_1_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0                    MK_ADDR_CONST(0x11d3058)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0                        MK_ADDR_CONST(0x11d305c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0                        MK_ADDR_CONST(0x11d3060)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0                        MK_ADDR_CONST(0x11d3064)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0_PEX0_CORE_1_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0                     MK_ADDR_CONST(0x11d3068)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0_PEX0_CORE_1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0                      MK_ADDR_CONST(0x11d306c)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0_PEX0_CORE_1_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0                    MK_ADDR_CONST(0x11d3070)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0                     MK_ADDR_CONST(0x11d3074)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0                  MK_ADDR_CONST(0x11d3078)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_SCR                      PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0                 MK_ADDR_CONST(0x11d307c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_SCR                     PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0                      MK_ADDR_CONST(0x11d3080)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0                    MK_ADDR_CONST(0x11d3084)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0                     MK_ADDR_CONST(0x11d3088)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0                      MK_ADDR_CONST(0x11d308c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0_PEX0_CORE_2_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0                    MK_ADDR_CONST(0x11d3090)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0                        MK_ADDR_CONST(0x11d3094)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0                        MK_ADDR_CONST(0x11d3098)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0                        MK_ADDR_CONST(0x11d309c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0_PEX0_CORE_2_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0                     MK_ADDR_CONST(0x11d30a0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0_PEX0_CORE_2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0                      MK_ADDR_CONST(0x11d30a4)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0_PEX0_CORE_2_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0                    MK_ADDR_CONST(0x11d30a8)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0                     MK_ADDR_CONST(0x11d30ac)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0                  MK_ADDR_CONST(0x11d30b0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_SCR                      PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0                 MK_ADDR_CONST(0x11d30b4)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_SCR                     PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0                      MK_ADDR_CONST(0x11d30b8)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0                    MK_ADDR_CONST(0x11d30bc)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0                     MK_ADDR_CONST(0x11d30c0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0                      MK_ADDR_CONST(0x11d30c4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0_PEX0_CORE_3_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0                    MK_ADDR_CONST(0x11d30c8)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0                        MK_ADDR_CONST(0x11d30cc)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0                        MK_ADDR_CONST(0x11d30d0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0                        MK_ADDR_CONST(0x11d30d4)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0_PEX0_CORE_3_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0                     MK_ADDR_CONST(0x11d30d8)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0_PEX0_CORE_3_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0                      MK_ADDR_CONST(0x11d30dc)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0_PEX0_CORE_3_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0                    MK_ADDR_CONST(0x11d30e0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0                     MK_ADDR_CONST(0x11d30e4)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0                  MK_ADDR_CONST(0x11d30e8)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_SCR                      PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0                 MK_ADDR_CONST(0x11d30ec)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_SCR                     PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0                      MK_ADDR_CONST(0x11d30f0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0                    MK_ADDR_CONST(0x11d30f4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0                     MK_ADDR_CONST(0x11d30f8)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0                      MK_ADDR_CONST(0x11d30fc)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0_PEX0_CORE_4_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0                    MK_ADDR_CONST(0x11d3100)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_SCR                        PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0                        MK_ADDR_CONST(0x11d3104)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0                        MK_ADDR_CONST(0x11d3108)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0                        MK_ADDR_CONST(0x11d310c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_SCR                    PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0_PEX0_CORE_4_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0                     MK_ADDR_CONST(0x11d3110)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_SCR                         PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0_PEX0_CORE_4_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0                      MK_ADDR_CONST(0x11d3114)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_SCR                  PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0_PEX0_CORE_4_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0                      MK_ADDR_CONST(0x11df000)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0                      MK_ADDR_CONST(0x11df004)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX0_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0                  MK_ADDR_CONST(0x11e0000)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SCR                      PEX1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_RESET_VAL                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0_SWR_PEX1_CORE_5_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0                      MK_ADDR_CONST(0x11e0004)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SCR                  PEX1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_RESET_VAL                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0_SET_SWR_PEX1_CORE_5_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0                      MK_ADDR_CONST(0x11e0008)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_SCR                  PEX1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_RESET_VAL                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_APB_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0_CLR_SWR_PEX1_CORE_5_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0                      MK_ADDR_CONST(0x11e1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_SCR                  PEX1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0_CLK_ENB_PEX1_CORE_5_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0                  MK_ADDR_CONST(0x11e1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SCR                      PEX1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0_SET_CLK_ENB_PEX1_CORE_5_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0                  MK_ADDR_CONST(0x11e1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_SCR                      PEX1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0_CLR_CLK_ENB_PEX1_CORE_5_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0                  MK_ADDR_CONST(0x11e2000)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_SCR                      PEX1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_RANGE                        15:15
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_RANGE                       14:14
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L7_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_RANGE                        13:13
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_RANGE                       12:12
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L6_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_RANGE                        11:11
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_RANGE                       10:10
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L5_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_RANGE                        9:9
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_RANGE                       8:8
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L4_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_RANGE                        7:7
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_RANGE                       6:6
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L3_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_RANGE                        5:5
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_RANGE                       4:4
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L2_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_RANGE                        3:3
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_RANGE                       2:2
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L1_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_RANGE                        1:1
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_P2U_CLK_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0_PEX1_L0_CLK_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0                    MK_ADDR_CONST(0x11e3000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_SCR                        PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0                     MK_ADDR_CONST(0x11e3004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_SCR                         PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0                  MK_ADDR_CONST(0x11e3008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_SCR                      PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_RESET_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_READ_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_WRITE_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0                 MK_ADDR_CONST(0x11e300c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_SCR                     PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                        MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                        23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0                      MK_ADDR_CONST(0x11e3010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_SCR                  PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_WRITE_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_FAULT_REPORT_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ACTION_RESET_REQ_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0                    MK_ADDR_CONST(0x11e3014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_SCR                        PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_WRITE_MASK                         MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_RANGE                        6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_DC_FAULT_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                     5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REPORT_OVERFLOW_ERROR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_CLK_WINDOW_EN_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_COUNTER_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0                     MK_ADDR_CONST(0x11e3018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_SCR                         PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                   0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0                      MK_ADDR_CONST(0x11e301c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_SCR                  PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_RESET_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_READ_MASK                    MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_WRITE_MASK                   MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_CLEAR_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_RANGE                      4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_FAULT_OUT_STATUS_TRUE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_RANGE                        3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_OVERFLOW_ERROR_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                        2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_INIT_ENUM                  FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_FALSE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0_PEX1_CORE_5_FMON_DC_FAULT_TRUE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0                    MK_ADDR_CONST(0x11e3020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_SCR                        PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_RESET_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_READ_MASK                  MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_WRITE_MASK                         MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_RANGE                   31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_RANGE                       2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0                        MK_ADDR_CONST(0x11e3024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_SCR                    PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_READ_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_DONE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0                        MK_ADDR_CONST(0x11e3028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_SCR                    PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_RANGE                    2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0                        MK_ADDR_CONST(0x11e302c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_SCR                    PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_RANGE                   31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0_PEX1_CORE_5_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0                     MK_ADDR_CONST(0x11e3030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_SCR                         PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0_PEX1_CORE_5_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0                      MK_ADDR_CONST(0x11e3034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_SCR                  PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_RANGE                    1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_REF_WINDOW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0_PEX1_CORE_5_FMON_ENABLE_DEBUG_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0                      MK_ADDR_CONST(0x11ef000)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SCR                  0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0                      MK_ADDR_CONST(0x11ef004)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SCR                  0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PEX1_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0                    MK_ADDR_CONST(0x11f0000)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_RESET_VAL                  MK_MASK_CONST(0x20010025)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_RESET_MASK                         MK_MASK_CONST(0xfffffdff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_READ_MASK                  MK_MASK_CONST(0xfffffdff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_WRITE_MASK                         MK_MASK_CONST(0xfffffdff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_SHIFT                 MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_RANGE                 31:30
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_LSB                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTREGOFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_FIELD                  MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_RANGE                  29:24
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_DEFAULT                        MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINCINTRV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_RANGE                       23:16
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_RANGE                    15:15
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCINVERT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_RANGE                    14:14
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCCENTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_RANGE                    13:13
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCPDMBYP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_RANGE                       12:12
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCBYP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_RANGE                 11:11
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_INTERP_RESET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_RANGE                    10:10
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_BYPASS_SS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_FIELD                       MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_RANGE                       8:0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_DEFAULT                     MK_MASK_CONST(0x25)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_DEFAULT_MASK                        MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0_PLLNVHS_SSCMAX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVHS_MISC1_0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0                      MK_ADDR_CONST(0x11f0004)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_RESET_VAL                    MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_RESET_MASK                   MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_READ_MASK                    MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_WRITE_MASK                   MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_RANGE                       31:31
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_INIT_ENUM                   PLLNVHS_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_PLLNVHS_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_PTO_ROOT_CLK_SEL_PLLNVHS_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_RANGE                   7:5
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_TEST_OUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_RANGE                      4:4
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_SDM_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_RANGE                     3:3
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_RANGE                      2:2
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_DITHER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SSC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC1_0_PLLNVHS_EN_SDM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVHS_BASE_0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0                       MK_ADDR_CONST(0x11f0008)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_RESET_VAL                     MK_MASK_CONST(0x7d02)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_RESET_MASK                    MK_MASK_CONST(0xefffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_READ_MASK                     MK_MASK_CONST(0xefffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_WRITE_MASK                    MK_MASK_CONST(0xefffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_ENABLE_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_SHIFT                   MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_MSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_LSB                     MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_LOCK_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_RANGE                  29:29
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_FDIV4B_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_FIELD                 MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_RANGE                 27:16
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_DEFAULT_MASK                  MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_EXT_SETUP_27_16_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_DEFAULT                  MK_MASK_CONST(0x7d)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_NDIV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_RANGE                    7:0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_DEFAULT                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE_0_PLLNVHS_MDIV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVHS_BASE1_0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0                      MK_ADDR_CONST(0x11f000c)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_RESET_VAL                    MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_RESET_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_READ_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_WRITE_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_FIELD                      MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_RANGE                      5:0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_DEFAULT                    MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_DEFAULT_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_BASE1_0_PLLNVHS_PLDIV_CML_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVHS_MISC_0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0                       MK_ADDR_CONST(0x11f0010)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_RESET_VAL                     MK_MASK_CONST(0x6200)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_WRITE_MASK                    MK_MASK_CONST(0xffffe7ff)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_RANGE                   31:16
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_SETUP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_RANGE                  15:15
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BYPASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_RANGE                      14:14
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_OFF                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_SWCTL_ON                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_RANGE                     13:13
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_OFF                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_IDDQ_OVERRIDE_VALUE_ON                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_RANGE                        12:12
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_FREQLOCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_RANGE                    11:11
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_RANGE                 10:10
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_INIT_ENUM                     REF_ENABLE
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_REF_ENABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_REF_DIS_REF_DISABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_RANGE                     9:9
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_LOCK_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_RANGE                     8:8
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_PTS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_RANGE                     7:6
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KCP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_RANGE                    5:4
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG14V_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_RANGE                    3:2
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_VREG10V_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_BG_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_RANGE                    0:0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_MISC_0_PLLNVHS_KVCO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0                   MK_ADDR_CONST(0x11f0014)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_DIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_RANGE                        15:0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0_PLLNVHS_SDM_SSC_STEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0                   MK_ADDR_CONST(0x11f0018)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_RANGE                 31:16
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MAX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0_PLLNVHS_SDM_SSC_MIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVHS_AUX_0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0                        MK_ADDR_CONST(0x11f001c)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_RESET_VAL                      MK_MASK_CONST(0x6002070)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_RESET_MASK                     MK_MASK_CONST(0x8fffff78)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_READ_MASK                      MK_MASK_CONST(0x8fffff78)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_WRITE_MASK                     MK_MASK_CONST(0x83ffff78)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_SHIFT                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_RANGE                   31:31
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_LSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_INIT_ENUM                       SKIP
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_SKIP                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SEQ_INCLUDE_INCLUDE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_SHIFT                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_RANGE                        27:26
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_LSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_INIT_ENUM                    SEQ_ON
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_SEQ_OFF                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_SEQ_ON                       MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_STATE_SEQ_BUSY                     MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_RANGE                  25:25
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_INIT_ENUM                      SEQ_ON
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_SEQ_OFF                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_START_STATE_SEQ_ON                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SEQ_ENABLE_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_RANGE                   23:16
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_MSB                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_DLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_RANGE                 15:8
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_DEFAULT                       MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_LOCK_DLY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_RANGE                 6:6
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_SS_SWCTL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_RANGE                     5:5
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_CONFIG_SWCTL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_RANGE                     4:4
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_ENABLE_SWCTL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_RANGE                      3:3
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX_0_PLLNVHS_USE_LOCKDET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLNVHS_AUX1_0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0                       MK_ADDR_CONST(0x11f0020)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_RESET_VAL                     MK_MASK_CONST(0x105)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_INTRESET_DLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_DEFAULT                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVHS_AUX1_0_PLLNVHS_ENABLE_DLY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0                        MK_ADDR_CONST(0x790000)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_RESET_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_READ_MASK                      MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_WRITE_MASK                     MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_ENB_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVIDEND_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_6_DIV_DIVISOR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVENC1_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0                     MK_ADDR_CONST(0x1270000)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SCR                         NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_0_SWR_NVENC1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0                 MK_ADDR_CONST(0x1270004)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SCR                     NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0_SET_SWR_NVENC1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0                 MK_ADDR_CONST(0x1270008)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_SCR                     NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0_CLR_SWR_NVENC1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0                 MK_ADDR_CONST(0x1271000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_SCR                     NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0_CLK_ENB_NVENC1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0                     MK_ADDR_CONST(0x1271004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SCR                         NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0_SET_CLK_ENB_NVENC1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0                     MK_ADDR_CONST(0x1271008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_SCR                         NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0_CLR_CLK_ENB_NVENC1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0                 MK_ADDR_CONST(0x1272000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_SCR                     NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0_BOND_OUT_NVENC1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0                  MK_ADDR_CONST(0x1273000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_SCR                      NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_PLLC2_OUT0                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_PLLC3_OUT0                        MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_DFLL_NVENC1                       MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0_NVENC1_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0                   MK_ADDR_CONST(0x1273004)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SCR                       NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_RESET_VAL                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_RESET_MASK                        MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_READ_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_WRITE_MASK                        MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_ENB_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_RANGE                   15:8
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVIDEND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0_SUPER_NVENC1_DIV_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0                   MK_ADDR_CONST(0x1274000)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_SCR                       NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0_CLK_SPARE_REG_NVENC1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0                 MK_ADDR_CONST(0x1278000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_SCR                     NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0_NVENC1_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0                  MK_ADDR_CONST(0x1278004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_SCR                      NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0_NVENC1_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0                       MK_ADDR_CONST(0x1278008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_SCR                   NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_RESET_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_READ_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_WRITE_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0                      MK_ADDR_CONST(0x127800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_SCR                  NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_RESET_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_READ_MASK                    MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_WRITE_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                  MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                  23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0_NVENC1_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0                   MK_ADDR_CONST(0x1278010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_SCR                       NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_FAULT_REPORT_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0_NVENC1_FMON_ACTION_RESET_REQ_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0                 MK_ADDR_CONST(0x1278014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_SCR                     NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_RESET_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_READ_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_WRITE_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_RANGE                  6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_DC_FAULT_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                       5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_RANGE                 3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REPORT_OVERFLOW_ERROR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_REF_CLK_WINDOW_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FMON_COUNTER_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0                  MK_ADDR_CONST(0x1278018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_SCR                      NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_RANGE                 2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                     FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_FALSE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_CLK_STATUS_TRUE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                     0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0_NVENC1_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0                   MK_ADDR_CONST(0x127801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_SCR                       NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_RESET_MASK                        MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_READ_MASK                         MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_WRITE_MASK                        MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_CLEAR_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_RANGE                        4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_FAULT_OUT_STATUS_TRUE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_RANGE                  3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_OVERFLOW_ERROR_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                  2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                   1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_INIT_ENUM                    FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_FALSE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0_NVENC1_FMON_DC_FAULT_TRUE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0                 MK_ADDR_CONST(0x1278020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_SCR                     NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_RESET_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_READ_MASK                       MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_WRITE_MASK                      MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_RANGE                     31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_RANGE                 2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_ENABLE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0                     MK_ADDR_CONST(0x1278024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_SCR                         NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0_NVENC1_FMON_LOAD_DATA_DONE_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0                     MK_ADDR_CONST(0x1278028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_SCR                         NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_RANGE                      2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0_NVENC1_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0                     MK_ADDR_CONST(0x127802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_SCR                         NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_FIELD                     MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_RANGE                     31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0_NVENC1_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0                  MK_ADDR_CONST(0x1278030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_SCR                      NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_READ_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_WRITE_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_RANGE                     3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_RANGE                     2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0_NVENC1_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0                   MK_ADDR_CONST(0x1278034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_SCR                       NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_RANGE                      1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_REF_WINDOW_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_RANGE                    0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0_NVENC1_FMON_ENABLE_DEBUG_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0                    MK_ADDR_CONST(0x127f000)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SCR                        0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0                    MK_ADDR_CONST(0x127f004)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SCR                        0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_MSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_LSB                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_MSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_LSB                    MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_MSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_LSB                    MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_MSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_LSB                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_MSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_LSB                    MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_MSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_LSB                    MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_MSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_LSB                    MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_MSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_MSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_LSB                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_MSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_LSB                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_MSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_LSB                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_MSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_LSB                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_MSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_LSB                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_MSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_LSB                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_LSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_TPIU_0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0                       MK_ADDR_CONST(0x11a0000)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_0_SWR_TPIU_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0                   MK_ADDR_CONST(0x11a0004)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0_SET_SWR_TPIU_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0                   MK_ADDR_CONST(0x11a0008)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_RESET_VAL                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0_CLR_SWR_TPIU_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0                   MK_ADDR_CONST(0x11a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0_CLK_ENB_TPIU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0                       MK_ADDR_CONST(0x11a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0_SET_CLK_ENB_TPIU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0                       MK_ADDR_CONST(0x11a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0_CLR_CLK_ENB_TPIU_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0                   MK_ADDR_CONST(0x11a100c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0_BOND_OUT_TPIU_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0                    MK_ADDR_CONST(0x11a2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_RESET_VAL                  MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_RESET_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_READ_MASK                  MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_WRITE_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_PLLC2_OUT0                    MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_PLLC3_OUT0                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_PLLREFE_VCOCLK                        MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_CLK_S                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_SRC_CLK_M                 MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0_TPIU_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0                       MK_ADDR_CONST(0x1290000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0_CLK_ENB_TPIU_PAD_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0                   MK_ADDR_CONST(0x1290004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0_SET_CLK_ENB_TPIU_PAD_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0                   MK_ADDR_CONST(0x1290008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_READ_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0_CLR_CLK_ENB_TPIU_PAD_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0                       MK_ADDR_CONST(0x129000c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_SCR                   0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_READ_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0_BOND_OUT_TPIU_PAD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0                      MK_ADDR_CONST(0x1290010)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_SCR                  0
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_RESET_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_READ_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_FIELD                   MK_FIELD_CONST(0x7f, CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_RANGE                   6:0
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0_TPIU_PAD_TRIMMER_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CTRL_TPIU_0
#define CLK_RST_CONTROLLER_CTRL_TPIU_0                  MK_ADDR_CONST(0x1290014)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_SCR                      0
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_RANGE                       0:0
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CTRL_TPIU_0_TPIU_CLK_SRC_INV_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTH_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0                      MK_ADDR_CONST(0x1280000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0_SWR_UARTH_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0                  MK_ADDR_CONST(0x1280004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0_SET_SWR_UARTH_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0                  MK_ADDR_CONST(0x1280008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0_CLR_SWR_UARTH_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0                  MK_ADDR_CONST(0x1281000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0_CLK_ENB_UARTH_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0                      MK_ADDR_CONST(0x1281004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0_SET_CLK_ENB_UARTH_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0                      MK_ADDR_CONST(0x1281008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0_CLR_CLK_ENB_UARTH_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0                  MK_ADDR_CONST(0x1282000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0_BOND_OUT_UARTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0                   MK_ADDR_CONST(0x1283000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_RESET_VAL                         MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_RESET_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_READ_MASK                         MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_WRITE_MASK                        MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_SHIFT                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_LSB                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_DEFAULT                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_CLK_S                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_CLK_M                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_MSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_DEFAULT                 MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0                     MK_ADDR_CONST(0x210000)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0_SWR_MSSNVL_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0                 MK_ADDR_CONST(0x210004)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0_SET_SWR_MSSNVL_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0                 MK_ADDR_CONST(0x210008)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0_CLR_SWR_MSSNVL_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0                 MK_ADDR_CONST(0x21000c)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_RESET_VAL                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_RANGE                       3:3
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL4_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL3_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL2_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0_SWR_HSH_MSSNVL1_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0                     MK_ADDR_CONST(0x210010)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_RANGE                       3:3
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL4_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL3_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL2_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0_SET_SWR_HSH_MSSNVL1_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0                     MK_ADDR_CONST(0x210014)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_RANGE                       3:3
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL4_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL3_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL2_RST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0_CLR_SWR_HSH_MSSNVL1_RST_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0                 MK_ADDR_CONST(0x211000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_RANGE                   5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CFPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_RANGE                   4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CEPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_RANGE                   3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CDPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CCPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CBPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_RANGE                   0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0_CLK_ENB_MC_CAPA_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0                     MK_ADDR_CONST(0x211004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_RESET_VAL                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_RANGE                   5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CFPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_RANGE                   4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CEPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_RANGE                   3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CDPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CCPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CBPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_RANGE                   0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0_SET_CLK_ENB_MC_CAPA_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0                     MK_ADDR_CONST(0x211008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_RESET_VAL                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_RANGE                   5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CFPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_RANGE                   4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CEPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_RANGE                   3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CDPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CCPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CBPA_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_RANGE                   0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0_CLR_CLK_ENB_MC_CAPA_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0                 MK_ADDR_CONST(0x21100c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_SHIFT                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_RANGE                  5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_LSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CFPA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_RANGE                  4:4
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CEPA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_RANGE                  3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CDPA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_SHIFT                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_RANGE                  2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_LSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CCPA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_SHIFT                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_LSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CBPA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_RANGE                  0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0_BOND_OUT_MC_CAPA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMC_MISC_0
#define CLK_RST_CONTROLLER_EMC_MISC_0                   MK_ADDR_CONST(0x212000)
#define CLK_RST_CONTROLLER_EMC_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EMC_MISC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_EMC_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_EMC_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EMC_MISC_0_RESET_VAL                         MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_EMC_MISC_0_RESET_MASK                        MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_EMC_MISC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_READ_MASK                         MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_EMC_MISC_0_WRITE_MASK                        MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_RANGE                     4:4
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_INIT_ENUM                 DIV_BY_2
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_DIV_BY_1                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_DIV_BY_2                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_RANGE                      1:0
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_INIT_ENUM                  SIDE_A
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SIDE_A                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SIDE_B                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SIDE_C                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SIDE_D                     MK_ENUM_CONST(3)


// Register CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0                     MK_ADDR_CONST(0x1230000)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0_SWR_SLVSEC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0                 MK_ADDR_CONST(0x1230004)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0_SET_SWR_SLVSEC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0                 MK_ADDR_CONST(0x1230008)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0_CLR_SWR_SLVSEC_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0                 MK_ADDR_CONST(0x1231000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSCIL_IOBIST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0_CLK_ENB_SLVSEC_PADCTRL_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0                     MK_ADDR_CONST(0x1231004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_WRITE_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSCIL_IOBIST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0_SET_CLK_ENB_SLVSEC_PADCTRL_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0                     MK_ADDR_CONST(0x1231008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSCIL_IOBIST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0_CLR_CLK_ENB_SLVSEC_PADCTRL_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0                 MK_ADDR_CONST(0x1232000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_RANGE                   2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PADCTRL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_RANGE                   1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSCIL_IOBIST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0_BOND_OUT_SLVSEC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0                  MK_ADDR_CONST(0x1233000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_RESET_VAL                        MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_SRC_CLK_M                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0_SLVSEC_PADCTRL_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Reserved address 0x1233004

// Register CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0                  MK_ADDR_CONST(0x1233008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_RESET_VAL                        MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0_SLVSCIL_IOBIST_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0                      MK_ADDR_CONST(0xf40000)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_SCR                  0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_RESET_VAL                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_RESET_MASK                   MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_READ_MASK                    MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_WRITE_MASK                   MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                 17:17
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_RANGE                 16:16
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_RANGE                    6:6
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                    5:5
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                   4:4
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_RANGE                        3:3
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0_DLA_FALCON_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0                     MK_ADDR_CONST(0xf40004)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_SCR                         0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_RESET_VAL                   MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_RESET_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_READ_MASK                   MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_WRITE_MASK                  MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                  31:28
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                  27:24
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_RANGE                   20:16
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_RANGE                   4:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0_DLA_FALCON_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0                      MK_ADDR_CONST(0xf40008)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_SCR                  0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_RESET_VAL                    MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_RESET_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_READ_MASK                    MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_WRITE_MASK                   MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                 20:16
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                       MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                   15:8
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_RANGE                 7:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0_DLA_FALCON_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0                      MK_ADDR_CONST(0xf4000c)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_SCR                  0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                   31:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0_DLA_FALCON_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0                     MK_ADDR_CONST(0xf40010)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_RANGE                  31:16
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_RANGE                       15:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0_DLA_FALCON_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0                     MK_ADDR_CONST(0xf40014)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_RESET_VAL                   MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_RESET_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_READ_MASK                   MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_WRITE_MASK                  MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                    31:28
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                        27:24
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                    23:20
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                     19:16
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_RANGE                      11:8
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                   7:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0_DLA_FALCON_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0                      MK_ADDR_CONST(0xf40018)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_SCR                  0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_RESET_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_READ_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_RANGE                       15:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0_DLA_FALCON_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0                 MK_ADDR_CONST(0xf4001c)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_SCR                     0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_RESET_VAL                       MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_RESET_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_READ_MASK                       MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_WRITE_MASK                      MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_RANGE                        31:24
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_RANGE                       23:16
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0_DLA_FALCON_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0                  MK_ADDR_CONST(0xf40020)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_SCR                      0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                        7:3
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                 2:1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_RANGE                   0:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0_DLA_FALCON_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0                 MK_ADDR_CONST(0xf40024)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_SCR                     0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_RESET_VAL                       MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_RESET_MASK                      MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_READ_MASK                       MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_WRITE_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                        13:13
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                 12:12
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_FIELD                      MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_RANGE                      11:3
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_DEFAULT                    MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                      2:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0_DLA_FALCON_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xf40028

// Reserved address 0xf4002c

// Reserved address 0xf40030

// Reserved address 0xf40034

// Reserved address 0xf40038

// Reserved address 0xf4003c

// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0                    MK_ADDR_CONST(0xf40040)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0                    MK_ADDR_CONST(0xf40044)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_READ_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                         MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0_DLA_FALCON_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0                     MK_ADDR_CONST(0xf40048)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_SCR                         0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_RESET_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_READ_MASK                   MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                  MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0_DLA_FALCON_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0                     MK_ADDR_CONST(0xf4004c)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_SCR                         0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_RESET_MASK                  MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_READ_MASK                   MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0_DLA_FALCON_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0                        MK_ADDR_CONST(0xf40050)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_SCR                    0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_RESET_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_READ_MASK                      MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_RANGE                 16:8
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                       7:4
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                       3:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0_DLA_FALCON_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0                   MK_ADDR_CONST(0xf40054)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_SCR                       0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_RESET_VAL                         MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_RESET_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_READ_MASK                         MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_WRITE_MASK                        MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                      25:25
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                       19:16
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                        12:12
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_RANGE                  8:8
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_RANGE                   2:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0_DLA_FALCON_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0                   MK_ADDR_CONST(0xf40058)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_SCR                       0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                         MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                        MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                 29:28
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                 23:20
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                   12:4
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                   3:2
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                        1:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0                   MK_ADDR_CONST(0xf4005c)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_SCR                       0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_RESET_MASK                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_READ_MASK                         MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                    3:3
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0_DLA_FALCON_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xf40060

// Reserved address 0xf40064

// Reserved address 0xf40068

// Register CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0                 MK_ADDR_CONST(0xf4006c)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_RESET_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_READ_MASK                       MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_WRITE_MASK                      MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_RANGE                 31:28
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                       27:27
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_RANGE                    25:25
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_RANGE                  24:24
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                        19:16
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                     15:15
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                    2:0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0_DLA_FALCON_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0                        MK_ADDR_CONST(0xf40070)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_SCR                    0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_FIELD                        MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0_DLA_FALCON_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0                        MK_ADDR_CONST(0xf40074)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_SCR                    0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_RANGE                        3:0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0_DLA_FALCON_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xf40078

// Register CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0                 MK_ADDR_CONST(0xf4007c)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_SCR                     0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_RANGE                  3:3
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_INIT_ENUM                      DFLL_DLA_FALCON_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_DFLL_DLA_FALCON_CLK_OUT_PTO_OBS                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_NAFLLDLA_FALCON_PTO_ROOT_CLK_SEL_DFLL_DLA_FALCON_CLK_OUT_PTO_DIV2                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_SHIFT)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_RANGE                    2:0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_DEFAULT                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_INIT_ENUM                        CLK_NULL
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_DFLL_DLA_FALCON_CLK                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_DFLL_DLA_FALCON_PRE_SKP_CLK                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_DFLL_DLA_FALCON_FLL_UPD_CLK                      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_ADC_SOC_REF_DLA_FALCON_CLK                       MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_AVFS_8_CAR_PCLK                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_OSC_DIV_CLK                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0_DLA_FALCON_PTS_CLK_NULL                 MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_RST_DEV_CV_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_0                 MK_ADDR_CONST(0x1190000)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_RANGE                      2:2
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL1_WARM_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_EARLYL2_WARM_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_0_SWR_PREBOOTL2_WARM_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CV_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0                     MK_ADDR_CONST(0x1190004)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_RESET_VAL                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_WRITE_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_RANGE                      2:2
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL1_WARM_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_EARLYL2_WARM_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_SET_0_SET_SWR_PREBOOTL2_WARM_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0                     MK_ADDR_CONST(0x1190008)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_RESET_VAL                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_RESET_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_READ_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_RANGE                      2:2
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL1_WARM_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_EARLYL2_WARM_RST_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0_CLR_SWR_PREBOOTL2_WARM_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0                  MK_ADDR_CONST(0x119000c)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0_SWR_CV_HOST1X_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0                      MK_ADDR_CONST(0x1190010)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0_SET_SWR_CV_HOST1X_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0                      MK_ADDR_CONST(0x1190014)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_READ_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_DEFAULT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0_CLR_SWR_CV_HOST1X_RST_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0                     MK_ADDR_CONST(0x4f0000)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0_SWR_NVDEC1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0                 MK_ADDR_CONST(0x4f0004)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0_SET_SWR_NVDEC1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0                 MK_ADDR_CONST(0x4f0008)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_RESET_VAL                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0_CLR_SWR_NVDEC1_RST_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0                 MK_ADDR_CONST(0x4f1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0_CLK_ENB_NVDEC1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0                     MK_ADDR_CONST(0x4f1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0_SET_CLK_ENB_NVDEC1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0                     MK_ADDR_CONST(0x4f1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_READ_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0_CLR_CLK_ENB_NVDEC1_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0                 MK_ADDR_CONST(0x4f2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_READ_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0_BOND_OUT_NVDEC1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0                  MK_ADDR_CONST(0x4f3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_RESET_VAL                        MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_RESET_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_READ_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_WRITE_MASK                       MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_FIELD                     MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_DEFAULT                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_PLLP_OUT0                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_PLLC2_OUT0                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_PLLC_OUT0                 MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_PLLC3_OUT0                        MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_PLLBPMPCAM_OUT                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_DFLL_NVDEC1                       MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_CLK_S                     MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_SRC_CLK_M                     MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0_NVDEC1_CLK_DIVISOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0                   MK_ADDR_CONST(0x4f3004)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_RESET_VAL                         MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_RESET_MASK                        MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_READ_MASK                         MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_WRITE_MASK                        MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_ENB_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_RANGE                   15:8
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVIDEND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0_SUPER_NVDEC1_DIV_DIVISOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0                   MK_ADDR_CONST(0x4f4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0_CLK_SPARE_REG_NVDEC1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0                  MK_ADDR_CONST(0xf50000)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_RESET_VAL                        MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_RESET_MASK                       MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_READ_MASK                        MK_MASK_CONST(0x3007b)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_WRITE_MASK                       MK_MASK_CONST(0x7b)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_RANGE                 17:17
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_DVCO_MIN_REACHED_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_RANGE                 16:16
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_FLL_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_RANGE                    6:6
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                    5:5
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_PRB_CLKOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                   4:4
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_EN_CLK_PRE_SKP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_RANGE                        3:3
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_BYPASSFLL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0_NVDEC1_NAFLL_CFG1_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0                 MK_ADDR_CONST(0xf50004)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_RESET_VAL                       MK_MASK_CONST(0x86000003)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_RESET_MASK                      MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_READ_MASK                       MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_WRITE_MASK                      MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                  31:28
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                        MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_FAST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                  MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                  27:24
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                        MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_FLL_FRUG_MAIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_RANGE                   20:16
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_MSB                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_PDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_FIELD                   MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_RANGE                   4:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_DEFAULT                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0_NVDEC1_NAFLL_COEFF_MDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0                  MK_ADDR_CONST(0xf50008)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_RESET_VAL                        MK_MASK_CONST(0xa0c00)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_RESET_MASK                       MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_READ_MASK                        MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_WRITE_MASK                       MK_MASK_CONST(0x1fffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_FIELD                 MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_RANGE                 20:16
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT                       MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_SWITCH_LDMEM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                   15:8
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_LSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                 MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_CTRL_LDMEM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0_NVDEC1_NAFLL_CFG2_FLL_INIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0                  MK_ADDR_CONST(0xf5000c)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                   31:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0_NVDEC1_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0                 MK_ADDR_CONST(0xf50010)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_RESET_VAL                       MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_RANGE                  31:16
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_RANGE                       15:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_DEFAULT                     MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0_NVDEC1_NAFLL_CTRL1_FLL_CTRL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0                 MK_ADDR_CONST(0xf50014)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_RESET_VAL                       MK_MASK_CONST(0x26f0000)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_RESET_MASK                      MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_READ_MASK                       MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_WRITE_MASK                      MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                    31:28
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_VFGAIN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                        27:24
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_MSB                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                      MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_INIT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                    MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                    23:20
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                     MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                     19:16
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_FIELD                      MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_RANGE                      11:8
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_DEBUG_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0_NVDEC1_NAFLL_CTRL2_FLL_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0                  MK_ADDR_CONST(0xf50018)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_RANGE                       15:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0_NVDEC1_NAFLL_MISC_DEBUG_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0                     MK_ADDR_CONST(0xf5001c)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_RESET_VAL                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_RESET_MASK                  MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_READ_MASK                   MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_WRITE_MASK                  MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_RANGE                        31:24
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_RANGE                       23:16
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0_NVDEC1_NAFLL_SKP_COEFF_DIVIDEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0                      MK_ADDR_CONST(0xf50020)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                        7:3
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_RAMP_RATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                 2:1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_CTRL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_RANGE                   0:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0_NVDEC1_NAFLL_SKP_CTRL_SKP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0                     MK_ADDR_CONST(0xf50024)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_RESET_VAL                   MK_MASK_CONST(0x50)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_RESET_MASK                  MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_READ_MASK                   MK_MASK_CONST(0x3fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_WRITE_MASK                  MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_RANGE                        13:13
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_RANGE                 12:12
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_TRANSITION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_FIELD                      MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_RANGE                      11:3
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_DEFAULT                    MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_FLL_TIMEOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0_NVDEC1_NAFLL_DVCO_SLOWDOWN_RATIO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xf50028

// Reserved address 0xf5002c

// Reserved address 0xf50030

// Reserved address 0xf50034

// Reserved address 0xf50038

// Reserved address 0xf5003c

// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0                        MK_ADDR_CONST(0xf50040)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_LSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_AUTO_INC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0_NVDEC1_NAFLL_LUT_WRITE_ADDR_OFFSET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0                        MK_ADDR_CONST(0xf50044)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                     MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_READ_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                     MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                 MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                  MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0_NVDEC1_NAFLL_LUT_WRITE_DATA_VAL0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0                 MK_ADDR_CONST(0xf50048)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_RESET_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_READ_MASK                       MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_AUTO_INC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0_NVDEC1_NAFLL_LUT_READ_ADDR_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0                 MK_ADDR_CONST(0xf5004c)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_RESET_MASK                      MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_READ_MASK                       MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_FIELD                   MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                    MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0_NVDEC1_NAFLL_LUT_READ_DATA_VAL0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0                    MK_ADDR_CONST(0xf50050)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_RESET_MASK                         MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_READ_MASK                  MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_RANGE                 16:8
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_NDIV_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                       7:4
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_VFGAIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                       3:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0_NVDEC1_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0                       MK_ADDR_CONST(0xf50054)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_RESET_VAL                     MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_RESET_MASK                    MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_READ_MASK                     MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_WRITE_MASK                    MK_MASK_CONST(0x20f1107)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_RANGE                      25:25
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_MSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_LSB                        MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_SKIP_BAD_DOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                       MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                       19:16
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                        12:12
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RAM_READ_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_SHIFT                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_RANGE                  8:8
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_LSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_RESET_FSM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_RANGE                   2:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0_NVDEC1_NAFLL_LUT_CFG_TEMP_IDX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0                       MK_ADDR_CONST(0xf50058)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                    MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                     MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                    MK_MASK_CONST(0x30f01fff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_RANGE                 29:28
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                 23:20
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                   12:4
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_FIELD                   MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_RANGE                   3:2
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                        MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                        1:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0                       MK_ADDR_CONST(0xf5005c)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_RESET_MASK                    MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_READ_MASK                     MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                    3:3
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0_NVDEC1_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xf50060

// Reserved address 0xf50064

// Reserved address 0xf50068

// Register CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0                     MK_ADDR_CONST(0xf5006c)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_RESET_MASK                  MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_READ_MASK                   MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_WRITE_MASK                  MK_MASK_CONST(0xfb0f8007)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_RANGE                 31:28
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_SOURCE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                       27:27
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_RANGE                    25:25
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_LSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_START_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_RANGE                  24:24
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_MSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_RESET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_RANGE                        19:16
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_NUMCYCLES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_RANGE                     15:15
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                    2:0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0_NVDEC1_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0                    MK_ADDR_CONST(0xf50070)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_FIELD                        MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0_NVDEC1_CLK_FR_CNTR_CNT0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0                    MK_ADDR_CONST(0xf50074)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_READ_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_FIELD                        MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_RANGE                        3:0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0_NVDEC1_CLK_FR_CNTR_CNT1_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0xf50078

// Register CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0                     MK_ADDR_CONST(0xf5007c)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_RESET_VAL                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_READ_MASK                   MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_SHIFT                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_MSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_LSB                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_INIT_ENUM                      DFLL_NVDEC1_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_DFLL_NVDEC1_CLK_OUT_PTO_OBS                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NAFLLNVDEC1_PTO_ROOT_CLK_SEL_DFLL_NVDEC1_CLK_OUT_PTO_DIV2                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_RANGE                    2:0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_DEFAULT                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_INIT_ENUM                        CLK_NULL
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_DFLL_NVDEC1_CLK                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_DFLL_NVDEC1_PRE_SKP_CLK                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_DFLL_NVDEC1_FLL_UPD_CLK                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_ADC_SOC_REF_NVDEC1_CLK                   MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_AVFS_22_CAR_PCLK                 MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_OSC_DIV_CLK                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0_NVDEC1_PTS_CLK_NULL                 MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_PLLMSC_BASE_0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0                        MK_ADDR_CONST(0x20000)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_RESET_VAL                      MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_RESET_MASK                     MK_MASK_CONST(0xec10ffff)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_READ_MASK                      MK_MASK_CONST(0xec10ffff)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_WRITE_MASK                     MK_MASK_CONST(0xe010ffff)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_RANGE                 31:31
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_BYPASSPLL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_REF_ENABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_REF_DIS_REF_DISABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_LOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_SHIFT                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_RANGE                 26:26
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_LSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_FREQ_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_RANGE                      20:20
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_DEFAULT                    MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_BASE_0_PLLMSC_DIVM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSC_MISC1_0
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0                       MK_ADDR_CONST(0x20004)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_RESET_MASK                    MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_READ_MASK                     MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_WRITE_MASK                    MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_RANGE                       31:31
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_SW_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_CLAMP_PH90__PROD                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_FIELD                    MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_RANGE                    27:0
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_DEFAULT_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC1_0_PLLMSC_SETUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSC_MISC2_0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0                       MK_ADDR_CONST(0x20008)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_RESET_VAL                     MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_RESET_MASK                    MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_READ_MASK                     MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_WRITE_MASK                    MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_RANGE                 31:31
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_INIT_ENUM                     PLLMSC_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_PLLMSC_CLK_OUT_PTO_OBS                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTO_ROOT_CLK_SEL_PLLMSC_CLK_OUT_PTO_DIV2                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_RANGE                     17:16
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG14V_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_RANGE                     15:14
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VREG10V_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_RANGE                 13:13
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_OVERRIDE_SYNCMUX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_RANGE                  12:12
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_VCO_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_RANGE                    11:11
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_SYNC_MUX_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_RANGE                       10:10
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_ENABLE_SW_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_RANGE                      9:8
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_PTS_FO                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_RANGE                     5:5
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_RANGE                        4:4
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_EN_LCKDET_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_RANGE                    3:3
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_LOCK_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_RANGE                      2:1
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KCP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_MISC2_0_PLLMSC_KVCO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSCB_BASE_0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0                       MK_ADDR_CONST(0x2000c)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_RESET_VAL                     MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_RESET_MASK                    MK_MASK_CONST(0x4c10ffff)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_READ_MASK                     MK_MASK_CONST(0x4c10ffff)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_WRITE_MASK                    MK_MASK_CONST(0x4010ffff)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_ENABLE_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_LOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_SHIFT                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_RANGE                       26:26
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_LSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_FREQ_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_RANGE                    20:20
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_DEFAULT                  MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_RANGE                    7:0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_DEFAULT                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_BASE_0_PLLMSCB_DIVM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSCB_MISC1_0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0                      MK_ADDR_CONST(0x20010)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_RESET_VAL                    MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_RANGE                       31:31
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_INIT_ENUM                   PLLMSCB_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_PLLMSCB_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_PTO_ROOT_CLK_SEL_PLLMSCB_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_LOCK_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_RANGE                      28:28
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_EN_LCKDET_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_FIELD                  MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_RANGE                  27:0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_MISC1_0_PLLMSCB_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0                      MK_ADDR_CONST(0x20014)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_RESET_VAL                    MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_RESET_MASK                   MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_READ_MASK                    MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SDM_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_SSC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_RANGE                      29:29
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_RANGE                       28:28
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_EN_DITHER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_RANGE                       27:27
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_RANGE                    25:23
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0_PLLMSC_SDM_TEST_OUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0                    MK_ADDR_CONST(0x20018)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_RANGE                   31:16
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MAX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0_PLLMSC_SDM_SSC_MIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0                    MK_ADDR_CONST(0x2001c)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_RANGE                  31:16
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_SSC_STEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0_PLLMSC_SDM_DIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0                     MK_ADDR_CONST(0x20020)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_RESET_VAL                   MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_RESET_MASK                  MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_READ_MASK                   MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_WRITE_MASK                  MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SDM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_SSC_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_RANGE                    29:29
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_RANGE                     28:28
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_EN_DITHER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_RANGE                     27:27
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0_PLLMSCB_SDM_RESET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0                   MK_ADDR_CONST(0x20024)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_RANGE                 31:16
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MAX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0_PLLMSCB_SDM_SSC_MIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0                   MK_ADDR_CONST(0x20028)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_RANGE                        31:16
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_SSC_STEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0_PLLMSCB_SDM_DIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSC_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0                      MK_ADDR_CONST(0xfd0000)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SCR                  EMCSC_SCR_EMCSC_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_MEM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_0_SWR_EMC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0                  MK_ADDR_CONST(0xfd0004)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SCR                      EMCSC_SCR_EMCSC_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_MEM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0_SET_SWR_EMC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0                  MK_ADDR_CONST(0xfd0008)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_SCR                      EMCSC_SCR_EMCSC_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_RESET_VAL                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_MEM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0_CLR_SWR_EMC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0                  MK_ADDR_CONST(0xfd1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_SCR                      EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_RESET_VAL                        MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_RESET_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_READ_MASK                        MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_WRITE_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MCHUBSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC5_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_IOBIST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMCSC_LATENCY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_BBC_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MC_CPU_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DLL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_MEM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0_CLK_ENB_EMC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0                      MK_ADDR_CONST(0xfd1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SCR                  EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_RESET_VAL                    MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_RESET_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_READ_MASK                    MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_WRITE_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MCHUBSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC5_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_IOBIST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMCSC_LATENCY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_BBC_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MC_CPU_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DLL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_MEM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0_SET_CLK_ENB_EMC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0                      MK_ADDR_CONST(0xfd1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_SCR                  EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_RESET_VAL                    MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_RESET_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_READ_MASK                    MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MCHUBSC_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC5_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_IOBIST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMCSC_LATENCY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_BBC_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MC_CPU_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DLL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_MEM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0_CLR_CLK_ENB_EMC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0                  MK_ADDR_CONST(0xfd2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_SCR                      EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_RESET_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_READ_MASK                        MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_WRITE_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_RANGE                   10:10
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MCHUBSC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_RANGE                       9:9
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_RANGE                      8:8
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_IOBIST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_RANGE                     7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMCSC_LATENCY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_RANGE                    6:6
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_BBC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_RANGE                    5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MC_CPU_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_RANGE                   2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DLL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_RANGE                       1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_MEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0_BOND_OUT_EMC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0                   MK_ADDR_CONST(0xfd3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_SCR                       EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_RESET_VAL                         MK_MASK_CONST(0x60900000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_RESET_MASK                        MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_READ_MASK                         MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_WRITE_MASK                        MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_RANGE                      31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_DEFAULT                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_INIT_ENUM                  OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_PLLM_OUT0                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_PLLC_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_PLLP_OUT0                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_OSC_UNDIV                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_PLLM_UD                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_PLLMB_UD                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_PLLMB_OUT0                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_SRC_PLLP_UD                    MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_RANGE                    27:27
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_FORCE_CC_TRIGGER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_RANGE                      26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_INVERT_DCD_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_USE_32KHZ_AS_CLK_M_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_RANGE                 23:23
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_SWITCH_COMPLETE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_RANGE                 20:20
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_PLLC_OUT_FOR_EMC_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_MC_EMC_SAME_FREQ_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_RANGE                     15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_CLK_DIV2_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0_EMC_2X_CLK_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0                   MK_ADDR_CONST(0xfd3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_SCR                       EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_RESET_VAL                         MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_SRC_CLK_M                 MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0                       MK_ADDR_CONST(0xfd3008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_SCR                   EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_RESET_VAL                     MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_RESET_MASK                    MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_READ_MASK                     MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_WRITE_MASK                    MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_PLLM_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_PLLM_UD                       MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_PLLMB_UD                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_PLLMB_OUT0                    MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_SRC_PLLP_UD                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_RANGE                    11:10
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_PLLM_VCOA                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_PLLM_VCOB                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_DDLL_CLK_SEL_EMC_DLL_SWITCH_OUT                       MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0_EMC_DLL_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0                  MK_ADDR_CONST(0xfd300c)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_SCR                      EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_RESET_VAL                        MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_RESET_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_READ_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_RANGE                      31:31
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_RANGE                      11:11
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_RANGE                      10:10
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_RANGE                      9:9
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_RANGE                      8:8
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_RANGE                        7:7
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                    DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_PROG                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_RANGE                  6:6
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                      ACTIVE
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_ACTIVE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_BYPASS                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_RANGE                 4:3
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_RANGE                 1:0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0                     MK_ADDR_CONST(0xfd3010)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_SCR                         EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_RESET_VAL                   MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_RESET_MASK                  MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_READ_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_WRITE_MASK                  MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_ACTIVE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_BYPASS                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0                      MK_ADDR_CONST(0xfd3014)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_SCR                  EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_RESET_VAL                    MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_RESET_MASK                   MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_READ_MASK                    MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_WRITE_MASK                   MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_RANGE                    31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_INIT_ENUM                        CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_OUT0                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLC_OUT0                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_OUT0                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_CLK_M                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_UD                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_UD                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_UD                  MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_LSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_SAFE_INVERT_DCD_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0                     MK_ADDR_CONST(0xfd4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_SCR                         EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0_CLK_SPARE_REG_EMCC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0                      MK_ADDR_CONST(0xfd8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_SCR                  EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0                       MK_ADDR_CONST(0xfd8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_SCR                   EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0                    MK_ADDR_CONST(0xfd8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_SCR                        EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0                   MK_ADDR_CONST(0xfd800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_SCR                       EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0                        MK_ADDR_CONST(0xfd8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_SCR                    EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0_EMCSC_CDB_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0                      MK_ADDR_CONST(0xfd8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_SCR                  EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_RESET_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_READ_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0                       MK_ADDR_CONST(0xfd8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_SCR                   EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0                        MK_ADDR_CONST(0xfd801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_SCR                    EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_RESET_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_READ_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0_EMCSC_CDB_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0                      MK_ADDR_CONST(0xfd8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_SCR                  EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_RESET_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_READ_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_WRITE_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0                  MK_ADDR_CONST(0xfd8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_SCR                      EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0                  MK_ADDR_CONST(0xfd8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_SCR                      EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0                  MK_ADDR_CONST(0xfd802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_SCR                      EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0_EMCSC_CDB_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0                       MK_ADDR_CONST(0xfd8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_SCR                   EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0_EMCSC_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0                        MK_ADDR_CONST(0xfd8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_SCR                    EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0_EMCSC_CDB_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0                   MK_ADDR_CONST(0xfdf000)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SCR                       0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0                       MK_ADDR_CONST(0xfdf004)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SCR                   0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0                   MK_ADDR_CONST(0xfdf008)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSD_BASE_0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0                        MK_ADDR_CONST(0x30000)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_RESET_VAL                      MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_RESET_MASK                     MK_MASK_CONST(0xec10ffff)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_READ_MASK                      MK_MASK_CONST(0xec10ffff)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_WRITE_MASK                     MK_MASK_CONST(0xe010ffff)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_RANGE                 31:31
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_BYPASSPLL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_SHIFT                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_MSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_LSB                      MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_REF_ENABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_REF_DIS_REF_DISABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_SHIFT                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_MSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_LSB                        MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_LOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_SHIFT                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_RANGE                 26:26
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_LSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_FREQ_LOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_RANGE                      20:20
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_DEFAULT                    MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_BASE_0_PLLMSD_DIVM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSD_MISC1_0
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0                       MK_ADDR_CONST(0x30004)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_RESET_MASK                    MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_READ_MASK                     MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_WRITE_MASK                    MK_MASK_CONST(0x8fffffff)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_RANGE                       31:31
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_SW_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_SW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_CLAMP_PH90__PROD                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_FIELD                    MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_RANGE                    27:0
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_DEFAULT_MASK                     MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC1_0_PLLMSD_SETUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSD_MISC2_0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0                       MK_ADDR_CONST(0x30008)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_RESET_VAL                     MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_RESET_MASK                    MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_READ_MASK                     MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_WRITE_MASK                    MK_MASK_CONST(0x8003ff3f)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_SHIFT                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_RANGE                 31:31
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_LSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_INIT_ENUM                     PLLMSD_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_PLLMSD_CLK_OUT_PTO_OBS                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTO_ROOT_CLK_SEL_PLLMSD_CLK_OUT_PTO_DIV2                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_RANGE                     17:16
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG14V_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_FIELD                     MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_RANGE                     15:14
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VREG10V_CTRL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_RANGE                 13:13
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_OVERRIDE_SYNCMUX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_SHIFT                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_RANGE                  12:12
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_MSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_LSB                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_VCO_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_RANGE                    11:11
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_SYNC_MUX_CTRL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_RANGE                       10:10
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_ENABLE_SW_OVERRIDE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_RANGE                      9:8
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_PTS_FO                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_RANGE                     5:5
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_IDDQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_RANGE                        4:4
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_EN_LCKDET_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_RANGE                    3:3
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_LOCK_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_FIELD                      MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_RANGE                      2:1
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KCP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_MISC2_0_PLLMSD_KVCO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSDB_BASE_0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0                       MK_ADDR_CONST(0x3000c)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_RESET_VAL                     MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_RESET_MASK                    MK_MASK_CONST(0x4c10ffff)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_READ_MASK                     MK_MASK_CONST(0x4c10ffff)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_WRITE_MASK                    MK_MASK_CONST(0x4010ffff)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_ENABLE_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_LOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_SHIFT                       MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_RANGE                       26:26
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_LSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_FREQ_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_SHIFT                    MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_RANGE                    20:20
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_MSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_LSB                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_DEFAULT                  MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_RANGE                    7:0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_DEFAULT                  MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_BASE_0_PLLMSDB_DIVM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSDB_MISC1_0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0                      MK_ADDR_CONST(0x30010)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_RESET_VAL                    MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_RANGE                       31:31
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_INIT_ENUM                   PLLMSDB_CLK_OUT_PTO_OBS
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_PLLMSDB_CLK_OUT_PTO_OBS                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_PTO_ROOT_CLK_SEL_PLLMSDB_CLK_OUT_PTO_DIV2                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_LOCK_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_IDDQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_SHIFT                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_RANGE                      28:28
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_MSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_LSB                        MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_EN_LCKDET_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_FIELD                  MK_FIELD_CONST(0xfffffff, CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_RANGE                  27:0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xfffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_MISC1_0_PLLMSDB_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0                      MK_ADDR_CONST(0x30014)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_RESET_VAL                    MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_RESET_MASK                   MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_READ_MASK                    MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_SHIFT                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_LSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SDM_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_SHIFT                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_MSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_LSB                    MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_SSC_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_RANGE                      29:29
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_MSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_SHIFT                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_RANGE                       28:28
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_MSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_LSB                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_EN_DITHER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_SHIFT                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_RANGE                       27:27
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_MSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_LSB                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_SHIFT                    MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_RANGE                    25:23
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_MSB                      MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_LSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0_PLLMSD_SDM_TEST_OUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0                    MK_ADDR_CONST(0x30018)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_RANGE                   31:16
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MAX_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_FIELD                   MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0_PLLMSD_SDM_SSC_MIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0                    MK_ADDR_CONST(0x3001c)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_SHIFT                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_FIELD                  MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_RANGE                  31:16
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_LSB                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_SSC_STEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0_PLLMSD_SDM_DIN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0                     MK_ADDR_CONST(0x30020)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_RESET_VAL                   MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_RESET_MASK                  MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_READ_MASK                   MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_WRITE_MASK                  MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SDM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_SHIFT                        MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_MSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_LSB                  MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_SSC_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_RANGE                    29:29
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_RANGE                     28:28
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_EN_DITHER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_RANGE                     27:27
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0_PLLMSDB_SDM_RESET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0                   MK_ADDR_CONST(0x30024)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_RANGE                 31:16
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MAX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_FIELD                 MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0_PLLMSDB_SDM_SSC_MIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0                   MK_ADDR_CONST(0x30028)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_FIELD                        MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_RANGE                        31:16
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_SSC_STEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0_PLLMSDB_SDM_DIN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSD_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0                      MK_ADDR_CONST(0xfe0000)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SCR                  EMCSD_SCR_EMCSD_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_RESET_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_READ_MASK                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_MEM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_0_SWR_EMC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0                  MK_ADDR_CONST(0xfe0004)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SCR                      EMCSD_SCR_EMCSD_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_MEM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0_SET_SWR_EMC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0                  MK_ADDR_CONST(0xfe0008)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_SCR                      EMCSD_SCR_EMCSD_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_RESET_VAL                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_RESET_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_READ_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_WRITE_MASK                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_MEM_RST_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0_CLR_SWR_EMC_RST_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0                  MK_ADDR_CONST(0xfe1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_SCR                      EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_RESET_VAL                        MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_RESET_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_READ_MASK                        MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_WRITE_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MCHUBSD_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC7_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_IOBIST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMCSD_LATENCY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_BBC_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MC_CPU_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DLL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_MEM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0_CLK_ENB_EMC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0                      MK_ADDR_CONST(0xfe1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SCR                  EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_RESET_VAL                    MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_RESET_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_READ_MASK                    MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_WRITE_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MCHUBSD_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC7_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_IOBIST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMCSD_LATENCY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_BBC_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MC_CPU_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DLL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_MEM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0_SET_CLK_ENB_EMC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0                      MK_ADDR_CONST(0xfe1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_SCR                  EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_RESET_VAL                    MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_RESET_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_READ_MASK                    MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_WRITE_MASK                   MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MCHUBSD_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC7_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_IOBIST_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMCSD_LATENCY_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_BBC_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MC_CPU_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DLL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_MEM_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0_CLR_CLK_ENB_EMC_ENABLE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0                  MK_ADDR_CONST(0xfe2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_SCR                      EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_RESET_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_READ_MASK                        MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_WRITE_MASK                       MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_RANGE                   10:10
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MCHUBSD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_RANGE                       9:9
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_RANGE                      8:8
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_IOBIST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_RANGE                     7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMCSD_LATENCY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_RANGE                    6:6
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_BBC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_RANGE                    5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MC_CPU_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_RANGE                   2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DLL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_RANGE                       1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_MEM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0_BOND_OUT_EMC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0                   MK_ADDR_CONST(0xfe3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_SCR                       EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_RESET_VAL                         MK_MASK_CONST(0x60900000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_RESET_MASK                        MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_READ_MASK                         MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_WRITE_MASK                        MK_MASK_CONST(0xee9180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_SHIFT                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_FIELD                      MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_RANGE                      31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_LSB                        MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_DEFAULT                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_INIT_ENUM                  OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_PLLM_OUT0                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_PLLC_OUT0                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_PLLP_OUT0                  MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_OSC_UNDIV                  MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_PLLM_UD                    MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_PLLMB_UD                   MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_PLLMB_OUT0                 MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_SRC_PLLP_UD                    MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_RANGE                    27:27
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_FORCE_CC_TRIGGER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_SHIFT                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_RANGE                      26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_MSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_LSB                        MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_INVERT_DCD_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_SHIFT                  MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_MSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_LSB                    MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_USE_32KHZ_AS_CLK_M_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_RANGE                 23:23
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_SWITCH_COMPLETE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_RANGE                 20:20
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_PLLC_OUT_FOR_EMC_EN_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_MC_EMC_SAME_FREQ_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_RANGE                     15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_CLK_DIV2_EN_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0_EMC_2X_CLK_DIVISOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0                   MK_ADDR_CONST(0xfe3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_SCR                       EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_RESET_VAL                         MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_RESET_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_READ_MASK                         MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_WRITE_MASK                        MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_SRC_CLK_M                 MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0                       MK_ADDR_CONST(0xfe3008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_SCR                   EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_RESET_VAL                     MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_RESET_MASK                    MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_READ_MASK                     MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_WRITE_MASK                    MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_DEFAULT                       MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_INIT_ENUM                     OSC_UNDIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_PLLM_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_PLLC_OUT0                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_OSC_UNDIV                     MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_PLLM_UD                       MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_PLLMB_UD                      MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_PLLMB_OUT0                    MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_SRC_PLLP_UD                       MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_FIELD                    MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_RANGE                    11:10
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_PLLM_VCOA                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_PLLM_VCOB                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_DDLL_CLK_SEL_EMC_DLL_SWITCH_OUT                       MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0_EMC_DLL_CLK_DIVISOR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0                  MK_ADDR_CONST(0xfe300c)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_SCR                      EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_RESET_VAL                        MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_RESET_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_READ_MASK                        MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_RANGE                      31:31
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_LSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_RANGE                      11:11
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_RANGE                      10:10
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_RANGE                      9:9
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_RANGE                      8:8
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_RANGE                        7:7
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                    DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_PROG                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_RANGE                  6:6
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_MSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_LSB                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                      ACTIVE
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_ACTIVE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_BYPASS                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_RANGE                 4:3
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_RANGE                 1:0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0                     MK_ADDR_CONST(0xfe3010)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_SCR                         EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_RESET_VAL                   MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_RESET_MASK                  MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_READ_MASK                   MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_WRITE_MASK                  MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_MSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_LSB                  MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DISABLE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_ENABLE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_ACTIVE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_BYPASS                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_FIELD                       MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0                      MK_ADDR_CONST(0xfe3014)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_SCR                  EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_RESET_VAL                    MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_RESET_MASK                   MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_READ_MASK                    MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_WRITE_MASK                   MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_FIELD                    MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_RANGE                    31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_INIT_ENUM                        CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_OUT0                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLC_OUT0                        MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_OUT0                        MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_CLK_M                    MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_UD                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_UD                 MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_OUT0                       MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_UD                  MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_MSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_LSB                      MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_SAFE_INVERT_DCD_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0                     MK_ADDR_CONST(0xfe4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_SCR                         EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_FIELD                    MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0_CLK_SPARE_REG_EMCD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0                      MK_ADDR_CONST(0xfe8000)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_SCR                  EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_HIGH_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0                       MK_ADDR_CONST(0xfe8004)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_SCR                   EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_RANGE                 31:0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_THRESH_LOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0                    MK_ADDR_CONST(0xfe8008)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_SCR                        EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_READ_MASK                  MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_FIELD                      MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_RANGE                      23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0                   MK_ADDR_CONST(0xfe800c)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_SCR                       EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_READ_MASK                         MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD                    MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_RANGE                    23:0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_MSB                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DC_CHECK_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0                        MK_ADDR_CONST(0xfe8010)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_SCR                    EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_FAULT_REPORT_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0_EMCSD_CDB_FMON_ACTION_RESET_REQ_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0                      MK_ADDR_CONST(0xfe8014)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_SCR                  EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_RESET_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_READ_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_RANGE                    6:6
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_DC_FAULT_VIOL_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_RANGE                 5:5
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_LOW_THRESH_VIOL_ENABLE                 MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_RANGE                   3:3
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REPORT_OVERFLOW_ERROR_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_CLK_WINDOW_EN_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_COUNTER_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DISABLE                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_ENABLE                 MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0                       MK_ADDR_CONST(0xfe8018)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_SCR                   EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_RESET_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_READ_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_RANGE                   2:2
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_INIT_ENUM                       FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_FALSE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_CLK_STATUS_TRUE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_RANGE                       1:1
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_RANGE                       0:0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0                        MK_ADDR_CONST(0xfe801c)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_SCR                    EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_RESET_MASK                     MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_READ_MASK                      MK_MASK_CONST(0x8000001f)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_INIT_ENUM                   FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_FALSE                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_CLEAR_TRUE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_RANGE                  4:4
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_LSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_FAULT_OUT_STATUS_TRUE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_RANGE                    3:3
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_OVERFLOW_ERROR_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_RANGE                    2:2
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT_ENUM                        FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_RANGE                     1:1
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT_ENUM                 FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_SHIFT)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_RANGE                  0:0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_MSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_INIT_ENUM                      FALSE
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_FALSE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0_EMCSD_CDB_FMON_DC_FAULT_TRUE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0                      MK_ADDR_CONST(0xfe8020)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_SCR                  EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_RESET_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_READ_MASK                    MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_WRITE_MASK                   MK_MASK_CONST(0x80000007)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SHIFT                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_RANGE                       31:31
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_LSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_RANGE                   2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0                  MK_ADDR_CONST(0xfe8024)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_SCR                      EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_READ_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_DONE_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0                  MK_ADDR_CONST(0xfe8028)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_SCR                      EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_RANGE                        2:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_SEL_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0                  MK_ADDR_CONST(0xfe802c)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_SCR                      EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_SHIFT)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_RANGE                       31:0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0_EMCSD_CDB_FMON_LOAD_DATA_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0                       MK_ADDR_CONST(0xfe8030)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_SCR                   EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_READ_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_RANGE                       3:3
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_HOLD_COUNT_SAMPLES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_RANGE                       2:2
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_CLEAR_FMON_COUNTER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_RANGE                 1:1
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MASK_MIN_MAX_COUNT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SHIFT)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_RANGE                        0:0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0_EMCSD_CDB_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0                        MK_ADDR_CONST(0xfe8034)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_SCR                    EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_RESET_MASK                     MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_READ_MASK                      MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_RANGE                        1:1
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_REF_WINDOW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_RANGE                      0:0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0_EMCSD_CDB_FMON_ENABLE_DEBUG_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0                   MK_ADDR_CONST(0xfef000)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SCR                       0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0                       MK_ADDR_CONST(0xfef004)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SCR                   0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0                   MK_ADDR_CONST(0xfef008)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SCR                       0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_MSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_LSB                   MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_MSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_LSB                   MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_MSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_LSB                   MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_MSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_LSB                   MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_MSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_LSB                   MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_MSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_LSB                   MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_MSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_LSB                   MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_MSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_LSB                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_MSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_LSB                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_MSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_LSB                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_MSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_LSB                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_MSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_LSB                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_MSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_LSB                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_MSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_LSB                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0                    MK_ADDR_CONST(0x19b0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0                    MK_ADDR_CONST(0x19b0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x19b0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x19b000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x19b0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x19b0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x19b0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x19b001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x19b0020

// Reserved address 0x19b0024

// Reserved address 0x19b0028

// Reserved address 0x19b002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x19b0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x19b0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x19b0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x19b003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x19b0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x19b0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x19b0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x19b004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x19b0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x19b0054

// Reserved address 0x19b0058

// Reserved address 0x19b005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0                 MK_ADDR_CONST(0x19bf000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0                    MK_ADDR_CONST(0x1a20000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0                    MK_ADDR_CONST(0x1a20004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1a20008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x1a2000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1a20010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1a20014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1a20018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x1a2001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1a20020

// Reserved address 0x1a20024

// Reserved address 0x1a20028

// Reserved address 0x1a2002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1a20030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1a20034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1a20038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x1a2003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1a20040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1a20044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1a20048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1a2004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1a20050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1a20054

// Reserved address 0x1a20058

// Reserved address 0x1a2005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0                 MK_ADDR_CONST(0x1a2f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0                    MK_ADDR_CONST(0x1a00000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0                    MK_ADDR_CONST(0x1a00004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1a00008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x1a0000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1a00010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1a00014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1a00018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x1a0001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1a00020

// Reserved address 0x1a00024

// Reserved address 0x1a00028

// Reserved address 0x1a0002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1a00030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1a00034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1a00038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x1a0003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1a00040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1a00044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1a00048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1a0004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1a00050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1a00054

// Reserved address 0x1a00058

// Reserved address 0x1a0005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0                 MK_ADDR_CONST(0x1a0f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0                    MK_ADDR_CONST(0x18e0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0                    MK_ADDR_CONST(0x18e0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x18e0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x18e000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x18e0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x18e0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x18e0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x18e001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x18e0020

// Reserved address 0x18e0024

// Reserved address 0x18e0028

// Reserved address 0x18e002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x18e0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x18e0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x18e0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x18e003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x18e0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x18e0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x18e0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x18e004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x18e0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x18e0054

// Reserved address 0x18e0058

// Reserved address 0x18e005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0                 MK_ADDR_CONST(0x18ef000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0                    MK_ADDR_CONST(0x18c0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0                    MK_ADDR_CONST(0x18c0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x18c0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x18c000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x18c0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x18c0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x18c0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x18c001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x18c0020

// Reserved address 0x18c0024

// Reserved address 0x18c0028

// Reserved address 0x18c002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x18c0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x18c0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x18c0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x18c003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x18c0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x18c0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x18c0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x18c004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x18c0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x18c0054

// Reserved address 0x18c0058

// Reserved address 0x18c005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0                 MK_ADDR_CONST(0x18cf000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0                    MK_ADDR_CONST(0x1940000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x30001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0                    MK_ADDR_CONST(0x1940004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1940008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x194000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1940010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1940014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_RANGE                 1:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1940018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x194001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1940020

// Reserved address 0x1940024

// Reserved address 0x1940028

// Reserved address 0x194002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1940030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1940034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1940038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x194003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0xd)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0xd)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0xd)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1940040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1940044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1940048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x194004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1940050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1940054

// Reserved address 0x1940058

// Reserved address 0x194005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0                 MK_ADDR_CONST(0x194f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0                     MK_ADDR_CONST(0x1850000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_RESET_VAL                   MK_MASK_CONST(0x20001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_RESET_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_READ_MASK                   MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_RANGE                       31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_DEFAULT                     MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_RANGE                        5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0                     MK_ADDR_CONST(0x1850004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_READ_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0_SWRST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0                     MK_ADDR_CONST(0x1850008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_RESET_VAL                   MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_FIELD                  MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_RANGE                  5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0                       MK_ADDR_CONST(0x185000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_RESET_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_READ_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                   8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Reserved address 0x1850010

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0                    MK_ADDR_CONST(0x1850014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_READ_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_FIELD                  MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_RANGE                  1:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_MSB                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0                       MK_ADDR_CONST(0x1850018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_RESET_VAL                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                   7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0                    MK_ADDR_CONST(0x185001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                        7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                       MK_ENUM_CONST(225)


// Reserved address 0x1850020

// Reserved address 0x1850024

// Reserved address 0x1850028

// Reserved address 0x185002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0                 MK_ADDR_CONST(0x1850030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0                  MK_ADDR_CONST(0x1850034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0                 MK_ADDR_CONST(0x1850038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0                 MK_ADDR_CONST(0x185003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0                  MK_ADDR_CONST(0x1850040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0                   MK_ADDR_CONST(0x1850044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0                  MK_ADDR_CONST(0x1850048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x185004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0                    MK_ADDR_CONST(0x1850050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                 2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                 1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                        MK_ENUM_CONST(1)


// Reserved address 0x1850054

// Reserved address 0x1850058

// Reserved address 0x185005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0                  MK_ADDR_CONST(0x185f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SCR                      0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0                     MK_ADDR_CONST(0x1860000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_RESET_VAL                   MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_RESET_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_READ_MASK                   MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_RANGE                       31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_DEFAULT                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_RANGE                        5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0                     MK_ADDR_CONST(0x1860004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_READ_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0_SWRST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0                     MK_ADDR_CONST(0x1860008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_RESET_VAL                   MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_FIELD                  MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_RANGE                  5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0                       MK_ADDR_CONST(0x186000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_RESET_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_READ_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                   8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0                        MK_ADDR_CONST(0x1860010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_RESET_VAL                      MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_FIELD                    MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                  MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                        -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0                    MK_ADDR_CONST(0x1860014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_WRITE_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_RANGE                  2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0                       MK_ADDR_CONST(0x1860018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_RESET_VAL                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                   7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0                    MK_ADDR_CONST(0x186001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                        7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                       MK_ENUM_CONST(225)


// Reserved address 0x1860020

// Reserved address 0x1860024

// Reserved address 0x1860028

// Reserved address 0x186002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0                 MK_ADDR_CONST(0x1860030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0                  MK_ADDR_CONST(0x1860034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0                 MK_ADDR_CONST(0x1860038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0                 MK_ADDR_CONST(0x186003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                       MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0                  MK_ADDR_CONST(0x1860040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0                   MK_ADDR_CONST(0x1860044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0                  MK_ADDR_CONST(0x1860048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x186004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0                    MK_ADDR_CONST(0x1860050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                         MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                         MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                 4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                 3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                 2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                 1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                        MK_ENUM_CONST(1)


// Reserved address 0x1860054

// Reserved address 0x1860058

// Reserved address 0x186005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0                  MK_ADDR_CONST(0x186f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SCR                      0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0                    MK_ADDR_CONST(0x18a0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x30001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0                    MK_ADDR_CONST(0x18a0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x18a0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x18a000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x18a0010

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x18a0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_RANGE                 1:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x18a0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x18a001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x18a0020

// Reserved address 0x18a0024

// Reserved address 0x18a0028

// Reserved address 0x18a002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x18a0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x18a0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x18a0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x18a003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x18a0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x18a0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x18a0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x18a004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x18a0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x18a0054

// Reserved address 0x18a0058

// Reserved address 0x18a005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0                 MK_ADDR_CONST(0x18af000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0                    MK_ADDR_CONST(0x1990000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0                    MK_ADDR_CONST(0x1990004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1990008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x199000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1990010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1990014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1990018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x199001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1990020

// Reserved address 0x1990024

// Reserved address 0x1990028

// Reserved address 0x199002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1990030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1990034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1990038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x199003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1990040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1990044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1990048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x199004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1990050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1990054

// Reserved address 0x1990058

// Reserved address 0x199005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0                 MK_ADDR_CONST(0x199f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0                    MK_ADDR_CONST(0x1980000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0                    MK_ADDR_CONST(0x1980004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1980008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x198000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x1980010

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1980014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1980018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x198001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1980020

// Reserved address 0x1980024

// Reserved address 0x1980028

// Reserved address 0x198002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1980030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1980034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1980038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x198003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1980040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1980044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1980048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x198004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1980050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1980054

// Reserved address 0x1980058

// Reserved address 0x198005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0                 MK_ADDR_CONST(0x198f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0                    MK_ADDR_CONST(0x1900000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0xb0001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0                    MK_ADDR_CONST(0x1900004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1900008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x190000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1900010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1900014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_RANGE                 3:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1900018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x190001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1900020

// Reserved address 0x1900024

// Reserved address 0x1900028

// Reserved address 0x190002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1900030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_RANGE                    11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_RANGE                    10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1900034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1900038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_RANGE                    11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_RANGE                    10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x190003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0xfe1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0xfe1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0xfe1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_RANGE                    11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_RANGE                    10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1900040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1900044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_RANGE                      11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_RANGE                      10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1900048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x190004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1900050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RANGE                        9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RANGE                        8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1900054

// Reserved address 0x1900058

// Reserved address 0x190005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0                 MK_ADDR_CONST(0x190f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0                    MK_ADDR_CONST(0x1970000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x20001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0                    MK_ADDR_CONST(0x1970004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1970008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x197000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x1970010

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1970014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_RANGE                 1:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1970018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x197001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1970020

// Reserved address 0x1970024

// Reserved address 0x1970028

// Reserved address 0x197002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1970030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1970034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1970038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x197003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1970040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1970044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1970048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x197004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1970050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1970054

// Reserved address 0x1970058

// Reserved address 0x197005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0                 MK_ADDR_CONST(0x197f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0                     MK_ADDR_CONST(0x1890000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_RESET_VAL                   MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_RESET_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_READ_MASK                   MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_RANGE                       31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_DEFAULT                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_RANGE                        5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0                     MK_ADDR_CONST(0x1890004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_READ_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0_SWRST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0                     MK_ADDR_CONST(0x1890008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_RESET_VAL                   MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_FIELD                  MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_RANGE                  5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0                       MK_ADDR_CONST(0x189000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_RESET_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_READ_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                   8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0                        MK_ADDR_CONST(0x1890010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_RESET_VAL                      MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_FIELD                    MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                  MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                        -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0                    MK_ADDR_CONST(0x1890014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_WRITE_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_RANGE                  2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0                       MK_ADDR_CONST(0x1890018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_RESET_VAL                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                   7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0                    MK_ADDR_CONST(0x189001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                        7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                       MK_ENUM_CONST(225)


// Reserved address 0x1890020

// Reserved address 0x1890024

// Reserved address 0x1890028

// Reserved address 0x189002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0                 MK_ADDR_CONST(0x1890030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0                  MK_ADDR_CONST(0x1890034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0                 MK_ADDR_CONST(0x1890038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0                 MK_ADDR_CONST(0x189003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                       MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0                  MK_ADDR_CONST(0x1890040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0                   MK_ADDR_CONST(0x1890044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0                  MK_ADDR_CONST(0x1890048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x189004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0                    MK_ADDR_CONST(0x1890050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                         MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                         MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                 4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                 3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                 2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                 1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                        MK_ENUM_CONST(1)


// Reserved address 0x1890054

// Reserved address 0x1890058

// Reserved address 0x189005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0                  MK_ADDR_CONST(0x189f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SCR                      0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0                    MK_ADDR_CONST(0x1a10000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0                    MK_ADDR_CONST(0x1a10004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1a10008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x1a1000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1a10010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1a10014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1a10018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x1a1001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1a10020

// Reserved address 0x1a10024

// Reserved address 0x1a10028

// Reserved address 0x1a1002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1a10030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1a10034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1a10038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x1a1003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1a10040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1a10044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1a10048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1a1004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1a10050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1a10054

// Reserved address 0x1a10058

// Reserved address 0x1a1005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0                 MK_ADDR_CONST(0x1a1f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0                    MK_ADDR_CONST(0x19a0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0                    MK_ADDR_CONST(0x19a0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x19a0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x19a000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x19a0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x19a0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x19a0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x19a001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x19a0020

// Reserved address 0x19a0024

// Reserved address 0x19a0028

// Reserved address 0x19a002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x19a0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x19a0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x19a0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x19a003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x19a0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x19a0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x19a0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x19a004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x19a0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x19a0054

// Reserved address 0x19a0058

// Reserved address 0x19a005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0                 MK_ADDR_CONST(0x19af000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0                    MK_ADDR_CONST(0x19c0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0                    MK_ADDR_CONST(0x19c0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x19c0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x19c000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x19c0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x19c0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x19c0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x19c001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x19c0020

// Reserved address 0x19c0024

// Reserved address 0x19c0028

// Reserved address 0x19c002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x19c0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x19c0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x19c0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x19c003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x19c0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x19c0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x19c0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x19c004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x19c0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x19c0054

// Reserved address 0x19c0058

// Reserved address 0x19c005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0                 MK_ADDR_CONST(0x19cf000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0                    MK_ADDR_CONST(0x1a80000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x60001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0                    MK_ADDR_CONST(0x1a80004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1a80008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x1a8000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1a80010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1a80014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1a80018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x1a8001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1a80020

// Reserved address 0x1a80024

// Reserved address 0x1a80028

// Reserved address 0x1a8002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1a80030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1a80034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1a80038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x1a8003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x71)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x71)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x71)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1a80040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1a80044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1a80048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1a8004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1a80050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1a80054

// Reserved address 0x1a80058

// Reserved address 0x1a8005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0                 MK_ADDR_CONST(0x1a8f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0                     MK_ADDR_CONST(0x1840000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_RESET_VAL                   MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_RESET_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_READ_MASK                   MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_RANGE                       31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_DEFAULT                     MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_RANGE                        5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0                     MK_ADDR_CONST(0x1840004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_READ_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0_SWRST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0                     MK_ADDR_CONST(0x1840008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_RESET_VAL                   MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_FIELD                  MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_RANGE                  5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0                       MK_ADDR_CONST(0x184000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_RESET_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_READ_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                   8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0                        MK_ADDR_CONST(0x1840010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_RESET_VAL                      MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_FIELD                    MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                  MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                        -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0                    MK_ADDR_CONST(0x1840014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_WRITE_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_RANGE                  2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0                       MK_ADDR_CONST(0x1840018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_RESET_VAL                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                   7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0                    MK_ADDR_CONST(0x184001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                        7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                       MK_ENUM_CONST(225)


// Reserved address 0x1840020

// Reserved address 0x1840024

// Reserved address 0x1840028

// Reserved address 0x184002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0                 MK_ADDR_CONST(0x1840030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0                  MK_ADDR_CONST(0x1840034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0                 MK_ADDR_CONST(0x1840038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0                 MK_ADDR_CONST(0x184003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                      MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                       MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                      MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0                  MK_ADDR_CONST(0x1840040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0                   MK_ADDR_CONST(0x1840044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0                  MK_ADDR_CONST(0x1840048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x184004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0                    MK_ADDR_CONST(0x1840050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                 5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                 4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                 3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                 2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                 1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                        MK_ENUM_CONST(1)


// Reserved address 0x1840054

// Reserved address 0x1840058

// Reserved address 0x184005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0                  MK_ADDR_CONST(0x184f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SCR                      0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0                    MK_ADDR_CONST(0x19d0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0                    MK_ADDR_CONST(0x19d0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x19d0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x19d000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x19d0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x19d0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x19d0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x19d001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x19d0020

// Reserved address 0x19d0024

// Reserved address 0x19d0028

// Reserved address 0x19d002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x19d0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x19d0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x19d0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x19d003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x19d0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x19d0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x19d0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x19d004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x19d0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x19d0054

// Reserved address 0x19d0058

// Reserved address 0x19d005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0                 MK_ADDR_CONST(0x19df000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0                  MK_ADDR_CONST(0xaf0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_RESET_VAL                        MK_MASK_CONST(0x60001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_RESET_MASK                       MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_READ_MASK                        MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_FIELD                    MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_RANGE                    31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_DEFAULT                  MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_FIELD                     MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_RANGE                     5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0                  MK_ADDR_CONST(0xaf0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0_SWRST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0                  MK_ADDR_CONST(0xaf0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_RESET_VAL                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_READ_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_DEFAULT                     MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0                    MK_ADDR_CONST(0xaf000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_RESET_MASK                         MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_READ_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                        MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                        8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0                     MK_ADDR_CONST(0xaf0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_RESET_VAL                   MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_FIELD                 MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_RANGE                 31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_MSB                   MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                       MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                     -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0                 MK_ADDR_CONST(0xaf0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_RANGE                       2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0                    MK_ADDR_CONST(0xaf0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_RESET_VAL                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                        7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0                 MK_ADDR_CONST(0xaf001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                     MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                     7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                    MK_ENUM_CONST(225)


// Reserved address 0xaf0020

// Reserved address 0xaf0024

// Reserved address 0xaf0028

// Reserved address 0xaf002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0                      MK_ADDR_CONST(0xaf0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_RANGE                   6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                   5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                   4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                   3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                   2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                   1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                   0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0                       MK_ADDR_CONST(0xaf0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_RANGE                    6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                    1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0                      MK_ADDR_CONST(0xaf0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_RANGE                   6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                   5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                   4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                   3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                   2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                   1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                   0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0                      MK_ADDR_CONST(0xaf003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                   MK_MASK_CONST(0x79)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                    MK_MASK_CONST(0x79)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                   MK_MASK_CONST(0x79)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_RANGE                   6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                   5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                   4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                   3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                   0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                  MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0                       MK_ADDR_CONST(0xaf0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_RANGE                    6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                    1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0                        MK_ADDR_CONST(0xaf0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0                       MK_ADDR_CONST(0xaf0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_RANGE                    6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                    1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Reserved address 0xaf004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0                 MK_ADDR_CONST(0xaf0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                     MK_ENUM_CONST(1)


// Reserved address 0xaf0054

// Reserved address 0xaf0058

// Reserved address 0xaf005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0                       MK_ADDR_CONST(0xaff000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SCR                   0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0                    MK_ADDR_CONST(0x18d0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x60001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0                    MK_ADDR_CONST(0x18d0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x18d0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x18d000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x18d0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x18d0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x18d0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x18d001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x18d0020

// Reserved address 0x18d0024

// Reserved address 0x18d0028

// Reserved address 0x18d002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x18d0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x18d0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x18d0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x18d003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x71)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x71)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x71)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x18d0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x18d0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x18d0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x18d004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x18d0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x18d0054

// Reserved address 0x18d0058

// Reserved address 0x18d005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0                 MK_ADDR_CONST(0x18df000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0                     MK_ADDR_CONST(0x1870000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_RESET_VAL                   MK_MASK_CONST(0x130001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_RESET_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_READ_MASK                   MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_RANGE                       31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_DEFAULT                     MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_RANGE                        5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0                     MK_ADDR_CONST(0x1870004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_READ_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0_SWRST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0                     MK_ADDR_CONST(0x1870008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_RESET_VAL                   MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_FIELD                  MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_RANGE                  5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0                       MK_ADDR_CONST(0x187000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_RESET_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_READ_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                   8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0                        MK_ADDR_CONST(0x1870010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_RESET_VAL                      MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_FIELD                    MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                  MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                        -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0                    MK_ADDR_CONST(0x1870014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_RESET_MASK                         MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_READ_MASK                  MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_WRITE_MASK                         MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_FIELD                  MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_RANGE                  4:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_MSB                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0                       MK_ADDR_CONST(0x1870018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_RESET_VAL                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                   7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0                    MK_ADDR_CONST(0x187001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                        7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                       MK_ENUM_CONST(225)


// Reserved address 0x1870020

// Reserved address 0x1870024

// Reserved address 0x1870028

// Reserved address 0x187002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0                 MK_ADDR_CONST(0x1870030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_RANGE                     19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_RANGE                     18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_RANGE                     17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_RANGE                     16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_RANGE                     15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_RANGE                     14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_RANGE                     13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_RANGE                     12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0                  MK_ADDR_CONST(0x1870034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_RANGE                      19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_RANGE                      18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_RANGE                      17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_RANGE                      16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_RANGE                      15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_RANGE                      14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_RANGE                      13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_RANGE                      12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_RANGE                      11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_RANGE                      10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0                 MK_ADDR_CONST(0x1870038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_RANGE                     19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_RANGE                     18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_RANGE                     17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_RANGE                     16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_RANGE                     15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_RANGE                     14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_RANGE                     13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_RANGE                     12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0                 MK_ADDR_CONST(0x187003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                      MK_MASK_CONST(0xfff81)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                       MK_MASK_CONST(0xfff81)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                      MK_MASK_CONST(0xfff81)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT                     MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_RANGE                     19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_MSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_LSB                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT                     MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_RANGE                     18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_MSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_LSB                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT                     MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_RANGE                     17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_MSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_LSB                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_RANGE                     16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_RANGE                     15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_RANGE                     14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_RANGE                     13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_RANGE                     12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0                  MK_ADDR_CONST(0x1870040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_RANGE                      19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_RANGE                      18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_RANGE                      17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_RANGE                      16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_RANGE                      15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_RANGE                      14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_RANGE                      13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_RANGE                      12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_RANGE                      11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_RANGE                      10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0                   MK_ADDR_CONST(0x1870044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_RANGE                        9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_RANGE                        8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0                  MK_ADDR_CONST(0x1870048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                        MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_RANGE                      19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR19_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_RANGE                      18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR18_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_RANGE                      17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR17_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_RANGE                      16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR16_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_RANGE                      15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR15_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_RANGE                      14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR14_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_RANGE                      13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR13_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_RANGE                      12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_RANGE                      11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_RANGE                      10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x187004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0                    MK_ADDR_CONST(0x1870050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                         MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                         MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_RANGE                        19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR19_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_RANGE                        18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR18_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_RANGE                        17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR17_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_RANGE                        16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR16_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_RANGE                        15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR15_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RANGE                        14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RANGE                        13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RANGE                        12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RANGE                        11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RANGE                        10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RANGE                 9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_MSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_LSB                   MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RANGE                 8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_LSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RANGE                 7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RANGE                 6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_MSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_LSB                   MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                 5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                 4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                 3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                 2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                 1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                        MK_ENUM_CONST(1)


// Reserved address 0x1870054

// Reserved address 0x1870058

// Reserved address 0x187005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0                  MK_ADDR_CONST(0x187f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SCR                      0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0                   MK_ADDR_CONST(0xcf0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_RESET_VAL                         MK_MASK_CONST(0x100001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_RESET_MASK                        MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_READ_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_RANGE                     31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_DEFAULT                   MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_FIELD                      MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_RANGE                      5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0                   MK_ADDR_CONST(0xcf0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0_SWRST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0                   MK_ADDR_CONST(0xcf0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_RESET_VAL                         MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_READ_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_RANGE                        5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_DEFAULT                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0                     MK_ADDR_CONST(0xcf000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_RESET_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_READ_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                 8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0                      MK_ADDR_CONST(0xcf0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_RESET_VAL                    MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                      -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0                  MK_ADDR_CONST(0xcf0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_READ_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_FIELD                        MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_RANGE                        4:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0                     MK_ADDR_CONST(0xcf0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_RESET_VAL                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                 7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0                  MK_ADDR_CONST(0xcf001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                      7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                     MK_ENUM_CONST(225)


// Reserved address 0xcf0020

// Reserved address 0xcf0024

// Reserved address 0xcf0028

// Reserved address 0xcf002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0                       MK_ADDR_CONST(0xcf0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_RANGE                   16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_RANGE                   15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_RANGE                   14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_RANGE                   13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_RANGE                   12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_RANGE                   11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_RANGE                   10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_RANGE                    9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_RANGE                    8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_RANGE                    7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_RANGE                    6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                    1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0                        MK_ADDR_CONST(0xcf0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_RANGE                    16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_RANGE                    15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_RANGE                    14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_RANGE                    13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_RANGE                    12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_RANGE                    11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_RANGE                    10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_NOFORCE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FORCE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0                       MK_ADDR_CONST(0xcf0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_RANGE                   16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_RANGE                   15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_RANGE                   14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_RANGE                   13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_RANGE                   12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT                   MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_RANGE                   11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_MSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_LSB                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT                   MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_RANGE                   10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_MSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_LSB                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT                    MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_RANGE                    9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_MSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_LSB                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_RANGE                    8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_MSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_LSB                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_RANGE                    7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_MSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_LSB                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                    MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_RANGE                    6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_MSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_LSB                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                    1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0                       MK_ADDR_CONST(0xcf003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                    MK_MASK_CONST(0x1f001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                     MK_MASK_CONST(0x1f001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                    MK_MASK_CONST(0x1f001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT                   MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_RANGE                   16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_MSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_LSB                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT                   MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_RANGE                   15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_LSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SHIFT                   MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_RANGE                   14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_MSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_LSB                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SHIFT                   MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_RANGE                   13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_MSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_LSB                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SHIFT                   MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_RANGE                   12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_MSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_LSB                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DISABLE                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_ENABLE                  MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0                        MK_ADDR_CONST(0xcf0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_RANGE                    16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_RANGE                    15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_RANGE                    14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_RANGE                    13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_RANGE                    12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_RANGE                    11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_RANGE                    10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0                 MK_ADDR_CONST(0xcf0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_RANGE                     16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_MSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_RANGE                     15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_LSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_RANGE                     14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_RANGE                     13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_RANGE                     12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0                        MK_ADDR_CONST(0xcf0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT                    MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_RANGE                    16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_MSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_LSB                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR16_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT                    MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_RANGE                    15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_MSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_LSB                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR15_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_RANGE                    14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR14_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_RANGE                    13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR13_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_RANGE                    12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR12_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_RANGE                    11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_RANGE                    10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0xcf004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0                  MK_ADDR_CONST(0xcf0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                       MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                       MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_RANGE                      16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR16_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_RANGE                      15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR15_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RANGE                      14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RANGE                      13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RANGE                      12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RANGE                      11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RANGE                      10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_NORELOAD                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RELOAD                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                      MK_ENUM_CONST(1)


// Reserved address 0xcf0054

// Reserved address 0xcf0058

// Reserved address 0xcf005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0                        MK_ADDR_CONST(0xcff000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SCR                    0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0                    MK_ADDR_CONST(0x19e0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0                    MK_ADDR_CONST(0x19e0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x19e0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x19e000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x19e0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x19e0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x19e0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x19e001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x19e0020

// Reserved address 0x19e0024

// Reserved address 0x19e0028

// Reserved address 0x19e002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x19e0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x19e0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x19e0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x19e003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x39)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x39)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x39)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x19e0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x19e0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x19e0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x19e004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x19e0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x19e0054

// Reserved address 0x19e0058

// Reserved address 0x19e005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0                 MK_ADDR_CONST(0x19ef000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0                    MK_ADDR_CONST(0x18f0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x70001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0                    MK_ADDR_CONST(0x18f0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x18f0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x18f000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x18f0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x18f0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x18f0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x18f001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x18f0020

// Reserved address 0x18f0024

// Reserved address 0x18f0028

// Reserved address 0x18f002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x18f0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x18f0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x18f0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x18f003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0xfd)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0xfd)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0xfd)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x18f0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x18f0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x18f0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x18f004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x18f0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x18f0054

// Reserved address 0x18f0058

// Reserved address 0x18f005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0                 MK_ADDR_CONST(0x18ff000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0                    MK_ADDR_CONST(0x19f0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0xe0001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0                    MK_ADDR_CONST(0x19f0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x19f0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x19f000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x19f0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x19f0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_RANGE                 3:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x19f0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x19f001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x19f0020

// Reserved address 0x19f0024

// Reserved address 0x19f0028

// Reserved address 0x19f002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x19f0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_RANGE                    14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_RANGE                    13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_RANGE                    12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_RANGE                    11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_RANGE                    10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x19f0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_RANGE                     14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_RANGE                     13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_RANGE                     12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x19f0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_RANGE                    14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_RANGE                    13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_RANGE                    12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_RANGE                    11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_RANGE                    10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x19f003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x7fc1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x7fc1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x7fc1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SHIFT                    MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_RANGE                    14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_MSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_LSB                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR14_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SHIFT                    MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_RANGE                    13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_MSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_LSB                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR13_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SHIFT                    MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_RANGE                    12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_MSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_LSB                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_RANGE                    11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_MSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_LSB                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_RANGE                    10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_MSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_LSB                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_RANGE                     9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_MSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_LSB                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_RANGE                     8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_MSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_LSB                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_RANGE                     7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_LSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_RANGE                     6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_MSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_LSB                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x19f0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_RANGE                     14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_RANGE                     13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_RANGE                     12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x19f0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_RANGE                      14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_RANGE                      13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_RANGE                      12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_RANGE                      11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_RANGE                      10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x19f0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT                     MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_RANGE                     14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_MSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_LSB                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT                     MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_RANGE                     13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_MSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_LSB                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_RANGE                     12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_MSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_LSB                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_RANGE                     11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_MSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_LSB                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_RANGE                     10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_MSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_LSB                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x19f004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x19f0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7fff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RANGE                        9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RANGE                        8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x19f0054

// Reserved address 0x19f0058

// Reserved address 0x19f005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0                 MK_ADDR_CONST(0x19ff000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0                    MK_ADDR_CONST(0x1930000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0                    MK_ADDR_CONST(0x1930004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1930008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x193000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1930010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1930014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1930018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x193001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1930020

// Reserved address 0x1930024

// Reserved address 0x1930028

// Reserved address 0x193002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1930030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1930034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1930038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x193003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1930040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1930044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1930048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x193004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1930050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1930054

// Reserved address 0x1930058

// Reserved address 0x193005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0                 MK_ADDR_CONST(0x193f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0                    MK_ADDR_CONST(0x18b0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0                    MK_ADDR_CONST(0x18b0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x18b0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x18b000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x18b0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x18b0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x18b0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x18b001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x18b0020

// Reserved address 0x18b0024

// Reserved address 0x18b0028

// Reserved address 0x18b002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x18b0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x18b0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x18b0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x18b003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x18b0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x18b0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x18b0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x18b004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x18b0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x18b0054

// Reserved address 0x18b0058

// Reserved address 0x18b005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0                 MK_ADDR_CONST(0x18bf000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0                   MK_ADDR_CONST(0x10f0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_RESET_VAL                         MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_RESET_MASK                        MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_READ_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_RANGE                     31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_DEFAULT                   MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_FIELD                      MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_RANGE                      5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0                   MK_ADDR_CONST(0x10f0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0_SWRST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0                   MK_ADDR_CONST(0x10f0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_RESET_VAL                         MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_READ_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_RANGE                        5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_DEFAULT                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0                     MK_ADDR_CONST(0x10f000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_RESET_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_READ_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                 8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0                      MK_ADDR_CONST(0x10f0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_RESET_VAL                    MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                      -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0                  MK_ADDR_CONST(0x10f0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_RANGE                        2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0                     MK_ADDR_CONST(0x10f0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_RESET_VAL                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                 7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0                  MK_ADDR_CONST(0x10f001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                      7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                     MK_ENUM_CONST(225)


// Reserved address 0x10f0020

// Reserved address 0x10f0024

// Reserved address 0x10f0028

// Reserved address 0x10f002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0                       MK_ADDR_CONST(0x10f0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                    1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0                        MK_ADDR_CONST(0x10f0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0                       MK_ADDR_CONST(0x10f0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                    1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0                       MK_ADDR_CONST(0x10f003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                    MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                    MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0                        MK_ADDR_CONST(0x10f0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0                 MK_ADDR_CONST(0x10f0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0                        MK_ADDR_CONST(0x10f0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x10f004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0                  MK_ADDR_CONST(0x10f0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                      MK_ENUM_CONST(1)


// Reserved address 0x10f0054

// Reserved address 0x10f0058

// Reserved address 0x10f005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0                        MK_ADDR_CONST(0x10ff000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SCR                    0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0                     MK_ADDR_CONST(0x1880000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_RESET_VAL                   MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_RESET_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_READ_MASK                   MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_FIELD                       MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_RANGE                       31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_MSB                 MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_DEFAULT                     MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_RANGE                        5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_DEFAULT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0                     MK_ADDR_CONST(0x1880004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_READ_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0_SWRST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0                     MK_ADDR_CONST(0x1880008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_RESET_VAL                   MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_FIELD                  MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_RANGE                  5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_MSB                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_DEFAULT                        MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0                       MK_ADDR_CONST(0x188000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_RESET_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_READ_MASK                     MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                   8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_MSB                     MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0                        MK_ADDR_CONST(0x1880010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_RESET_VAL                      MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_FIELD                    MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_MSB                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                  MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                        -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0                    MK_ADDR_CONST(0x1880014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_RESET_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_READ_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_WRITE_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_RANGE                  2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_MSB                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0                       MK_ADDR_CONST(0x1880018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_RESET_VAL                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_READ_MASK                     MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                   MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                   7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0                    MK_ADDR_CONST(0x188001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                        MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                        7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                 MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                       MK_ENUM_CONST(225)


// Reserved address 0x1880020

// Reserved address 0x1880024

// Reserved address 0x1880028

// Reserved address 0x188002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0                 MK_ADDR_CONST(0x1880030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0                  MK_ADDR_CONST(0x1880034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0                 MK_ADDR_CONST(0x1880038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0                 MK_ADDR_CONST(0x188003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                       MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0                  MK_ADDR_CONST(0x1880040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0                   MK_ADDR_CONST(0x1880044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                        MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0                  MK_ADDR_CONST(0x1880048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x188004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0                    MK_ADDR_CONST(0x1880050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                         MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                         MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                 4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                   MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                 3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                   MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                 2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                 1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                        MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                 MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                 0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                      MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                        MK_ENUM_CONST(1)


// Reserved address 0x1880054

// Reserved address 0x1880058

// Reserved address 0x188005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0                  MK_ADDR_CONST(0x188f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SCR                      0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_RANGE                    29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_RANGE                    27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_RANGE                  26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_RANGE                        23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_RANGE                        22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_RANGE                        21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_RANGE                        20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_RANGE                        19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_RANGE                        18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_RANGE                        17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_RANGE                        16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_RANGE                        15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_RANGE                        14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_RANGE                        13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_RANGE                        12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_RANGE                        11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_RANGE                        10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_RANGE                        9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_RANGE                        8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_RANGE                        7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_RANGE                        6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0                    MK_ADDR_CONST(0x1a30000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x40001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0                    MK_ADDR_CONST(0x1a30004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1a30008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x1a3000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1a30010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1a30014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1a30018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x1a3001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1a30020

// Reserved address 0x1a30024

// Reserved address 0x1a30028

// Reserved address 0x1a3002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1a30030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1a30034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1a30038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x1a3003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1a30040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1a30044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1a30048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1a3004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1a30050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1a30054

// Reserved address 0x1a30058

// Reserved address 0x1a3005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0                 MK_ADDR_CONST(0x1a3f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0                   MK_ADDR_CONST(0xdf0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_RESET_VAL                         MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_RESET_MASK                        MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_READ_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SHIFT                     MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_FIELD                     MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_RANGE                     31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_MSB                       MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_LSB                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_DEFAULT                   MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_FIELD                      MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_RANGE                      5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0                   MK_ADDR_CONST(0xdf0004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_WRITE_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0_SWRST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0                   MK_ADDR_CONST(0xdf0008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_RESET_VAL                         MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_READ_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_FIELD                        MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_RANGE                        5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_DEFAULT                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0                     MK_ADDR_CONST(0xdf000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_RESET_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_READ_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                 MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                 8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_MSB                   MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                  MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0                      MK_ADDR_CONST(0xdf0010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_RESET_VAL                    MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_MSB                    MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                      -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0                  MK_ADDR_CONST(0xdf0014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_READ_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_RANGE                        2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0                     MK_ADDR_CONST(0xdf0018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_DUAL                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_SCR                         EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_RESET_VAL                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_READ_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                 MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                 7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0                  MK_ADDR_CONST(0xdf001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                      MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                      7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                     MK_ENUM_CONST(225)


// Reserved address 0xdf0020

// Reserved address 0xdf0024

// Reserved address 0xdf0028

// Reserved address 0xdf002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0                       MK_ADDR_CONST(0xdf0030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                    1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0                        MK_ADDR_CONST(0xdf0034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0                       MK_ADDR_CONST(0xdf0038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                    MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                    1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0                       MK_ADDR_CONST(0xdf003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                    MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                    MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                    MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                    5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                    MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                    4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                    MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                    3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                    MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                    2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                   MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                    MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                    0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                  MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                   MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0                        MK_ADDR_CONST(0xdf0040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0                 MK_ADDR_CONST(0xdf0044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0                        MK_ADDR_CONST(0xdf0048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0xdf004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0                  MK_ADDR_CONST(0xdf0050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                      MK_ENUM_CONST(1)


// Reserved address 0xdf0054

// Reserved address 0xdf0058

// Reserved address 0xdf005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0                        MK_ADDR_CONST(0xdff000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SCR                    0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0                    MK_ADDR_CONST(0x1950000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x20001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0                    MK_ADDR_CONST(0x1950004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1950008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x195000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x1950010

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1950014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_RANGE                 1:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1950018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x195001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1950020

// Reserved address 0x1950024

// Reserved address 0x1950028

// Reserved address 0x195002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1950030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1950034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1950038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x195003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1950040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1950044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1950048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x195004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1950050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1950054

// Reserved address 0x1950058

// Reserved address 0x195005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0                 MK_ADDR_CONST(0x195f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0                    MK_ADDR_CONST(0x1960000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x20001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0                    MK_ADDR_CONST(0x1960004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1960008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x196000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Reserved address 0x1960010

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1960014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_RANGE                 1:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1960018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x196001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1960020

// Reserved address 0x1960024

// Reserved address 0x1960028

// Reserved address 0x196002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1960030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1960034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1960038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x196003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1960040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1960044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1960048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x196004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1960050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1960054

// Reserved address 0x1960058

// Reserved address 0x196005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0                 MK_ADDR_CONST(0x196f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0                    MK_ADDR_CONST(0x1920000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0                    MK_ADDR_CONST(0x1920004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1920008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x192000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1920010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1920014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1920018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x192001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1920020

// Reserved address 0x1920024

// Reserved address 0x1920028

// Reserved address 0x192002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1920030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1920034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1920038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x192003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x39)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x39)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x39)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1920040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1920044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1920048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x192004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1920050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1920054

// Reserved address 0x1920058

// Reserved address 0x192005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0                 MK_ADDR_CONST(0x192f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0                    MK_ADDR_CONST(0x1910000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0                    MK_ADDR_CONST(0x1910004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1910008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x191000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1910010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1910014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1910018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x191001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1910020

// Reserved address 0x1910024

// Reserved address 0x1910028

// Reserved address 0x191002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1910030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1910034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1910038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x191003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x39)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x39)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x39)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1910040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1910044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1910048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x191004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1910050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1910054

// Reserved address 0x1910058

// Reserved address 0x191005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0                 MK_ADDR_CONST(0x191f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0                    MK_ADDR_CONST(0x1a70000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x20001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0                    MK_ADDR_CONST(0x1a70004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1a70008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x1a7000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1a70010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1a70014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_RANGE                 1:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1a70018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x1a7001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1a70020

// Reserved address 0x1a70024

// Reserved address 0x1a70028

// Reserved address 0x1a7002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1a70030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1a70034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1a70038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x1a7003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1a70040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1a70044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1a70048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1a7004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1a70050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1a70054

// Reserved address 0x1a70058

// Reserved address 0x1a7005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0                 MK_ADDR_CONST(0x1a7f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0                    MK_ADDR_CONST(0x1a60000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x20001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0                    MK_ADDR_CONST(0x1a60004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1a60008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x1a6000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1a60010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1a60014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_RANGE                 1:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1a60018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x1a6001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1a60020

// Reserved address 0x1a60024

// Reserved address 0x1a60028

// Reserved address 0x1a6002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1a60030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1a60034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1a60038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x1a6003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1a60040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1a60044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1a60048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1a6004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1a60050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1a60054

// Reserved address 0x1a60058

// Reserved address 0x1a6005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0                 MK_ADDR_CONST(0x1a6f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0                    MK_ADDR_CONST(0x1a50000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0                    MK_ADDR_CONST(0x1a50004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1a50008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x1a5000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1a50010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1a50014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1a50018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x1a5001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1a50020

// Reserved address 0x1a50024

// Reserved address 0x1a50028

// Reserved address 0x1a5002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1a50030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1a50034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1a50038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x1a5003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1a50040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1a50044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1a50048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1a5004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1a50050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1a50054

// Reserved address 0x1a50058

// Reserved address 0x1a5005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0                 MK_ADDR_CONST(0x1a5f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0                    MK_ADDR_CONST(0x1a40000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0x50001)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_RANGE                      31:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0                    MK_ADDR_CONST(0x1a40004)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0x1a40008)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_DUAL                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0x1a4000c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0                       MK_ADDR_CONST(0x1a40010)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_DUAL                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_SCR                   EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_RESET_VAL                     MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_RANGE                   31:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_DEFAULT                 MK_MASK_CONST(0xdead0000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0_VALUE_INIT_ENUM                       -559087616


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0x1a40014)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0x1a40018)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0x1a4001c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)


// Reserved address 0x1a40020

// Reserved address 0x1a40024

// Reserved address 0x1a40028

// Reserved address 0x1a4002c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0x1a40030)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0x1a40034)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0x1a40038)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0x1a4003c)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x3d)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0x1a40040)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0x1a40044)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0x1a40048)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x1a4004c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0x1a40050)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)


// Reserved address 0x1a40054

// Reserved address 0x1a40058

// Reserved address 0x1a4005c

// Register CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0                 MK_ADDR_CONST(0x1a4f000)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_DUAL                    0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SCR                     0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_RANGE                       23:23
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_RANGE                       22:22
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_RANGE                       21:21
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_RANGE                       20:20
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_RANGE                       19:19
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_RANGE                       18:18
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_RANGE                       17:17
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_RANGE                       16:16
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_RANGE                       15:15
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_RANGE                       14:14
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_RANGE                       13:13
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_RANGE                       12:12
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_RANGE                       11:11
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_RANGE                       10:10
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_RANGE                       9:9
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_RANGE                       8:8
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_RANGE                       7:7
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_RANGE                       6:6
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_RANGE                       5:5
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_RANGE                       4:4
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_RANGE                       3:3
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_RANGE                       2:2
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_RANGE                       1:1
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_RANGE                       0:0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARCLK_RST_REGS(_op_) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_KFUSE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPU_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0) \
_op_(CLK_RST_CONTROLLER_SWD_CLK_DIVISOR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SWD_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0) \
_op_(CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE2_0) \
_op_(CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0) \
_op_(CLK_RST_CONTROLLER_LOCK_BOND_OUT_0) \
_op_(CLK_RST_CONTROLLER_INTSTATUS_0) \
_op_(CLK_RST_CONTROLLER_SPARE_REG0_0) \
_op_(CLK_RST_CONTROLLER_CLK_MASK_ARM_0) \
_op_(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) \
_op_(CLK_RST_CONTROLLER_SOC2CCPLEX_CLKOBS_CLK_SEL_0) \
_op_(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0) \
_op_(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0) \
_op_(CLK_RST_CONTROLLER_INTMASK_0) \
_op_(CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UPHY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0) \
_op_(CLK_RST_CONTROLLER_PLLE_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLE_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLE_BASE1_0) \
_op_(CLK_RST_CONTROLLER_PLLE_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0) \
_op_(CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0) \
_op_(CLK_RST_CONTROLLER_PLLE_AUX_0) \
_op_(CLK_RST_CONTROLLER_PLLE_AUX1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLC_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_5_0) \
_op_(CLK_RST_CONTROLLER_PLLC_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLC_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0) \
_op_(CLK_RST_CONTROLLER_PLLM_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLM_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLM_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLM_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLP_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLP_OUTA_0) \
_op_(CLK_RST_CONTROLLER_PLLP_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLP_RESHIFT_0) \
_op_(CLK_RST_CONTROLLER_PLLP_OUTC_0) \
_op_(CLK_RST_CONTROLLER_PLLP_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLP_MISC2_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0) \
_op_(CLK_RST_CONTROLLER_PLLA_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLA_OUT_0) \
_op_(CLK_RST_CONTROLLER_PLLD_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLD_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLD_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLD_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLD_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C1_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0) \
_op_(CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_I2C1_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C5_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0) \
_op_(CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_I2C5_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ISP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0) \
_op_(CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_ISP_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0) \
_op_(CLK_RST_CONTROLLER_ISP_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_ISP_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_0) \
_op_(CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VI_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0) \
_op_(CLK_RST_CONTROLLER_VI_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_VI_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0) \
_op_(CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0) \
_op_(CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_EMC_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0) \
_op_(CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0) \
_op_(CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_RST_0) \
_op_(CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C3_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0) \
_op_(CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_I2C3_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTD_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CSITE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0) \
_op_(CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_LA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_LA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_LA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C4_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0) \
_op_(CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_I2C4_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR1_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0) \
_op_(CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_SOR1_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR2_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0) \
_op_(CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_SOR2_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR3_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0) \
_op_(CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_SOR3_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX2_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX3_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX2_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX3_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR0_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0) \
_op_(CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_SOR0_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SATA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SATA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HDA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SE_0) \
_op_(CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0) \
_op_(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0) \
_op_(CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_APE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_APE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0) \
_op_(CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_APE_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLREFE_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLREFE_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLREFE_OUT_0) \
_op_(CLK_RST_CONTROLLER_PLLREFE_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLREFE_MISC2_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_MISC_5_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLCV2_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLCV2_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLCV2_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLCV2_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLCV2_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLCV2_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLCV3_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLCV3_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLCV3_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLCV3_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLCV3_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLCV3_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0) \
_op_(CLK_RST_CONTROLLER_CTRL_DMIC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0) \
_op_(CLK_RST_CONTROLLER_CTRL_DMIC2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C6_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C6_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0) \
_op_(CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_I2C6_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0) \
_op_(CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_VIC_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0) \
_op_(CLK_RST_CONTROLLER_VIC_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_VIC_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVJPG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVENC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0) \
_op_(CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0) \
_op_(CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_NVENC_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_OUT1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_QSPI0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_QSPI0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSECB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0) \
_op_(CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_STRAP_TSECB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ADSP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0) \
_op_(CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0) \
_op_(CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MPHY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0) \
_op_(CLK_RST_CONTROLLER_CLK_MPHY_MISC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0) \
_op_(CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLD4_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLD4_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLD4_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLD4_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLD4_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLD4_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0) \
_op_(CLK_RST_CONTROLLER_CTRL_DMIC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0) \
_op_(CLK_RST_CONTROLLER_CTRL_DMIC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0) \
_op_(CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0) \
_op_(CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TACH_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EQOS_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_TX_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0) \
_op_(CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_EQOS_TX_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_EQOS_AXI_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0) \
_op_(CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0) \
_op_(CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0) \
_op_(CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_RST_0) \
_op_(CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_CSI_CLK_SRC_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_NVCSI_SCR_NVCSI_FMON_0) \
_op_(CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C7_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C7_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0) \
_op_(CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_I2C7_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C9_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C9_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0) \
_op_(CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_I2C9_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C12_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C13_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C14_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM6_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM7_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM8_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTF_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NIC_RATE_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_THERM_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0) \
_op_(CLK_RST_CONTROLLER_BPMP_CPU_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOPM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOVC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_AON_NIC_RATE_0) \
_op_(CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0) \
_op_(CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0) \
_op_(CLK_RST_CONTROLLER_CAN1_CORE_RATE_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN1_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0) \
_op_(CLK_RST_CONTROLLER_CAN2_CORE_RATE_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CAN2_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C2_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C8_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C8_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C10_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_I2C10_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_CTRL_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_OSC_CTRL_0) \
_op_(CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0) \
_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_0) \
_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0) \
_op_(CLK_RST_CONTROLLER_MISC_REG0_0) \
_op_(CLK_RST_CONTROLLER_PLLP_WB0_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_PWR_SEQ_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0) \
_op_(CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_STATUS_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0) \
_op_(CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_SHARED_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_CAN_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_GPIO_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_HSP_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_I2C2_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_I2C8_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_I2C10_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_OSC_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_PLLAON_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_PWM4_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_SPI2_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_TSC_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_UARTC_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_UARTG_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_UFS_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_TOUCH_0) \
_op_(CLK_RST_CONTROLLER_AON_APB_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_AON_I2C_SLOW_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CAN1_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CAN2_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_I2C2_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_I2C8_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_I2C10_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_AON_CPU_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_TSC_REF_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_CLR_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_BASE_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_MISC_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_CTRL_0_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_CTRL_1_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_CTRL_2_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_SETUP_1_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_SETUP_2_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0) \
_op_(CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_SCE_NIC_RATE_0) \
_op_(CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0) \
_op_(CLK_RST_CONTROLLER_SCE_SCR_SHARED_0) \
_op_(CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_SCE_SCR_DVFS_0) \
_op_(CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_CTRL3_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_ACC_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0) \
_op_(CLK_RST_CONTROLLER_CLK_M_DIVIDE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_QSPI1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_QSPI1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DLA0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DLA0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0) \
_op_(CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_DLA0_SCR_DLA0_CORE_FMON_0) \
_op_(CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DLA1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DLA1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0) \
_op_(CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_DLA1_SCR_DLA1_CORE_FMON_0) \
_op_(CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_AXI_CLR_0) \
_op_(CLK_RST_CONTROLLER_PVA0_SWR_RESET_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_DMA1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_CPU_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA0_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_DMA1_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_CPU_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_APB_0) \
_op_(CLK_RST_CONTROLLER_PVA0_CPU_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_PVA0_AXI_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_PVA0_APB_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA0_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_DMA1_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_PROCCFG_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_PM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_CPU_AXI_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA0_VPS1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS0_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA0_VPS1_0) \
_op_(CLK_RST_CONTROLLER_PVA0_VPS0_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_PVA0_VPS1_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS0_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_VPS1_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_CFG_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_H1X_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_SEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_RAMIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_TSCTN_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0) \
_op_(CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_PVA0_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_AXI_CLR_0) \
_op_(CLK_RST_CONTROLLER_PVA1_SWR_RESET_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_DMA1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_CPU_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA0_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_DMA1_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_CPU_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_APB_0) \
_op_(CLK_RST_CONTROLLER_PVA1_CPU_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_PVA1_AXI_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_PVA1_APB_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA0_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_DMA1_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_PROCCFG_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_PM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_CPU_AXI_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PVA1_VPS1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS0_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PVA1_VPS1_0) \
_op_(CLK_RST_CONTROLLER_PVA1_VPS0_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_PVA1_VPS1_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS0_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_VPS1_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_CFG_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_H1X_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_SEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_RAMIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_TSCTN_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_CPU_AXI_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0) \
_op_(CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_PVA1_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CVNAS_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CVNAS_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CVNAS_FCM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CV_SIMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_CTRL3_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_MONITOR_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_ACC_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_NUM_SAMPLES_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_OBS_WAIT_TIME_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_OBS_DATA_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED0_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_SAVED1_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT0_0) \
_op_(CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_PM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_PM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_PM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNRCE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_RCE_NIC_RATE_0) \
_op_(CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_RCE_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_RCE_APB_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_SW_INTERFACE_CTL_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_CTL_0_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_TIMEOUT_CTL_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_PLL_LOCK_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_PLL_PWRUP_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_SWITCH_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_SWDIV_PLL_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_1US_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_STATUS_0) \
_op_(CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0) \
_op_(CLK_RST_CONTROLLER_RCE_SCR_SHARED_0) \
_op_(CLK_RST_CONTROLLER_RCE_SCR_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_RCE_SCR_DVFS_0) \
_op_(CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_IST_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVLINK_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVLINK_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0) \
_op_(CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0) \
_op_(CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVLINK_SYS_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_TXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0) \
_op_(CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_NVLINK_SYS_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_LINK_0_TXLINK_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_PM_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT_0) \
_op_(CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG0_0) \
_op_(CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVHS_UPHY_PLL0_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVHS_UPHY_PLL_SEL_CFG0_0) \
_op_(CLK_RST_CONTROLLER_NVHS_UPHY_C5_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVHS_UPHY_C5_TX_BYP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVHS_UPHY_NVL_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG1_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG2_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG3_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG0_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG1_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG2_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL1_CFG3_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG0_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG1_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG2_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL2_CFG3_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG0_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG1_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG2_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL3_CFG3_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG0_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_PLL_SEL_CFG4_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_C0_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_C1_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_C2_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_C3_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_C4_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_SSP0_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_SSP1_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_SSP2_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_SSP3_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_SATA_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_IST0_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0) \
_op_(CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_0_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_2_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_3_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0) \
_op_(CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_PEX0_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0) \
_op_(CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0) \
_op_(CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_PEX1_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0) \
_op_(CLK_RST_CONTROLLER_PLLNVHS_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLNVHS_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLNVHS_BASE1_0) \
_op_(CLK_RST_CONTROLLER_PLLNVHS_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL1_0) \
_op_(CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL2_0) \
_op_(CLK_RST_CONTROLLER_PLLNVHS_AUX_0) \
_op_(CLK_RST_CONTROLLER_PLLNVHS_AUX1_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVENC1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0) \
_op_(CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TPIU_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TPIU_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_PAD_0) \
_op_(CLK_RST_CONTROLLER_CTRL_TPIU_PAD_0) \
_op_(CLK_RST_CONTROLLER_CTRL_TPIU_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTH_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTH_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MSSNVL_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MSSNVL_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0) \
_op_(CLK_RST_CONTROLLER_EMC_MISC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SLVSEC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CV_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CV_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CV_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDEC1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSC_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMSC_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSC_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSCB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMSCB_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSC_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMSC_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSC_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSCB_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_LATENCY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_DLL_0) \
_op_(CLK_RST_CONTROLLER_EMCSC_DIV_CLK_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_EMCSC_PLLC_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0) \
_op_(CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0) \
_op_(CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_RST_0) \
_op_(CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0) \
_op_(CLK_RST_CONTROLLER_PLLMSD_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMSD_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSD_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSDB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMSDB_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSD_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMSD_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSD_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSDB_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSD_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSD_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_LATENCY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_DLL_0) \
_op_(CLK_RST_CONTROLLER_EMCSD_DIV_CLK_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_EMCSD_PLLC_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_ACTION_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CONFIG_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_FAULT_STATUS_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0) \
_op_(CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0) \
_op_(CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_RST_0) \
_op_(CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_SWRESET_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_TYPE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_CURRENT_COUNTER_VALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_USERVALUE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INDEX_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_CORRECTABLE_THRESHOLD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0) \
_op_(CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_CLK_RST_CONTROLLER 0x00000000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_27 0x019b0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR     0x019b0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_34 0x01a20000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR     0x01a20000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_32 0x01a00000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR     0x01a00000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_14 0x018e0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR     0x018e0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_12 0x018c0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR     0x018c0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_20 0x01940000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR     0x01940000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_5  0x01850000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR      0x01850000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_6  0x01860000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR      0x01860000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_10 0x018a0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR     0x018a0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_25 0x01990000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR     0x01990000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_24 0x01980000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR     0x01980000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_16 0x01900000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR     0x01900000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_23 0x01970000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR     0x01970000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_9  0x01890000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR      0x01890000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_33 0x01a10000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR     0x01a10000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_26 0x019a0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR     0x019a0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_28 0x019c0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR     0x019c0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_40 0x01a80000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR     0x01a80000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_4  0x01840000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR      0x01840000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_29 0x019d0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR     0x019d0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP       0x00af0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR   0x00af0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_13 0x018d0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR     0x018d0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_7  0x01870000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR      0x01870000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_AON        0x00cf0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR    0x00cf0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_30 0x019e0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR     0x019e0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_15 0x018f0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR     0x018f0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_31 0x019f0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR     0x019f0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_19 0x01930000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR     0x01930000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_11 0x018b0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR     0x018b0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_RCE        0x010f0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR    0x010f0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_8  0x01880000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR      0x01880000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_35 0x01a30000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR     0x01a30000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_SCE        0x00df0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR    0x00df0000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_21 0x01950000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR     0x01950000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_22 0x01960000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR     0x01960000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_18 0x01920000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR     0x01920000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_17 0x01910000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR     0x01910000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_39 0x01a70000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR     0x01a70000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_38 0x01a60000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR     0x01a60000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_37 0x01a50000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR     0x01a50000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_36 0x01a40000
#define BASE_ADDRESS_CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR     0x01a40000

//
// ARCLK_RST REGISTER BANKS
//

#define CLK_RST_CONTROLLER0_FIRST_REG 0x0000 // CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0
#define CLK_RST_CONTROLLER0_LAST_REG 0x0020 // CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0
#define CLK_RST_CONTROLLER1_FIRST_REG 0x1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0
#define CLK_RST_CONTROLLER1_LAST_REG 0x1024 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0
#define CLK_RST_CONTROLLER2_FIRST_REG 0x2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0
#define CLK_RST_CONTROLLER2_LAST_REG 0x2008 // CLK_RST_CONTROLLER_TSOSC_FTM_MUX_SELECT_0
#define CLK_RST_CONTROLLER3_FIRST_REG 0x3000 // CLK_RST_CONTROLLER_CLK_SPARE0_0
#define CLK_RST_CONTROLLER3_LAST_REG 0x300c // CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0
#define CLK_RST_CONTROLLER4_FIRST_REG 0x3024 // CLK_RST_CONTROLLER_LOCK_BOND_OUT_0
#define CLK_RST_CONTROLLER4_LAST_REG 0x3024 // CLK_RST_CONTROLLER_LOCK_BOND_OUT_0
#define CLK_RST_CONTROLLER5_FIRST_REG 0x30a4 // CLK_RST_CONTROLLER_INTSTATUS_0
#define CLK_RST_CONTROLLER5_LAST_REG 0x30a8 // CLK_RST_CONTROLLER_SPARE_REG0_0
#define CLK_RST_CONTROLLER6_FIRST_REG 0x30b8 // CLK_RST_CONTROLLER_CLK_MASK_ARM_0
#define CLK_RST_CONTROLLER6_LAST_REG 0x30cc // CLK_RST_CONTROLLER_INTMASK_0
#define CLK_RST_CONTROLLER7_FIRST_REG 0x30d8 // CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0
#define CLK_RST_CONTROLLER7_LAST_REG 0x30dc // CLK_RST_CONTROLLER_SERDES_CLK_CTRL_0
#define CLK_RST_CONTROLLER8_FIRST_REG 0x40000 // CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0
#define CLK_RST_CONTROLLER8_LAST_REG 0x40014 // CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0
#define CLK_RST_CONTROLLER9_FIRST_REG 0x41000 // CLK_RST_CONTROLLER_PLLE_SS_CNTL_0
#define CLK_RST_CONTROLLER9_LAST_REG 0x41020 // CLK_RST_CONTROLLER_PLLE_AUX1_0
#define CLK_RST_CONTROLLER10_FIRST_REG 0x50000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0
#define CLK_RST_CONTROLLER10_LAST_REG 0x50030 // CLK_RST_CONTROLLER_PLLC_SS_CTRL2_0
#define CLK_RST_CONTROLLER11_FIRST_REG 0x51000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0
#define CLK_RST_CONTROLLER11_LAST_REG 0x51000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0
#define CLK_RST_CONTROLLER12_FIRST_REG 0x60000 // CLK_RST_CONTROLLER_PLLM_BASE_0
#define CLK_RST_CONTROLLER12_LAST_REG 0x60028 // CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0
#define CLK_RST_CONTROLLER13_FIRST_REG 0x70000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0
#define CLK_RST_CONTROLLER13_LAST_REG 0x70024 // CLK_RST_CONTROLLER_PLLP_MISC2_0
#define CLK_RST_CONTROLLER14_FIRST_REG 0x71000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0
#define CLK_RST_CONTROLLER14_LAST_REG 0x71000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0
#define CLK_RST_CONTROLLER15_FIRST_REG 0x80000 // CLK_RST_CONTROLLER_PLLA_BASE_0
#define CLK_RST_CONTROLLER15_LAST_REG 0x80018 // CLK_RST_CONTROLLER_PLLA_OUT_0
#define CLK_RST_CONTROLLER16_FIRST_REG 0xa0000 // CLK_RST_CONTROLLER_PLLD_BASE_0
#define CLK_RST_CONTROLLER16_LAST_REG 0xa0000 // CLK_RST_CONTROLLER_PLLD_BASE_0
#define CLK_RST_CONTROLLER17_FIRST_REG 0xa0008 // CLK_RST_CONTROLLER_PLLD_MISC_0
#define CLK_RST_CONTROLLER17_LAST_REG 0xa001c // CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0
#define CLK_RST_CONTROLLER18_FIRST_REG 0xc0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0
#define CLK_RST_CONTROLLER18_LAST_REG 0xc0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0
#define CLK_RST_CONTROLLER19_FIRST_REG 0xc1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0
#define CLK_RST_CONTROLLER19_LAST_REG 0xc1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0
#define CLK_RST_CONTROLLER20_FIRST_REG 0xc2000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0
#define CLK_RST_CONTROLLER20_LAST_REG 0xc2004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0
#define CLK_RST_CONTROLLER21_FIRST_REG 0xd0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0
#define CLK_RST_CONTROLLER21_LAST_REG 0xd0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0
#define CLK_RST_CONTROLLER22_FIRST_REG 0xd1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0
#define CLK_RST_CONTROLLER22_LAST_REG 0xd1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0
#define CLK_RST_CONTROLLER23_FIRST_REG 0xd2000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0
#define CLK_RST_CONTROLLER23_LAST_REG 0xd2004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0
#define CLK_RST_CONTROLLER24_FIRST_REG 0xe0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0
#define CLK_RST_CONTROLLER24_LAST_REG 0xe0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0
#define CLK_RST_CONTROLLER25_FIRST_REG 0xe1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0
#define CLK_RST_CONTROLLER25_LAST_REG 0xe1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0
#define CLK_RST_CONTROLLER26_FIRST_REG 0xe2000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0
#define CLK_RST_CONTROLLER26_LAST_REG 0xe2004 // CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0
#define CLK_RST_CONTROLLER27_FIRST_REG 0xe3000 // CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0
#define CLK_RST_CONTROLLER27_LAST_REG 0xe3000 // CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0
#define CLK_RST_CONTROLLER28_FIRST_REG 0x110000 // CLK_RST_CONTROLLER_RST_DEV_SPI3_0
#define CLK_RST_CONTROLLER28_LAST_REG 0x110008 // CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0
#define CLK_RST_CONTROLLER29_FIRST_REG 0x111000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0
#define CLK_RST_CONTROLLER29_LAST_REG 0x111008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0
#define CLK_RST_CONTROLLER30_FIRST_REG 0x112000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0
#define CLK_RST_CONTROLLER30_LAST_REG 0x112000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0
#define CLK_RST_CONTROLLER31_FIRST_REG 0x113000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0
#define CLK_RST_CONTROLLER31_LAST_REG 0x113000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0
#define CLK_RST_CONTROLLER32_FIRST_REG 0x120000 // CLK_RST_CONTROLLER_RST_DEV_I2C1_0
#define CLK_RST_CONTROLLER32_LAST_REG 0x120008 // CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0
#define CLK_RST_CONTROLLER33_FIRST_REG 0x121000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0
#define CLK_RST_CONTROLLER33_LAST_REG 0x121008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0
#define CLK_RST_CONTROLLER34_FIRST_REG 0x122000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0
#define CLK_RST_CONTROLLER34_LAST_REG 0x122000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0
#define CLK_RST_CONTROLLER35_FIRST_REG 0x123000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0
#define CLK_RST_CONTROLLER35_LAST_REG 0x123000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0
#define CLK_RST_CONTROLLER36_FIRST_REG 0x128000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C1_0
#define CLK_RST_CONTROLLER36_LAST_REG 0x128034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C1_0
#define CLK_RST_CONTROLLER37_FIRST_REG 0x12f000 // CLK_RST_CONTROLLER_I2C1_SCR_FUNC_0
#define CLK_RST_CONTROLLER37_LAST_REG 0x12f004 // CLK_RST_CONTROLLER_I2C1_SCR_FMON_0
#define CLK_RST_CONTROLLER38_FIRST_REG 0x130000 // CLK_RST_CONTROLLER_RST_DEV_I2C5_0
#define CLK_RST_CONTROLLER38_LAST_REG 0x130008 // CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0
#define CLK_RST_CONTROLLER39_FIRST_REG 0x131000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0
#define CLK_RST_CONTROLLER39_LAST_REG 0x131008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0
#define CLK_RST_CONTROLLER40_FIRST_REG 0x132000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0
#define CLK_RST_CONTROLLER40_LAST_REG 0x132000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0
#define CLK_RST_CONTROLLER41_FIRST_REG 0x133000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0
#define CLK_RST_CONTROLLER41_LAST_REG 0x133000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0
#define CLK_RST_CONTROLLER42_FIRST_REG 0x138000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C5_0
#define CLK_RST_CONTROLLER42_LAST_REG 0x138034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C5_0
#define CLK_RST_CONTROLLER43_FIRST_REG 0x13f000 // CLK_RST_CONTROLLER_I2C5_SCR_FUNC_0
#define CLK_RST_CONTROLLER43_LAST_REG 0x13f004 // CLK_RST_CONTROLLER_I2C5_SCR_FMON_0
#define CLK_RST_CONTROLLER44_FIRST_REG 0x140000 // CLK_RST_CONTROLLER_RST_DEV_SPI1_0
#define CLK_RST_CONTROLLER44_LAST_REG 0x140008 // CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0
#define CLK_RST_CONTROLLER45_FIRST_REG 0x141000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0
#define CLK_RST_CONTROLLER45_LAST_REG 0x141008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0
#define CLK_RST_CONTROLLER46_FIRST_REG 0x142000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0
#define CLK_RST_CONTROLLER46_LAST_REG 0x142000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0
#define CLK_RST_CONTROLLER47_FIRST_REG 0x143000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0
#define CLK_RST_CONTROLLER47_LAST_REG 0x143000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0
#define CLK_RST_CONTROLLER48_FIRST_REG 0x170000 // CLK_RST_CONTROLLER_RST_DEV_ISP_0
#define CLK_RST_CONTROLLER48_LAST_REG 0x170008 // CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0
#define CLK_RST_CONTROLLER49_FIRST_REG 0x171000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0
#define CLK_RST_CONTROLLER49_LAST_REG 0x171008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0
#define CLK_RST_CONTROLLER50_FIRST_REG 0x172000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0
#define CLK_RST_CONTROLLER50_LAST_REG 0x172000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0
#define CLK_RST_CONTROLLER51_FIRST_REG 0x173000 // CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0
#define CLK_RST_CONTROLLER51_LAST_REG 0x173004 // CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER52_FIRST_REG 0x174000 // CLK_RST_CONTROLLER_CLK_SPARE_ISP_0
#define CLK_RST_CONTROLLER52_LAST_REG 0x174000 // CLK_RST_CONTROLLER_CLK_SPARE_ISP_0
#define CLK_RST_CONTROLLER53_FIRST_REG 0x178000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_ISP_0
#define CLK_RST_CONTROLLER53_LAST_REG 0x178034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_ISP_0
#define CLK_RST_CONTROLLER54_FIRST_REG 0x17f000 // CLK_RST_CONTROLLER_ISP_SCR_FUNC_0
#define CLK_RST_CONTROLLER54_LAST_REG 0x17f004 // CLK_RST_CONTROLLER_ISP_SCR_FMON_0
#define CLK_RST_CONTROLLER55_FIRST_REG 0x180000 // CLK_RST_CONTROLLER_RST_DEV_VI_0
#define CLK_RST_CONTROLLER55_LAST_REG 0x180014 // CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0
#define CLK_RST_CONTROLLER56_FIRST_REG 0x181000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0
#define CLK_RST_CONTROLLER56_LAST_REG 0x181008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0
#define CLK_RST_CONTROLLER57_FIRST_REG 0x182000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0
#define CLK_RST_CONTROLLER57_LAST_REG 0x182000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0
#define CLK_RST_CONTROLLER58_FIRST_REG 0x183000 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_0
#define CLK_RST_CONTROLLER58_LAST_REG 0x183008 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST_0
#define CLK_RST_CONTROLLER59_FIRST_REG 0x188000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VI_0
#define CLK_RST_CONTROLLER59_LAST_REG 0x188034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VI_0
#define CLK_RST_CONTROLLER60_FIRST_REG 0x18f000 // CLK_RST_CONTROLLER_VI_SCR_FUNC_0
#define CLK_RST_CONTROLLER60_LAST_REG 0x18f004 // CLK_RST_CONTROLLER_VI_SCR_FMON_0
#define CLK_RST_CONTROLLER61_FIRST_REG 0x190000 // CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0
#define CLK_RST_CONTROLLER61_LAST_REG 0x190008 // CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0
#define CLK_RST_CONTROLLER62_FIRST_REG 0x191000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0
#define CLK_RST_CONTROLLER62_LAST_REG 0x191008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0
#define CLK_RST_CONTROLLER63_FIRST_REG 0x192000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0
#define CLK_RST_CONTROLLER63_LAST_REG 0x192000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0
#define CLK_RST_CONTROLLER64_FIRST_REG 0x193000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0
#define CLK_RST_CONTROLLER64_LAST_REG 0x193000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0
#define CLK_RST_CONTROLLER65_FIRST_REG 0x1b0000 // CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0
#define CLK_RST_CONTROLLER65_LAST_REG 0x1b0008 // CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0
#define CLK_RST_CONTROLLER66_FIRST_REG 0x1b1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0
#define CLK_RST_CONTROLLER66_LAST_REG 0x1b1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0
#define CLK_RST_CONTROLLER67_FIRST_REG 0x1b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0
#define CLK_RST_CONTROLLER67_LAST_REG 0x1b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0
#define CLK_RST_CONTROLLER68_FIRST_REG 0x1b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0
#define CLK_RST_CONTROLLER68_LAST_REG 0x1b3010 // CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER69_FIRST_REG 0x1c0000 // CLK_RST_CONTROLLER_RST_DEV_UARTA_0
#define CLK_RST_CONTROLLER69_LAST_REG 0x1c0008 // CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0
#define CLK_RST_CONTROLLER70_FIRST_REG 0x1c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0
#define CLK_RST_CONTROLLER70_LAST_REG 0x1c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0
#define CLK_RST_CONTROLLER71_FIRST_REG 0x1c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0
#define CLK_RST_CONTROLLER71_LAST_REG 0x1c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0
#define CLK_RST_CONTROLLER72_FIRST_REG 0x1c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0
#define CLK_RST_CONTROLLER72_LAST_REG 0x1c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0
#define CLK_RST_CONTROLLER73_FIRST_REG 0x1d0000 // CLK_RST_CONTROLLER_RST_DEV_UARTB_0
#define CLK_RST_CONTROLLER73_LAST_REG 0x1d0008 // CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0
#define CLK_RST_CONTROLLER74_FIRST_REG 0x1d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0
#define CLK_RST_CONTROLLER74_LAST_REG 0x1d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0
#define CLK_RST_CONTROLLER75_FIRST_REG 0x1d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0
#define CLK_RST_CONTROLLER75_LAST_REG 0x1d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0
#define CLK_RST_CONTROLLER76_FIRST_REG 0x1d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0
#define CLK_RST_CONTROLLER76_LAST_REG 0x1d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0
#define CLK_RST_CONTROLLER77_FIRST_REG 0x1e0000 // CLK_RST_CONTROLLER_RST_DEV_HOST1X_0
#define CLK_RST_CONTROLLER77_LAST_REG 0x1e0008 // CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0
#define CLK_RST_CONTROLLER78_FIRST_REG 0x1e1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0
#define CLK_RST_CONTROLLER78_LAST_REG 0x1e1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0
#define CLK_RST_CONTROLLER79_FIRST_REG 0x1e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0
#define CLK_RST_CONTROLLER79_LAST_REG 0x1e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0
#define CLK_RST_CONTROLLER80_FIRST_REG 0x1e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
#define CLK_RST_CONTROLLER80_LAST_REG 0x1e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
#define CLK_RST_CONTROLLER81_FIRST_REG 0x1e8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_HOST1X_0
#define CLK_RST_CONTROLLER81_LAST_REG 0x1e8034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_HOST1X_0
#define CLK_RST_CONTROLLER82_FIRST_REG 0x1ef000 // CLK_RST_CONTROLLER_HOST1X_SCR_FUNC_0
#define CLK_RST_CONTROLLER82_LAST_REG 0x1ef004 // CLK_RST_CONTROLLER_HOST1X_SCR_FMON_0
#define CLK_RST_CONTROLLER83_FIRST_REG 0x200000 // CLK_RST_CONTROLLER_RST_DEV_EMC_0
#define CLK_RST_CONTROLLER83_LAST_REG 0x200008 // CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0
#define CLK_RST_CONTROLLER84_FIRST_REG 0x201000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0
#define CLK_RST_CONTROLLER84_LAST_REG 0x201008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0
#define CLK_RST_CONTROLLER85_FIRST_REG 0x202000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0
#define CLK_RST_CONTROLLER85_LAST_REG 0x202000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0
#define CLK_RST_CONTROLLER86_FIRST_REG 0x203000 // CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0
#define CLK_RST_CONTROLLER86_LAST_REG 0x203014 // CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0
#define CLK_RST_CONTROLLER87_FIRST_REG 0x204000 // CLK_RST_CONTROLLER_CLK_SPARE_EMC_0
#define CLK_RST_CONTROLLER87_LAST_REG 0x204000 // CLK_RST_CONTROLLER_CLK_SPARE_EMC_0
#define CLK_RST_CONTROLLER88_FIRST_REG 0x208000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMC_CDB_0
#define CLK_RST_CONTROLLER88_LAST_REG 0x208034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMC_CDB_0
#define CLK_RST_CONTROLLER89_FIRST_REG 0x20f000 // CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FUNC_0
#define CLK_RST_CONTROLLER89_LAST_REG 0x20f008 // CLK_RST_CONTROLLER_EMC_SCR_EMC_CDB_FMON_0
#define CLK_RST_CONTROLLER90_FIRST_REG 0x220000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0
#define CLK_RST_CONTROLLER90_LAST_REG 0x220008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0
#define CLK_RST_CONTROLLER91_FIRST_REG 0x221000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0
#define CLK_RST_CONTROLLER91_LAST_REG 0x221000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0
#define CLK_RST_CONTROLLER92_FIRST_REG 0x222000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0
#define CLK_RST_CONTROLLER92_LAST_REG 0x222000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0
#define CLK_RST_CONTROLLER93_FIRST_REG 0x240000 // CLK_RST_CONTROLLER_RST_DEV_I2C3_0
#define CLK_RST_CONTROLLER93_LAST_REG 0x240008 // CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0
#define CLK_RST_CONTROLLER94_FIRST_REG 0x241000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0
#define CLK_RST_CONTROLLER94_LAST_REG 0x241008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0
#define CLK_RST_CONTROLLER95_FIRST_REG 0x242000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0
#define CLK_RST_CONTROLLER95_LAST_REG 0x242000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0
#define CLK_RST_CONTROLLER96_FIRST_REG 0x243000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0
#define CLK_RST_CONTROLLER96_LAST_REG 0x243000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0
#define CLK_RST_CONTROLLER97_FIRST_REG 0x248000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C3_0
#define CLK_RST_CONTROLLER97_LAST_REG 0x248034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C3_0
#define CLK_RST_CONTROLLER98_FIRST_REG 0x24f000 // CLK_RST_CONTROLLER_I2C3_SCR_FUNC_0
#define CLK_RST_CONTROLLER98_LAST_REG 0x24f004 // CLK_RST_CONTROLLER_I2C3_SCR_FMON_0
#define CLK_RST_CONTROLLER99_FIRST_REG 0x250000 // CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0
#define CLK_RST_CONTROLLER99_LAST_REG 0x250008 // CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0
#define CLK_RST_CONTROLLER100_FIRST_REG 0x251000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0
#define CLK_RST_CONTROLLER100_LAST_REG 0x251008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0
#define CLK_RST_CONTROLLER101_FIRST_REG 0x252000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0
#define CLK_RST_CONTROLLER101_LAST_REG 0x252000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0
#define CLK_RST_CONTROLLER102_FIRST_REG 0x253000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0
#define CLK_RST_CONTROLLER102_LAST_REG 0x253000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0
#define CLK_RST_CONTROLLER103_FIRST_REG 0x260000 // CLK_RST_CONTROLLER_RST_DEV_UARTD_0
#define CLK_RST_CONTROLLER103_LAST_REG 0x260008 // CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0
#define CLK_RST_CONTROLLER104_FIRST_REG 0x261000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0
#define CLK_RST_CONTROLLER104_LAST_REG 0x261008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0
#define CLK_RST_CONTROLLER105_FIRST_REG 0x262000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0
#define CLK_RST_CONTROLLER105_LAST_REG 0x262000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0
#define CLK_RST_CONTROLLER106_FIRST_REG 0x263000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0
#define CLK_RST_CONTROLLER106_LAST_REG 0x263000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0
#define CLK_RST_CONTROLLER107_FIRST_REG 0x280000 // CLK_RST_CONTROLLER_RST_DEV_CSITE_0
#define CLK_RST_CONTROLLER107_LAST_REG 0x280008 // CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0
#define CLK_RST_CONTROLLER108_FIRST_REG 0x281000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0
#define CLK_RST_CONTROLLER108_LAST_REG 0x281008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0
#define CLK_RST_CONTROLLER109_FIRST_REG 0x282000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0
#define CLK_RST_CONTROLLER109_LAST_REG 0x282000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0
#define CLK_RST_CONTROLLER110_FIRST_REG 0x283000 // CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0
#define CLK_RST_CONTROLLER110_LAST_REG 0x283000 // CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0
#define CLK_RST_CONTROLLER111_FIRST_REG 0x290000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0
#define CLK_RST_CONTROLLER111_LAST_REG 0x290008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0
#define CLK_RST_CONTROLLER112_FIRST_REG 0x291000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0
#define CLK_RST_CONTROLLER112_LAST_REG 0x291000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0
#define CLK_RST_CONTROLLER113_FIRST_REG 0x292000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0
#define CLK_RST_CONTROLLER113_LAST_REG 0x292004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0
#define CLK_RST_CONTROLLER114_FIRST_REG 0x2b0000 // CLK_RST_CONTROLLER_RST_DEV_TSEC_0
#define CLK_RST_CONTROLLER114_LAST_REG 0x2b0008 // CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0
#define CLK_RST_CONTROLLER115_FIRST_REG 0x2b1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0
#define CLK_RST_CONTROLLER115_LAST_REG 0x2b1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0
#define CLK_RST_CONTROLLER116_FIRST_REG 0x2b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0
#define CLK_RST_CONTROLLER116_LAST_REG 0x2b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0
#define CLK_RST_CONTROLLER117_FIRST_REG 0x2b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0
#define CLK_RST_CONTROLLER117_LAST_REG 0x2b3004 // CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER118_FIRST_REG 0x2c0000 // CLK_RST_CONTROLLER_RST_DEV_LA_0
#define CLK_RST_CONTROLLER118_LAST_REG 0x2c0008 // CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0
#define CLK_RST_CONTROLLER119_FIRST_REG 0x2c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0
#define CLK_RST_CONTROLLER119_LAST_REG 0x2c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0
#define CLK_RST_CONTROLLER120_FIRST_REG 0x2c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0
#define CLK_RST_CONTROLLER120_LAST_REG 0x2c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0
#define CLK_RST_CONTROLLER121_FIRST_REG 0x2c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_LA_0
#define CLK_RST_CONTROLLER121_LAST_REG 0x2c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_LA_0
#define CLK_RST_CONTROLLER122_FIRST_REG 0x300000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0
#define CLK_RST_CONTROLLER122_LAST_REG 0x300008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0
#define CLK_RST_CONTROLLER123_FIRST_REG 0x301000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0
#define CLK_RST_CONTROLLER123_LAST_REG 0x301000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0
#define CLK_RST_CONTROLLER124_FIRST_REG 0x302000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0
#define CLK_RST_CONTROLLER124_LAST_REG 0x302004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0
#define CLK_RST_CONTROLLER125_FIRST_REG 0x310000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0
#define CLK_RST_CONTROLLER125_LAST_REG 0x310008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0
#define CLK_RST_CONTROLLER126_FIRST_REG 0x311000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0
#define CLK_RST_CONTROLLER126_LAST_REG 0x311000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0
#define CLK_RST_CONTROLLER127_FIRST_REG 0x312000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0
#define CLK_RST_CONTROLLER127_LAST_REG 0x312004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0
#define CLK_RST_CONTROLLER128_FIRST_REG 0x320000 // CLK_RST_CONTROLLER_RST_DEV_I2C4_0
#define CLK_RST_CONTROLLER128_LAST_REG 0x320008 // CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0
#define CLK_RST_CONTROLLER129_FIRST_REG 0x321000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0
#define CLK_RST_CONTROLLER129_LAST_REG 0x321008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0
#define CLK_RST_CONTROLLER130_FIRST_REG 0x322000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0
#define CLK_RST_CONTROLLER130_LAST_REG 0x322000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0
#define CLK_RST_CONTROLLER131_FIRST_REG 0x323000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0
#define CLK_RST_CONTROLLER131_LAST_REG 0x323000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0
#define CLK_RST_CONTROLLER132_FIRST_REG 0x328000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C4_0
#define CLK_RST_CONTROLLER132_LAST_REG 0x328034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C4_0
#define CLK_RST_CONTROLLER133_FIRST_REG 0x32f000 // CLK_RST_CONTROLLER_I2C4_SCR_FUNC_0
#define CLK_RST_CONTROLLER133_LAST_REG 0x32f004 // CLK_RST_CONTROLLER_I2C4_SCR_FMON_0
#define CLK_RST_CONTROLLER134_FIRST_REG 0x330000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0
#define CLK_RST_CONTROLLER134_LAST_REG 0x330008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0
#define CLK_RST_CONTROLLER135_FIRST_REG 0x331000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0
#define CLK_RST_CONTROLLER135_LAST_REG 0x331000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0
#define CLK_RST_CONTROLLER136_FIRST_REG 0x332000 // CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0
#define CLK_RST_CONTROLLER136_LAST_REG 0x332000 // CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0
#define CLK_RST_CONTROLLER137_FIRST_REG 0x340000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER137_LAST_REG 0x340008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0
#define CLK_RST_CONTROLLER138_FIRST_REG 0x341000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER138_LAST_REG 0x341000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER139_FIRST_REG 0x342000 // CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER139_LAST_REG 0x342000 // CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER140_FIRST_REG 0x360000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0
#define CLK_RST_CONTROLLER140_LAST_REG 0x360008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0
#define CLK_RST_CONTROLLER141_FIRST_REG 0x361000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0
#define CLK_RST_CONTROLLER141_LAST_REG 0x361000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0
#define CLK_RST_CONTROLLER142_FIRST_REG 0x362000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0
#define CLK_RST_CONTROLLER142_LAST_REG 0x362000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0
#define CLK_RST_CONTROLLER143_FIRST_REG 0x370000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0
#define CLK_RST_CONTROLLER143_LAST_REG 0x370008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0
#define CLK_RST_CONTROLLER144_FIRST_REG 0x371000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0
#define CLK_RST_CONTROLLER144_LAST_REG 0x371000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0
#define CLK_RST_CONTROLLER145_FIRST_REG 0x372000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0
#define CLK_RST_CONTROLLER145_LAST_REG 0x372000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0
#define CLK_RST_CONTROLLER146_FIRST_REG 0x380000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0
#define CLK_RST_CONTROLLER146_LAST_REG 0x380008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0
#define CLK_RST_CONTROLLER147_FIRST_REG 0x381000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0
#define CLK_RST_CONTROLLER147_LAST_REG 0x381000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0
#define CLK_RST_CONTROLLER148_FIRST_REG 0x382000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0
#define CLK_RST_CONTROLLER148_LAST_REG 0x382000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0
#define CLK_RST_CONTROLLER149_FIRST_REG 0x390000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0
#define CLK_RST_CONTROLLER149_LAST_REG 0x390008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0
#define CLK_RST_CONTROLLER150_FIRST_REG 0x391000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0
#define CLK_RST_CONTROLLER150_LAST_REG 0x391000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0
#define CLK_RST_CONTROLLER151_FIRST_REG 0x392000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0
#define CLK_RST_CONTROLLER151_LAST_REG 0x392000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0
#define CLK_RST_CONTROLLER152_FIRST_REG 0x398000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C_SLOW_0
#define CLK_RST_CONTROLLER152_LAST_REG 0x398034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C_SLOW_0
#define CLK_RST_CONTROLLER153_FIRST_REG 0x39f000 // CLK_RST_CONTROLLER_I2C_SLOW_SCR_FUNC_0
#define CLK_RST_CONTROLLER153_LAST_REG 0x39f004 // CLK_RST_CONTROLLER_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER154_FIRST_REG 0x3a0000 // CLK_RST_CONTROLLER_RST_DEV_SOR1_0
#define CLK_RST_CONTROLLER154_LAST_REG 0x3a0008 // CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0
#define CLK_RST_CONTROLLER155_FIRST_REG 0x3a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0
#define CLK_RST_CONTROLLER155_LAST_REG 0x3a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0
#define CLK_RST_CONTROLLER156_FIRST_REG 0x3a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0
#define CLK_RST_CONTROLLER156_LAST_REG 0x3a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0
#define CLK_RST_CONTROLLER157_FIRST_REG 0x3a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0
#define CLK_RST_CONTROLLER157_LAST_REG 0x3a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0
#define CLK_RST_CONTROLLER158_FIRST_REG 0x3a8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR1_0
#define CLK_RST_CONTROLLER158_LAST_REG 0x3a8034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR1_0
#define CLK_RST_CONTROLLER159_FIRST_REG 0x3af000 // CLK_RST_CONTROLLER_SOR1_SCR_FUNC_0
#define CLK_RST_CONTROLLER159_LAST_REG 0x3af004 // CLK_RST_CONTROLLER_SOR1_SCR_FMON_0
#define CLK_RST_CONTROLLER160_FIRST_REG 0x1210000 // CLK_RST_CONTROLLER_RST_DEV_SOR2_0
#define CLK_RST_CONTROLLER160_LAST_REG 0x1210008 // CLK_RST_CONTROLLER_RST_DEV_SOR2_CLR_0
#define CLK_RST_CONTROLLER161_FIRST_REG 0x1211000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_0
#define CLK_RST_CONTROLLER161_LAST_REG 0x1211008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR2_CLR_0
#define CLK_RST_CONTROLLER162_FIRST_REG 0x1212000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0
#define CLK_RST_CONTROLLER162_LAST_REG 0x1212000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR2_0
#define CLK_RST_CONTROLLER163_FIRST_REG 0x1213000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0
#define CLK_RST_CONTROLLER163_LAST_REG 0x1213000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR2_0
#define CLK_RST_CONTROLLER164_FIRST_REG 0x1218000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR2_0
#define CLK_RST_CONTROLLER164_LAST_REG 0x1218034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR2_0
#define CLK_RST_CONTROLLER165_FIRST_REG 0x121f000 // CLK_RST_CONTROLLER_SOR2_SCR_FUNC_0
#define CLK_RST_CONTROLLER165_LAST_REG 0x121f004 // CLK_RST_CONTROLLER_SOR2_SCR_FMON_0
#define CLK_RST_CONTROLLER166_FIRST_REG 0x1220000 // CLK_RST_CONTROLLER_RST_DEV_SOR3_0
#define CLK_RST_CONTROLLER166_LAST_REG 0x1220008 // CLK_RST_CONTROLLER_RST_DEV_SOR3_CLR_0
#define CLK_RST_CONTROLLER167_FIRST_REG 0x1221000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_0
#define CLK_RST_CONTROLLER167_LAST_REG 0x1221008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR3_CLR_0
#define CLK_RST_CONTROLLER168_FIRST_REG 0x1222000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0
#define CLK_RST_CONTROLLER168_LAST_REG 0x1222000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR3_0
#define CLK_RST_CONTROLLER169_FIRST_REG 0x1223000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0
#define CLK_RST_CONTROLLER169_LAST_REG 0x1223000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR3_0
#define CLK_RST_CONTROLLER170_FIRST_REG 0x1228000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR3_0
#define CLK_RST_CONTROLLER170_LAST_REG 0x1228034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR3_0
#define CLK_RST_CONTROLLER171_FIRST_REG 0x122f000 // CLK_RST_CONTROLLER_SOR3_SCR_FUNC_0
#define CLK_RST_CONTROLLER171_LAST_REG 0x122f004 // CLK_RST_CONTROLLER_SOR3_SCR_FMON_0
#define CLK_RST_CONTROLLER172_FIRST_REG 0x3b0000 // CLK_RST_CONTROLLER_RST_DEV_SOR0_0
#define CLK_RST_CONTROLLER172_LAST_REG 0x3b0044 // CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0
#define CLK_RST_CONTROLLER173_FIRST_REG 0x3b1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0
#define CLK_RST_CONTROLLER173_LAST_REG 0x3b1044 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0
#define CLK_RST_CONTROLLER174_FIRST_REG 0x3b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0
#define CLK_RST_CONTROLLER174_LAST_REG 0x3b2014 // CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0
#define CLK_RST_CONTROLLER175_FIRST_REG 0x3b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0
#define CLK_RST_CONTROLLER175_LAST_REG 0x3b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0
#define CLK_RST_CONTROLLER176_FIRST_REG 0x3b4000 // CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0
#define CLK_RST_CONTROLLER176_LAST_REG 0x3b4000 // CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0
#define CLK_RST_CONTROLLER177_FIRST_REG 0x3b8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SOR0_0
#define CLK_RST_CONTROLLER177_LAST_REG 0x3b806c // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SOR_SAFE_0
#define CLK_RST_CONTROLLER178_FIRST_REG 0x3bf000 // CLK_RST_CONTROLLER_SOR0_SCR_FUNC_0
#define CLK_RST_CONTROLLER178_LAST_REG 0x3bf008 // CLK_RST_CONTROLLER_SOR_SAFE_SCR_FMON_0
#define CLK_RST_CONTROLLER179_FIRST_REG 0x3c0000 // CLK_RST_CONTROLLER_RST_DEV_SATA_0
#define CLK_RST_CONTROLLER179_LAST_REG 0x3c0008 // CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0
#define CLK_RST_CONTROLLER180_FIRST_REG 0x3c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0
#define CLK_RST_CONTROLLER180_LAST_REG 0x3c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0
#define CLK_RST_CONTROLLER181_FIRST_REG 0x3c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0
#define CLK_RST_CONTROLLER181_LAST_REG 0x3c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0
#define CLK_RST_CONTROLLER182_FIRST_REG 0x3c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0
#define CLK_RST_CONTROLLER182_LAST_REG 0x3c3004 // CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0
#define CLK_RST_CONTROLLER183_FIRST_REG 0x3c4000 // CLK_RST_CONTROLLER_CLK_SPARE_SATA_0
#define CLK_RST_CONTROLLER183_LAST_REG 0x3c4000 // CLK_RST_CONTROLLER_CLK_SPARE_SATA_0
#define CLK_RST_CONTROLLER184_FIRST_REG 0x3d0000 // CLK_RST_CONTROLLER_RST_DEV_HDA_0
#define CLK_RST_CONTROLLER184_LAST_REG 0x3d0008 // CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0
#define CLK_RST_CONTROLLER185_FIRST_REG 0x3d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0
#define CLK_RST_CONTROLLER185_LAST_REG 0x3d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0
#define CLK_RST_CONTROLLER186_FIRST_REG 0x3d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0
#define CLK_RST_CONTROLLER186_LAST_REG 0x3d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0
#define CLK_RST_CONTROLLER187_FIRST_REG 0x3d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0
#define CLK_RST_CONTROLLER187_LAST_REG 0x3d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0
#define CLK_RST_CONTROLLER188_FIRST_REG 0x3e0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0
#define CLK_RST_CONTROLLER188_LAST_REG 0x3e0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0
#define CLK_RST_CONTROLLER189_FIRST_REG 0x3e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0
#define CLK_RST_CONTROLLER189_LAST_REG 0x3e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0
#define CLK_RST_CONTROLLER190_FIRST_REG 0x3e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_SE_0
#define CLK_RST_CONTROLLER190_LAST_REG 0x3e2004 // CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER191_FIRST_REG 0x3f0000 // CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0
#define CLK_RST_CONTROLLER191_LAST_REG 0x3f0014 // CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0
#define CLK_RST_CONTROLLER192_FIRST_REG 0x400000 // CLK_RST_CONTROLLER_RST_DEV_APE_0
#define CLK_RST_CONTROLLER192_LAST_REG 0x400008 // CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0
#define CLK_RST_CONTROLLER193_FIRST_REG 0x401000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0
#define CLK_RST_CONTROLLER193_LAST_REG 0x40102c // CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0
#define CLK_RST_CONTROLLER194_FIRST_REG 0x402000 // CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0
#define CLK_RST_CONTROLLER194_LAST_REG 0x40200c // CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0
#define CLK_RST_CONTROLLER195_FIRST_REG 0x403000 // CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0
#define CLK_RST_CONTROLLER195_LAST_REG 0x403008 // CLK_RST_CONTROLLER_CLK_SOURCE_APE_0
#define CLK_RST_CONTROLLER196_FIRST_REG 0x410000 // CLK_RST_CONTROLLER_PLLD2_BASE_0
#define CLK_RST_CONTROLLER196_LAST_REG 0x410018 // CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0
#define CLK_RST_CONTROLLER197_FIRST_REG 0x420000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0
#define CLK_RST_CONTROLLER197_LAST_REG 0x42001c // CLK_RST_CONTROLLER_PLLREFE_MISC2_0
#define CLK_RST_CONTROLLER198_FIRST_REG 0x421000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0
#define CLK_RST_CONTROLLER198_LAST_REG 0x421000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0
#define CLK_RST_CONTROLLER199_FIRST_REG 0x430000 // CLK_RST_CONTROLLER_PLLC2_BASE_0
#define CLK_RST_CONTROLLER199_LAST_REG 0x430014 // CLK_RST_CONTROLLER_PLLC2_MISC_4_0
#define CLK_RST_CONTROLLER200_FIRST_REG 0x440000 // CLK_RST_CONTROLLER_PLLC3_BASE_0
#define CLK_RST_CONTROLLER200_LAST_REG 0x440014 // CLK_RST_CONTROLLER_PLLC3_MISC_4_0
#define CLK_RST_CONTROLLER201_FIRST_REG 0x12a0000 // CLK_RST_CONTROLLER_PLLCV_BASE_0
#define CLK_RST_CONTROLLER201_LAST_REG 0x12a0024 // CLK_RST_CONTROLLER_PLLCV_SS_CTRL2_0
#define CLK_RST_CONTROLLER202_FIRST_REG 0x12b0000 // CLK_RST_CONTROLLER_PLLCV2_BASE_0
#define CLK_RST_CONTROLLER202_LAST_REG 0x12b0014 // CLK_RST_CONTROLLER_PLLCV2_MISC_4_0
#define CLK_RST_CONTROLLER203_FIRST_REG 0x12c0000 // CLK_RST_CONTROLLER_PLLCV3_BASE_0
#define CLK_RST_CONTROLLER203_LAST_REG 0x12c0014 // CLK_RST_CONTROLLER_PLLCV3_MISC_4_0
#define CLK_RST_CONTROLLER204_FIRST_REG 0x450000 // CLK_RST_CONTROLLER_PLLDP_BASE_0
#define CLK_RST_CONTROLLER204_LAST_REG 0x450018 // CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0
#define CLK_RST_CONTROLLER205_FIRST_REG 0x460000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0
#define CLK_RST_CONTROLLER205_LAST_REG 0x460020 // CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0
#define CLK_RST_CONTROLLER206_FIRST_REG 0x461000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0
#define CLK_RST_CONTROLLER206_LAST_REG 0x461000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0
#define CLK_RST_CONTROLLER207_FIRST_REG 0x470000 // CLK_RST_CONTROLLER_RST_DEV_XUSB_0
#define CLK_RST_CONTROLLER207_LAST_REG 0x470008 // CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0
#define CLK_RST_CONTROLLER208_FIRST_REG 0x471000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0
#define CLK_RST_CONTROLLER208_LAST_REG 0x471008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0
#define CLK_RST_CONTROLLER209_FIRST_REG 0x472000 // CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0
#define CLK_RST_CONTROLLER209_LAST_REG 0x472000 // CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0
#define CLK_RST_CONTROLLER210_FIRST_REG 0x473000 // CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0
#define CLK_RST_CONTROLLER210_LAST_REG 0x473010 // CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0
#define CLK_RST_CONTROLLER211_FIRST_REG 0x474000 // CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0
#define CLK_RST_CONTROLLER211_LAST_REG 0x474000 // CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0
#define CLK_RST_CONTROLLER212_FIRST_REG 0x4d0000 // CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0
#define CLK_RST_CONTROLLER212_LAST_REG 0x4d0008 // CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0
#define CLK_RST_CONTROLLER213_FIRST_REG 0x4d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0
#define CLK_RST_CONTROLLER213_LAST_REG 0x4d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0
#define CLK_RST_CONTROLLER214_FIRST_REG 0x4d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0
#define CLK_RST_CONTROLLER214_LAST_REG 0x4d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0
#define CLK_RST_CONTROLLER215_FIRST_REG 0x4d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0
#define CLK_RST_CONTROLLER215_LAST_REG 0x4d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0
#define CLK_RST_CONTROLLER216_FIRST_REG 0x4e0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0
#define CLK_RST_CONTROLLER216_LAST_REG 0x4e0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0
#define CLK_RST_CONTROLLER217_FIRST_REG 0x4e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0
#define CLK_RST_CONTROLLER217_LAST_REG 0x4e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0
#define CLK_RST_CONTROLLER218_FIRST_REG 0x4e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0
#define CLK_RST_CONTROLLER218_LAST_REG 0x4e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0
#define CLK_RST_CONTROLLER219_FIRST_REG 0x500000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0
#define CLK_RST_CONTROLLER219_LAST_REG 0x500008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0
#define CLK_RST_CONTROLLER220_FIRST_REG 0x501000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0
#define CLK_RST_CONTROLLER220_LAST_REG 0x501000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0
#define CLK_RST_CONTROLLER221_FIRST_REG 0x502000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0
#define CLK_RST_CONTROLLER221_LAST_REG 0x502000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0
#define CLK_RST_CONTROLLER222_FIRST_REG 0x503000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0
#define CLK_RST_CONTROLLER222_LAST_REG 0x503004 // CLK_RST_CONTROLLER_CTRL_DMIC1_0
#define CLK_RST_CONTROLLER223_FIRST_REG 0x510000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0
#define CLK_RST_CONTROLLER223_LAST_REG 0x510008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0
#define CLK_RST_CONTROLLER224_FIRST_REG 0x511000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0
#define CLK_RST_CONTROLLER224_LAST_REG 0x511000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0
#define CLK_RST_CONTROLLER225_FIRST_REG 0x512000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0
#define CLK_RST_CONTROLLER225_LAST_REG 0x512000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0
#define CLK_RST_CONTROLLER226_FIRST_REG 0x513000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0
#define CLK_RST_CONTROLLER226_LAST_REG 0x513004 // CLK_RST_CONTROLLER_CTRL_DMIC2_0
#define CLK_RST_CONTROLLER227_FIRST_REG 0x520000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0
#define CLK_RST_CONTROLLER227_LAST_REG 0x520008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0
#define CLK_RST_CONTROLLER228_FIRST_REG 0x521000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0
#define CLK_RST_CONTROLLER228_LAST_REG 0x521000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0
#define CLK_RST_CONTROLLER229_FIRST_REG 0x522000 // CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0
#define CLK_RST_CONTROLLER229_LAST_REG 0x522000 // CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0
#define CLK_RST_CONTROLLER230_FIRST_REG 0x530000 // CLK_RST_CONTROLLER_RST_DEV_I2C6_0
#define CLK_RST_CONTROLLER230_LAST_REG 0x530008 // CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0
#define CLK_RST_CONTROLLER231_FIRST_REG 0x531000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0
#define CLK_RST_CONTROLLER231_LAST_REG 0x531008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0
#define CLK_RST_CONTROLLER232_FIRST_REG 0x532000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0
#define CLK_RST_CONTROLLER232_LAST_REG 0x532000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0
#define CLK_RST_CONTROLLER233_FIRST_REG 0x533000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0
#define CLK_RST_CONTROLLER233_LAST_REG 0x533000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0
#define CLK_RST_CONTROLLER234_FIRST_REG 0x538000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C6_0
#define CLK_RST_CONTROLLER234_LAST_REG 0x538034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C6_0
#define CLK_RST_CONTROLLER235_FIRST_REG 0x53f000 // CLK_RST_CONTROLLER_I2C6_SCR_FUNC_0
#define CLK_RST_CONTROLLER235_LAST_REG 0x53f004 // CLK_RST_CONTROLLER_I2C6_SCR_FMON_0
#define CLK_RST_CONTROLLER236_FIRST_REG 0x550000 // CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0
#define CLK_RST_CONTROLLER236_LAST_REG 0x550008 // CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER237_FIRST_REG 0x551000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER237_LAST_REG 0x551014 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER238_FIRST_REG 0x552000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER238_LAST_REG 0x552004 // CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0
#define CLK_RST_CONTROLLER239_FIRST_REG 0x553000 // CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER239_LAST_REG 0x553000 // CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER240_FIRST_REG 0x560000 // CLK_RST_CONTROLLER_RST_DEV_VIC_0
#define CLK_RST_CONTROLLER240_LAST_REG 0x560008 // CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0
#define CLK_RST_CONTROLLER241_FIRST_REG 0x561000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0
#define CLK_RST_CONTROLLER241_LAST_REG 0x561008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0
#define CLK_RST_CONTROLLER242_FIRST_REG 0x562000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0
#define CLK_RST_CONTROLLER242_LAST_REG 0x562000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0
#define CLK_RST_CONTROLLER243_FIRST_REG 0x563000 // CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0
#define CLK_RST_CONTROLLER243_LAST_REG 0x563004 // CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER244_FIRST_REG 0x564000 // CLK_RST_CONTROLLER_CLK_SPARE_VIC_0
#define CLK_RST_CONTROLLER244_LAST_REG 0x564000 // CLK_RST_CONTROLLER_CLK_SPARE_VIC_0
#define CLK_RST_CONTROLLER245_FIRST_REG 0x568000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_VIC_0
#define CLK_RST_CONTROLLER245_LAST_REG 0x568034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_VIC_0
#define CLK_RST_CONTROLLER246_FIRST_REG 0x56f000 // CLK_RST_CONTROLLER_VIC_SCR_FUNC_0
#define CLK_RST_CONTROLLER246_LAST_REG 0x56f004 // CLK_RST_CONTROLLER_VIC_SCR_FMON_0
#define CLK_RST_CONTROLLER247_FIRST_REG 0x570000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER247_LAST_REG 0x570008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0
#define CLK_RST_CONTROLLER248_FIRST_REG 0x571000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER248_LAST_REG 0x571000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER249_FIRST_REG 0x572000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER249_LAST_REG 0x572000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER250_FIRST_REG 0x580000 // CLK_RST_CONTROLLER_RST_DEV_NVDEC_0
#define CLK_RST_CONTROLLER250_LAST_REG 0x580008 // CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0
#define CLK_RST_CONTROLLER251_FIRST_REG 0x581000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0
#define CLK_RST_CONTROLLER251_LAST_REG 0x581008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0
#define CLK_RST_CONTROLLER252_FIRST_REG 0x582000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0
#define CLK_RST_CONTROLLER252_LAST_REG 0x582000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0
#define CLK_RST_CONTROLLER253_FIRST_REG 0x583000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0
#define CLK_RST_CONTROLLER253_LAST_REG 0x583004 // CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER254_FIRST_REG 0x584000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0
#define CLK_RST_CONTROLLER254_LAST_REG 0x584000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0
#define CLK_RST_CONTROLLER255_FIRST_REG 0x590000 // CLK_RST_CONTROLLER_RST_DEV_NVJPG_0
#define CLK_RST_CONTROLLER255_LAST_REG 0x590008 // CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0
#define CLK_RST_CONTROLLER256_FIRST_REG 0x591000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0
#define CLK_RST_CONTROLLER256_LAST_REG 0x591008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0
#define CLK_RST_CONTROLLER257_FIRST_REG 0x592000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0
#define CLK_RST_CONTROLLER257_LAST_REG 0x592000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0
#define CLK_RST_CONTROLLER258_FIRST_REG 0x593000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0
#define CLK_RST_CONTROLLER258_LAST_REG 0x593004 // CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER259_FIRST_REG 0x5a0000 // CLK_RST_CONTROLLER_RST_DEV_NVENC_0
#define CLK_RST_CONTROLLER259_LAST_REG 0x5a0008 // CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0
#define CLK_RST_CONTROLLER260_FIRST_REG 0x5a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0
#define CLK_RST_CONTROLLER260_LAST_REG 0x5a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0
#define CLK_RST_CONTROLLER261_FIRST_REG 0x5a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0
#define CLK_RST_CONTROLLER261_LAST_REG 0x5a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0
#define CLK_RST_CONTROLLER262_FIRST_REG 0x5a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0
#define CLK_RST_CONTROLLER262_LAST_REG 0x5a3004 // CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER263_FIRST_REG 0x5a4000 // CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0
#define CLK_RST_CONTROLLER263_LAST_REG 0x5a4000 // CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0
#define CLK_RST_CONTROLLER264_FIRST_REG 0x5a8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC_0
#define CLK_RST_CONTROLLER264_LAST_REG 0x5a8034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC_0
#define CLK_RST_CONTROLLER265_FIRST_REG 0x5af000 // CLK_RST_CONTROLLER_NVENC_SCR_FUNC_0
#define CLK_RST_CONTROLLER265_LAST_REG 0x5af004 // CLK_RST_CONTROLLER_NVENC_SCR_FMON_0
#define CLK_RST_CONTROLLER266_FIRST_REG 0x5b0000 // CLK_RST_CONTROLLER_PLLA1_BASE_0
#define CLK_RST_CONTROLLER266_LAST_REG 0x5b0018 // CLK_RST_CONTROLLER_PLLA1_OUT1_0
#define CLK_RST_CONTROLLER267_FIRST_REG 0x5c0000 // CLK_RST_CONTROLLER_RST_DEV_QSPI0_0
#define CLK_RST_CONTROLLER267_LAST_REG 0x5c0008 // CLK_RST_CONTROLLER_RST_DEV_QSPI0_CLR_0
#define CLK_RST_CONTROLLER268_FIRST_REG 0x5c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_0
#define CLK_RST_CONTROLLER268_LAST_REG 0x5c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI0_CLR_0
#define CLK_RST_CONTROLLER269_FIRST_REG 0x5c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0
#define CLK_RST_CONTROLLER269_LAST_REG 0x5c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI0_0
#define CLK_RST_CONTROLLER270_FIRST_REG 0x5c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0
#define CLK_RST_CONTROLLER270_LAST_REG 0x5c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0_0
#define CLK_RST_CONTROLLER271_FIRST_REG 0x5e0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER271_LAST_REG 0x5e0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0
#define CLK_RST_CONTROLLER272_FIRST_REG 0x5e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER272_LAST_REG 0x5e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER273_FIRST_REG 0x5e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER273_LAST_REG 0x5e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER274_FIRST_REG 0x5f0000 // CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0
#define CLK_RST_CONTROLLER274_LAST_REG 0x5f0010 // CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT_0
#define CLK_RST_CONTROLLER275_FIRST_REG 0x600000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0
#define CLK_RST_CONTROLLER275_LAST_REG 0x600008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0
#define CLK_RST_CONTROLLER276_FIRST_REG 0x601000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0
#define CLK_RST_CONTROLLER276_LAST_REG 0x601000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0
#define CLK_RST_CONTROLLER277_FIRST_REG 0x602000 // CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0
#define CLK_RST_CONTROLLER277_LAST_REG 0x602000 // CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0
#define CLK_RST_CONTROLLER278_FIRST_REG 0x610000 // CLK_RST_CONTROLLER_RST_DEV_TSECB_0
#define CLK_RST_CONTROLLER278_LAST_REG 0x610008 // CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0
#define CLK_RST_CONTROLLER279_FIRST_REG 0x611000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0
#define CLK_RST_CONTROLLER279_LAST_REG 0x611008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0
#define CLK_RST_CONTROLLER280_FIRST_REG 0x612000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0
#define CLK_RST_CONTROLLER280_LAST_REG 0x612000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0
#define CLK_RST_CONTROLLER281_FIRST_REG 0x613000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0
#define CLK_RST_CONTROLLER281_LAST_REG 0x613004 // CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER282_FIRST_REG 0x614000 // CLK_RST_CONTROLLER_STRAP_TSECB_0
#define CLK_RST_CONTROLLER282_LAST_REG 0x614000 // CLK_RST_CONTROLLER_STRAP_TSECB_0
#define CLK_RST_CONTROLLER283_FIRST_REG 0x620000 // CLK_RST_CONTROLLER_RST_DEV_ADSP_0
#define CLK_RST_CONTROLLER283_LAST_REG 0x620008 // CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0
#define CLK_RST_CONTROLLER284_FIRST_REG 0x621000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0
#define CLK_RST_CONTROLLER284_LAST_REG 0x621008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0
#define CLK_RST_CONTROLLER285_FIRST_REG 0x622000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0
#define CLK_RST_CONTROLLER285_LAST_REG 0x622000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0
#define CLK_RST_CONTROLLER286_FIRST_REG 0x623000 // CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0
#define CLK_RST_CONTROLLER286_LAST_REG 0x623004 // CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0
#define CLK_RST_CONTROLLER287_FIRST_REG 0x650000 // CLK_RST_CONTROLLER_RST_DEV_MPHY_0
#define CLK_RST_CONTROLLER287_LAST_REG 0x650008 // CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0
#define CLK_RST_CONTROLLER288_FIRST_REG 0x651000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0
#define CLK_RST_CONTROLLER288_LAST_REG 0x651008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0
#define CLK_RST_CONTROLLER289_FIRST_REG 0x652000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0
#define CLK_RST_CONTROLLER289_LAST_REG 0x652000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0
#define CLK_RST_CONTROLLER290_FIRST_REG 0x653000 // CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0
#define CLK_RST_CONTROLLER290_LAST_REG 0x653010 // CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0
#define CLK_RST_CONTROLLER291_FIRST_REG 0x654000 // CLK_RST_CONTROLLER_CLK_MPHY_MISC_0
#define CLK_RST_CONTROLLER291_LAST_REG 0x654000 // CLK_RST_CONTROLLER_CLK_MPHY_MISC_0
#define CLK_RST_CONTROLLER292_FIRST_REG 0x655000 // CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0
#define CLK_RST_CONTROLLER292_LAST_REG 0x655000 // CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0
#define CLK_RST_CONTROLLER293_FIRST_REG 0x656000 // CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0
#define CLK_RST_CONTROLLER293_LAST_REG 0x656000 // CLK_RST_CONTROLLER_MPHY_TX_CLK_CTRL_0
#define CLK_RST_CONTROLLER294_FIRST_REG 0x657000 // CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0
#define CLK_RST_CONTROLLER294_LAST_REG 0x657000 // CLK_RST_CONTROLLER_MPHY_RX_CLK_CTRL_0
#define CLK_RST_CONTROLLER295_FIRST_REG 0x660000 // CLK_RST_CONTROLLER_PLLNVCSI_BASE_0
#define CLK_RST_CONTROLLER295_LAST_REG 0x660014 // CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0
#define CLK_RST_CONTROLLER296_FIRST_REG 0x670000 // CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0
#define CLK_RST_CONTROLLER296_LAST_REG 0x670014 // CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0
#define CLK_RST_CONTROLLER297_FIRST_REG 0x680000 // CLK_RST_CONTROLLER_PLLD3_BASE_0
#define CLK_RST_CONTROLLER297_LAST_REG 0x680018 // CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0
#define CLK_RST_CONTROLLER298_FIRST_REG 0x1200000 // CLK_RST_CONTROLLER_PLLD4_BASE_0
#define CLK_RST_CONTROLLER298_LAST_REG 0x1200018 // CLK_RST_CONTROLLER_PLLD4_SS_CTRL2_0
#define CLK_RST_CONTROLLER299_FIRST_REG 0x690000 // CLK_RST_CONTROLLER_PLLMSB_BASE_0
#define CLK_RST_CONTROLLER299_LAST_REG 0x690028 // CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0
#define CLK_RST_CONTROLLER300_FIRST_REG 0x6a0000 // CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0
#define CLK_RST_CONTROLLER300_LAST_REG 0x6a0008 // CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0
#define CLK_RST_CONTROLLER301_FIRST_REG 0x6a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0
#define CLK_RST_CONTROLLER301_LAST_REG 0x6a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0
#define CLK_RST_CONTROLLER302_FIRST_REG 0x6a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0
#define CLK_RST_CONTROLLER302_LAST_REG 0x6a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0
#define CLK_RST_CONTROLLER303_FIRST_REG 0x6a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0
#define CLK_RST_CONTROLLER303_LAST_REG 0x6a3008 // CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0
#define CLK_RST_CONTROLLER304_FIRST_REG 0x6a8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AXI_CBB_0
#define CLK_RST_CONTROLLER304_LAST_REG 0x6a8034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AXI_CBB_0
#define CLK_RST_CONTROLLER305_FIRST_REG 0x6af000 // CLK_RST_CONTROLLER_AXI_CBB_SCR_FUNC_0
#define CLK_RST_CONTROLLER305_LAST_REG 0x6af004 // CLK_RST_CONTROLLER_AXI_CBB_SCR_FMON_0
#define CLK_RST_CONTROLLER306_FIRST_REG 0x6b0000 // CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER306_LAST_REG 0x6b0000 // CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER307_FIRST_REG 0x730000 // CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER307_LAST_REG 0x730000 // CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER308_FIRST_REG 0x740000 // CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER308_LAST_REG 0x740000 // CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER309_FIRST_REG 0x750000 // CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER309_LAST_REG 0x750000 // CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER310_FIRST_REG 0x760000 // CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER310_LAST_REG 0x760000 // CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER311_FIRST_REG 0x770000 // CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER311_LAST_REG 0x770000 // CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER312_FIRST_REG 0x7b0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0
#define CLK_RST_CONTROLLER312_LAST_REG 0x7b0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0
#define CLK_RST_CONTROLLER313_FIRST_REG 0x7b1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0
#define CLK_RST_CONTROLLER313_LAST_REG 0x7b1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0
#define CLK_RST_CONTROLLER314_FIRST_REG 0x7b2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0
#define CLK_RST_CONTROLLER314_LAST_REG 0x7b2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0
#define CLK_RST_CONTROLLER315_FIRST_REG 0x7b3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0
#define CLK_RST_CONTROLLER315_LAST_REG 0x7b3004 // CLK_RST_CONTROLLER_CTRL_DMIC3_0
#define CLK_RST_CONTROLLER316_FIRST_REG 0x7c0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0
#define CLK_RST_CONTROLLER316_LAST_REG 0x7c0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0
#define CLK_RST_CONTROLLER317_FIRST_REG 0x7c1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0
#define CLK_RST_CONTROLLER317_LAST_REG 0x7c1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0
#define CLK_RST_CONTROLLER318_FIRST_REG 0x7c2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0
#define CLK_RST_CONTROLLER318_LAST_REG 0x7c2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0
#define CLK_RST_CONTROLLER319_FIRST_REG 0x7c3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0
#define CLK_RST_CONTROLLER319_LAST_REG 0x7c3004 // CLK_RST_CONTROLLER_CTRL_DMIC4_0
#define CLK_RST_CONTROLLER320_FIRST_REG 0x7d0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0
#define CLK_RST_CONTROLLER320_LAST_REG 0x7d0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0
#define CLK_RST_CONTROLLER321_FIRST_REG 0x7d1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0
#define CLK_RST_CONTROLLER321_LAST_REG 0x7d1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0
#define CLK_RST_CONTROLLER322_FIRST_REG 0x7d2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0
#define CLK_RST_CONTROLLER322_LAST_REG 0x7d2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0
#define CLK_RST_CONTROLLER323_FIRST_REG 0x7d3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0
#define CLK_RST_CONTROLLER323_LAST_REG 0x7d3004 // CLK_RST_CONTROLLER_CLK_TRIM_DSPK1_0
#define CLK_RST_CONTROLLER324_FIRST_REG 0x7e0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0
#define CLK_RST_CONTROLLER324_LAST_REG 0x7e0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0
#define CLK_RST_CONTROLLER325_FIRST_REG 0x7e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0
#define CLK_RST_CONTROLLER325_LAST_REG 0x7e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0
#define CLK_RST_CONTROLLER326_FIRST_REG 0x7e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0
#define CLK_RST_CONTROLLER326_LAST_REG 0x7e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0
#define CLK_RST_CONTROLLER327_FIRST_REG 0x7e3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0
#define CLK_RST_CONTROLLER327_LAST_REG 0x7e3004 // CLK_RST_CONTROLLER_CLK_TRIM_DSPK2_0
#define CLK_RST_CONTROLLER328_FIRST_REG 0x7f0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0
#define CLK_RST_CONTROLLER328_LAST_REG 0x7f0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0
#define CLK_RST_CONTROLLER329_FIRST_REG 0x7f1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0
#define CLK_RST_CONTROLLER329_LAST_REG 0x7f1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0
#define CLK_RST_CONTROLLER330_FIRST_REG 0x7f2000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0
#define CLK_RST_CONTROLLER330_LAST_REG 0x7f2004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0
#define CLK_RST_CONTROLLER331_FIRST_REG 0x800000 // CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0
#define CLK_RST_CONTROLLER331_LAST_REG 0x800008 // CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0
#define CLK_RST_CONTROLLER332_FIRST_REG 0x801000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0
#define CLK_RST_CONTROLLER332_LAST_REG 0x801008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0
#define CLK_RST_CONTROLLER333_FIRST_REG 0x802000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0
#define CLK_RST_CONTROLLER333_LAST_REG 0x802000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0
#define CLK_RST_CONTROLLER334_FIRST_REG 0x803000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0
#define CLK_RST_CONTROLLER334_LAST_REG 0x803000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0
#define CLK_RST_CONTROLLER335_FIRST_REG 0x804000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0
#define CLK_RST_CONTROLLER335_LAST_REG 0x804000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0
#define CLK_RST_CONTROLLER336_FIRST_REG 0x805000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER336_LAST_REG 0x805004 // CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER337_FIRST_REG 0x806000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0
#define CLK_RST_CONTROLLER337_LAST_REG 0x806000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0
#define CLK_RST_CONTROLLER338_FIRST_REG 0x808000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY0_0
#define CLK_RST_CONTROLLER338_LAST_REG 0x80806c // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER339_FIRST_REG 0x80f000 // CLK_RST_CONTROLLER_NVDISPLAY0_SCR_FUNC_0
#define CLK_RST_CONTROLLER339_LAST_REG 0x80f008 // CLK_RST_CONTROLLER_NVDISPLAYHUB_SCR_FMON_0
#define CLK_RST_CONTROLLER340_FIRST_REG 0x810000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0
#define CLK_RST_CONTROLLER340_LAST_REG 0x810008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0
#define CLK_RST_CONTROLLER341_FIRST_REG 0x811000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0
#define CLK_RST_CONTROLLER341_LAST_REG 0x811000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0
#define CLK_RST_CONTROLLER342_FIRST_REG 0x812000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0
#define CLK_RST_CONTROLLER342_LAST_REG 0x812000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0
#define CLK_RST_CONTROLLER343_FIRST_REG 0x818000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY1_0
#define CLK_RST_CONTROLLER343_LAST_REG 0x818034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY1_0
#define CLK_RST_CONTROLLER344_FIRST_REG 0x81f000 // CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FUNC_0
#define CLK_RST_CONTROLLER344_LAST_REG 0x81f004 // CLK_RST_CONTROLLER_NVDISPLAY1_SCR_FMON_0
#define CLK_RST_CONTROLLER345_FIRST_REG 0x820000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0
#define CLK_RST_CONTROLLER345_LAST_REG 0x820008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0
#define CLK_RST_CONTROLLER346_FIRST_REG 0x821000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0
#define CLK_RST_CONTROLLER346_LAST_REG 0x821000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0
#define CLK_RST_CONTROLLER347_FIRST_REG 0x822000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0
#define CLK_RST_CONTROLLER347_LAST_REG 0x822000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0
#define CLK_RST_CONTROLLER348_FIRST_REG 0x828000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY2_0
#define CLK_RST_CONTROLLER348_LAST_REG 0x828034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY2_0
#define CLK_RST_CONTROLLER349_FIRST_REG 0x82f000 // CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FUNC_0
#define CLK_RST_CONTROLLER349_LAST_REG 0x82f004 // CLK_RST_CONTROLLER_NVDISPLAY2_SCR_FMON_0
#define CLK_RST_CONTROLLER350_FIRST_REG 0x830000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_0
#define CLK_RST_CONTROLLER350_LAST_REG 0x830008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY3_CLR_0
#define CLK_RST_CONTROLLER351_FIRST_REG 0x831000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0
#define CLK_RST_CONTROLLER351_LAST_REG 0x831000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY3_0
#define CLK_RST_CONTROLLER352_FIRST_REG 0x832000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0
#define CLK_RST_CONTROLLER352_LAST_REG 0x832000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P3_0
#define CLK_RST_CONTROLLER353_FIRST_REG 0x838000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVDISPLAY3_0
#define CLK_RST_CONTROLLER353_LAST_REG 0x838034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVDISPLAY3_0
#define CLK_RST_CONTROLLER354_FIRST_REG 0x83f000 // CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FUNC_0
#define CLK_RST_CONTROLLER354_LAST_REG 0x83f004 // CLK_RST_CONTROLLER_NVDISPLAY3_SCR_FMON_0
#define CLK_RST_CONTROLLER355_FIRST_REG 0x840000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0
#define CLK_RST_CONTROLLER355_LAST_REG 0x840008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0
#define CLK_RST_CONTROLLER356_FIRST_REG 0x841000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0
#define CLK_RST_CONTROLLER356_LAST_REG 0x841008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0
#define CLK_RST_CONTROLLER357_FIRST_REG 0x842000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0
#define CLK_RST_CONTROLLER357_LAST_REG 0x842000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0
#define CLK_RST_CONTROLLER358_FIRST_REG 0x843000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0
#define CLK_RST_CONTROLLER358_LAST_REG 0x843000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0
#define CLK_RST_CONTROLLER359_FIRST_REG 0x850000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0
#define CLK_RST_CONTROLLER359_LAST_REG 0x850008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0
#define CLK_RST_CONTROLLER360_FIRST_REG 0x851000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0
#define CLK_RST_CONTROLLER360_LAST_REG 0x851008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0
#define CLK_RST_CONTROLLER361_FIRST_REG 0x852000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0
#define CLK_RST_CONTROLLER361_LAST_REG 0x852000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0
#define CLK_RST_CONTROLLER362_FIRST_REG 0x853000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0
#define CLK_RST_CONTROLLER362_LAST_REG 0x853000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0
#define CLK_RST_CONTROLLER363_FIRST_REG 0x860000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0
#define CLK_RST_CONTROLLER363_LAST_REG 0x860008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0
#define CLK_RST_CONTROLLER364_FIRST_REG 0x861000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0
#define CLK_RST_CONTROLLER364_LAST_REG 0x861008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0
#define CLK_RST_CONTROLLER365_FIRST_REG 0x862000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0
#define CLK_RST_CONTROLLER365_LAST_REG 0x862000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0
#define CLK_RST_CONTROLLER366_FIRST_REG 0x863000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0
#define CLK_RST_CONTROLLER366_LAST_REG 0x863000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0
#define CLK_RST_CONTROLLER367_FIRST_REG 0x870000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0
#define CLK_RST_CONTROLLER367_LAST_REG 0x870008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0
#define CLK_RST_CONTROLLER368_FIRST_REG 0x871000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0
#define CLK_RST_CONTROLLER368_LAST_REG 0x871008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0
#define CLK_RST_CONTROLLER369_FIRST_REG 0x872000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0
#define CLK_RST_CONTROLLER369_LAST_REG 0x872000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0
#define CLK_RST_CONTROLLER370_FIRST_REG 0x873000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0
#define CLK_RST_CONTROLLER370_LAST_REG 0x873000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0
#define CLK_RST_CONTROLLER371_FIRST_REG 0x880000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0
#define CLK_RST_CONTROLLER371_LAST_REG 0x880008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0
#define CLK_RST_CONTROLLER372_FIRST_REG 0x881000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0
#define CLK_RST_CONTROLLER372_LAST_REG 0x881008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0
#define CLK_RST_CONTROLLER373_FIRST_REG 0x882000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0
#define CLK_RST_CONTROLLER373_LAST_REG 0x882000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0
#define CLK_RST_CONTROLLER374_FIRST_REG 0x883000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0
#define CLK_RST_CONTROLLER374_LAST_REG 0x883000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0
#define CLK_RST_CONTROLLER375_FIRST_REG 0x890000 // CLK_RST_CONTROLLER_RST_DEV_TACH_0
#define CLK_RST_CONTROLLER375_LAST_REG 0x890008 // CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0
#define CLK_RST_CONTROLLER376_FIRST_REG 0x891000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0
#define CLK_RST_CONTROLLER376_LAST_REG 0x891008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0
#define CLK_RST_CONTROLLER377_FIRST_REG 0x892000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0
#define CLK_RST_CONTROLLER377_LAST_REG 0x892000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0
#define CLK_RST_CONTROLLER378_FIRST_REG 0x893000 // CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0
#define CLK_RST_CONTROLLER378_LAST_REG 0x893000 // CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0
#define CLK_RST_CONTROLLER379_FIRST_REG 0x8a0000 // CLK_RST_CONTROLLER_RST_DEV_EQOS_0
#define CLK_RST_CONTROLLER379_LAST_REG 0x8a0008 // CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0
#define CLK_RST_CONTROLLER380_FIRST_REG 0x8a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0
#define CLK_RST_CONTROLLER380_LAST_REG 0x8a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0
#define CLK_RST_CONTROLLER381_FIRST_REG 0x8a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0
#define CLK_RST_CONTROLLER381_LAST_REG 0x8a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0
#define CLK_RST_CONTROLLER382_FIRST_REG 0x8a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0
#define CLK_RST_CONTROLLER382_LAST_REG 0x8a3008 // CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0
#define CLK_RST_CONTROLLER383_FIRST_REG 0x8a8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EQOS_TX_0
#define CLK_RST_CONTROLLER383_LAST_REG 0x8a80a4 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EQOS_PTP_0
#define CLK_RST_CONTROLLER384_FIRST_REG 0x8af000 // CLK_RST_CONTROLLER_EQOS_SCR_FUNC_0
#define CLK_RST_CONTROLLER384_LAST_REG 0x8af00c // CLK_RST_CONTROLLER_EQOS_PTP_SCR_FMON_0
#define CLK_RST_CONTROLLER385_FIRST_REG 0x8b0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0
#define CLK_RST_CONTROLLER385_LAST_REG 0x8b0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0
#define CLK_RST_CONTROLLER386_FIRST_REG 0x8b1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0
#define CLK_RST_CONTROLLER386_LAST_REG 0x8b1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0
#define CLK_RST_CONTROLLER387_FIRST_REG 0x8c0000 // CLK_RST_CONTROLLER_RST_DEV_EMCSB_0
#define CLK_RST_CONTROLLER387_LAST_REG 0x8c0008 // CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0
#define CLK_RST_CONTROLLER388_FIRST_REG 0x8c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0
#define CLK_RST_CONTROLLER388_LAST_REG 0x8c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0
#define CLK_RST_CONTROLLER389_FIRST_REG 0x8c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0
#define CLK_RST_CONTROLLER389_LAST_REG 0x8c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0
#define CLK_RST_CONTROLLER390_FIRST_REG 0x8c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0
#define CLK_RST_CONTROLLER390_LAST_REG 0x8c3014 // CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0
#define CLK_RST_CONTROLLER391_FIRST_REG 0x8c4000 // CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0
#define CLK_RST_CONTROLLER391_LAST_REG 0x8c4000 // CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0
#define CLK_RST_CONTROLLER392_FIRST_REG 0x8c8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSB_CDB_0
#define CLK_RST_CONTROLLER392_LAST_REG 0x8c8034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSB_CDB_0
#define CLK_RST_CONTROLLER393_FIRST_REG 0x8cf000 // CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FUNC_0
#define CLK_RST_CONTROLLER393_LAST_REG 0x8cf008 // CLK_RST_CONTROLLER_EMCSB_SCR_EMCSB_CDB_FMON_0
#define CLK_RST_CONTROLLER394_FIRST_REG 0x8d0000 // CLK_RST_CONTROLLER_RST_DEV_UFS_0
#define CLK_RST_CONTROLLER394_LAST_REG 0x8d0008 // CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0
#define CLK_RST_CONTROLLER395_FIRST_REG 0x8d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0
#define CLK_RST_CONTROLLER395_LAST_REG 0x8d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0
#define CLK_RST_CONTROLLER396_FIRST_REG 0x8d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0
#define CLK_RST_CONTROLLER396_LAST_REG 0x8d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0
#define CLK_RST_CONTROLLER397_FIRST_REG 0x8d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0
#define CLK_RST_CONTROLLER397_LAST_REG 0x8d3004 // CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0
#define CLK_RST_CONTROLLER398_FIRST_REG 0x8e0000 // CLK_RST_CONTROLLER_RST_DEV_NVCSI_0
#define CLK_RST_CONTROLLER398_LAST_REG 0x8e0008 // CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0
#define CLK_RST_CONTROLLER399_FIRST_REG 0x8e1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0
#define CLK_RST_CONTROLLER399_LAST_REG 0x8e1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0
#define CLK_RST_CONTROLLER400_FIRST_REG 0x8e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0
#define CLK_RST_CONTROLLER400_LAST_REG 0x8e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0
#define CLK_RST_CONTROLLER401_FIRST_REG 0x8e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0
#define CLK_RST_CONTROLLER401_LAST_REG 0x8e3008 // CLK_RST_CONTROLLER_CSI_CLK_SRC_0
#define CLK_RST_CONTROLLER402_FIRST_REG 0x8e8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVCSI_0
#define CLK_RST_CONTROLLER402_LAST_REG 0x8e806c // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVCSILP_0
#define CLK_RST_CONTROLLER403_FIRST_REG 0x8ef000 // CLK_RST_CONTROLLER_NVCSI_SCR_FUNC_0
#define CLK_RST_CONTROLLER403_LAST_REG 0x8ef008 // CLK_RST_CONTROLLER_NVCSI_SCR_NVCSILP_FMON_0
#define CLK_RST_CONTROLLER404_FIRST_REG 0x8f0000 // CLK_RST_CONTROLLER_RST_DEV_I2C7_0
#define CLK_RST_CONTROLLER404_LAST_REG 0x8f0008 // CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0
#define CLK_RST_CONTROLLER405_FIRST_REG 0x8f1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0
#define CLK_RST_CONTROLLER405_LAST_REG 0x8f1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0
#define CLK_RST_CONTROLLER406_FIRST_REG 0x8f2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0
#define CLK_RST_CONTROLLER406_LAST_REG 0x8f2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0
#define CLK_RST_CONTROLLER407_FIRST_REG 0x8f3000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0
#define CLK_RST_CONTROLLER407_LAST_REG 0x8f3000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0
#define CLK_RST_CONTROLLER408_FIRST_REG 0x8f8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C7_0
#define CLK_RST_CONTROLLER408_LAST_REG 0x8f8034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C7_0
#define CLK_RST_CONTROLLER409_FIRST_REG 0x8ff000 // CLK_RST_CONTROLLER_I2C7_SCR_FUNC_0
#define CLK_RST_CONTROLLER409_LAST_REG 0x8ff004 // CLK_RST_CONTROLLER_I2C7_SCR_FMON_0
#define CLK_RST_CONTROLLER410_FIRST_REG 0x900000 // CLK_RST_CONTROLLER_RST_DEV_I2C9_0
#define CLK_RST_CONTROLLER410_LAST_REG 0x900008 // CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0
#define CLK_RST_CONTROLLER411_FIRST_REG 0x901000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0
#define CLK_RST_CONTROLLER411_LAST_REG 0x901008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0
#define CLK_RST_CONTROLLER412_FIRST_REG 0x902000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0
#define CLK_RST_CONTROLLER412_LAST_REG 0x902000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0
#define CLK_RST_CONTROLLER413_FIRST_REG 0x903000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0
#define CLK_RST_CONTROLLER413_LAST_REG 0x903000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0
#define CLK_RST_CONTROLLER414_FIRST_REG 0x908000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C9_0
#define CLK_RST_CONTROLLER414_LAST_REG 0x908034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C9_0
#define CLK_RST_CONTROLLER415_FIRST_REG 0x90f000 // CLK_RST_CONTROLLER_I2C9_SCR_FUNC_0
#define CLK_RST_CONTROLLER415_LAST_REG 0x90f004 // CLK_RST_CONTROLLER_I2C9_SCR_FMON_0
#define CLK_RST_CONTROLLER416_FIRST_REG 0x920000 // CLK_RST_CONTROLLER_RST_DEV_I2C12_0
#define CLK_RST_CONTROLLER416_LAST_REG 0x920008 // CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0
#define CLK_RST_CONTROLLER417_FIRST_REG 0x921000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0
#define CLK_RST_CONTROLLER417_LAST_REG 0x921008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0
#define CLK_RST_CONTROLLER418_FIRST_REG 0x922000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0
#define CLK_RST_CONTROLLER418_LAST_REG 0x922000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0
#define CLK_RST_CONTROLLER419_FIRST_REG 0x923000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0
#define CLK_RST_CONTROLLER419_LAST_REG 0x923000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0
#define CLK_RST_CONTROLLER420_FIRST_REG 0x930000 // CLK_RST_CONTROLLER_RST_DEV_I2C13_0
#define CLK_RST_CONTROLLER420_LAST_REG 0x930008 // CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0
#define CLK_RST_CONTROLLER421_FIRST_REG 0x931000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0
#define CLK_RST_CONTROLLER421_LAST_REG 0x931008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0
#define CLK_RST_CONTROLLER422_FIRST_REG 0x932000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0
#define CLK_RST_CONTROLLER422_LAST_REG 0x932000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0
#define CLK_RST_CONTROLLER423_FIRST_REG 0x933000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0
#define CLK_RST_CONTROLLER423_LAST_REG 0x933000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0
#define CLK_RST_CONTROLLER424_FIRST_REG 0x940000 // CLK_RST_CONTROLLER_RST_DEV_I2C14_0
#define CLK_RST_CONTROLLER424_LAST_REG 0x940008 // CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0
#define CLK_RST_CONTROLLER425_FIRST_REG 0x941000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0
#define CLK_RST_CONTROLLER425_LAST_REG 0x941008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0
#define CLK_RST_CONTROLLER426_FIRST_REG 0x942000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0
#define CLK_RST_CONTROLLER426_LAST_REG 0x942000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0
#define CLK_RST_CONTROLLER427_FIRST_REG 0x943000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0
#define CLK_RST_CONTROLLER427_LAST_REG 0x943000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0
#define CLK_RST_CONTROLLER428_FIRST_REG 0x950000 // CLK_RST_CONTROLLER_RST_DEV_PWM1_0
#define CLK_RST_CONTROLLER428_LAST_REG 0x950008 // CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0
#define CLK_RST_CONTROLLER429_FIRST_REG 0x951000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0
#define CLK_RST_CONTROLLER429_LAST_REG 0x951008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0
#define CLK_RST_CONTROLLER430_FIRST_REG 0x952000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0
#define CLK_RST_CONTROLLER430_LAST_REG 0x952000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0
#define CLK_RST_CONTROLLER431_FIRST_REG 0x953000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0
#define CLK_RST_CONTROLLER431_LAST_REG 0x953000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0
#define CLK_RST_CONTROLLER432_FIRST_REG 0x960000 // CLK_RST_CONTROLLER_RST_DEV_PWM2_0
#define CLK_RST_CONTROLLER432_LAST_REG 0x960008 // CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0
#define CLK_RST_CONTROLLER433_FIRST_REG 0x961000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0
#define CLK_RST_CONTROLLER433_LAST_REG 0x961008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0
#define CLK_RST_CONTROLLER434_FIRST_REG 0x962000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0
#define CLK_RST_CONTROLLER434_LAST_REG 0x962000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0
#define CLK_RST_CONTROLLER435_FIRST_REG 0x963000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0
#define CLK_RST_CONTROLLER435_LAST_REG 0x963000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0
#define CLK_RST_CONTROLLER436_FIRST_REG 0x970000 // CLK_RST_CONTROLLER_RST_DEV_PWM3_0
#define CLK_RST_CONTROLLER436_LAST_REG 0x970008 // CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0
#define CLK_RST_CONTROLLER437_FIRST_REG 0x971000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0
#define CLK_RST_CONTROLLER437_LAST_REG 0x971008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0
#define CLK_RST_CONTROLLER438_FIRST_REG 0x972000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0
#define CLK_RST_CONTROLLER438_LAST_REG 0x972000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0
#define CLK_RST_CONTROLLER439_FIRST_REG 0x973000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0
#define CLK_RST_CONTROLLER439_LAST_REG 0x973000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0
#define CLK_RST_CONTROLLER440_FIRST_REG 0x990000 // CLK_RST_CONTROLLER_RST_DEV_PWM5_0
#define CLK_RST_CONTROLLER440_LAST_REG 0x990008 // CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0
#define CLK_RST_CONTROLLER441_FIRST_REG 0x991000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0
#define CLK_RST_CONTROLLER441_LAST_REG 0x991008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0
#define CLK_RST_CONTROLLER442_FIRST_REG 0x992000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0
#define CLK_RST_CONTROLLER442_LAST_REG 0x992000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0
#define CLK_RST_CONTROLLER443_FIRST_REG 0x993000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0
#define CLK_RST_CONTROLLER443_LAST_REG 0x993000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0
#define CLK_RST_CONTROLLER444_FIRST_REG 0x9a0000 // CLK_RST_CONTROLLER_RST_DEV_PWM6_0
#define CLK_RST_CONTROLLER444_LAST_REG 0x9a0008 // CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0
#define CLK_RST_CONTROLLER445_FIRST_REG 0x9a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0
#define CLK_RST_CONTROLLER445_LAST_REG 0x9a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0
#define CLK_RST_CONTROLLER446_FIRST_REG 0x9a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0
#define CLK_RST_CONTROLLER446_LAST_REG 0x9a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0
#define CLK_RST_CONTROLLER447_FIRST_REG 0x9a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0
#define CLK_RST_CONTROLLER447_LAST_REG 0x9a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0
#define CLK_RST_CONTROLLER448_FIRST_REG 0x9b0000 // CLK_RST_CONTROLLER_RST_DEV_PWM7_0
#define CLK_RST_CONTROLLER448_LAST_REG 0x9b0008 // CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0
#define CLK_RST_CONTROLLER449_FIRST_REG 0x9b1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0
#define CLK_RST_CONTROLLER449_LAST_REG 0x9b1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0
#define CLK_RST_CONTROLLER450_FIRST_REG 0x9b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0
#define CLK_RST_CONTROLLER450_LAST_REG 0x9b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0
#define CLK_RST_CONTROLLER451_FIRST_REG 0x9b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0
#define CLK_RST_CONTROLLER451_LAST_REG 0x9b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0
#define CLK_RST_CONTROLLER452_FIRST_REG 0x9c0000 // CLK_RST_CONTROLLER_RST_DEV_PWM8_0
#define CLK_RST_CONTROLLER452_LAST_REG 0x9c0008 // CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0
#define CLK_RST_CONTROLLER453_FIRST_REG 0x9c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0
#define CLK_RST_CONTROLLER453_LAST_REG 0x9c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0
#define CLK_RST_CONTROLLER454_FIRST_REG 0x9c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0
#define CLK_RST_CONTROLLER454_LAST_REG 0x9c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0
#define CLK_RST_CONTROLLER455_FIRST_REG 0x9c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0
#define CLK_RST_CONTROLLER455_LAST_REG 0x9c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0
#define CLK_RST_CONTROLLER456_FIRST_REG 0x9d0000 // CLK_RST_CONTROLLER_RST_DEV_UARTE_0
#define CLK_RST_CONTROLLER456_LAST_REG 0x9d0008 // CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0
#define CLK_RST_CONTROLLER457_FIRST_REG 0x9d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0
#define CLK_RST_CONTROLLER457_LAST_REG 0x9d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0
#define CLK_RST_CONTROLLER458_FIRST_REG 0x9d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0
#define CLK_RST_CONTROLLER458_LAST_REG 0x9d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0
#define CLK_RST_CONTROLLER459_FIRST_REG 0x9d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0
#define CLK_RST_CONTROLLER459_LAST_REG 0x9d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0
#define CLK_RST_CONTROLLER460_FIRST_REG 0x9e0000 // CLK_RST_CONTROLLER_RST_DEV_UARTF_0
#define CLK_RST_CONTROLLER460_LAST_REG 0x9e0008 // CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0
#define CLK_RST_CONTROLLER461_FIRST_REG 0x9e1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0
#define CLK_RST_CONTROLLER461_LAST_REG 0x9e1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0
#define CLK_RST_CONTROLLER462_FIRST_REG 0x9e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0
#define CLK_RST_CONTROLLER462_LAST_REG 0x9e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0
#define CLK_RST_CONTROLLER463_FIRST_REG 0x9e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0
#define CLK_RST_CONTROLLER463_LAST_REG 0x9e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0
#define CLK_RST_CONTROLLER464_FIRST_REG 0x9f0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0
#define CLK_RST_CONTROLLER464_LAST_REG 0x9f0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0
#define CLK_RST_CONTROLLER465_FIRST_REG 0x9f1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0
#define CLK_RST_CONTROLLER465_LAST_REG 0x9f1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0
#define CLK_RST_CONTROLLER466_FIRST_REG 0x9f2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0
#define CLK_RST_CONTROLLER466_LAST_REG 0x9f2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0
#define CLK_RST_CONTROLLER467_FIRST_REG 0xa00000 // CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0
#define CLK_RST_CONTROLLER467_LAST_REG 0xa00014 // CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0
#define CLK_RST_CONTROLLER468_FIRST_REG 0xa01000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0
#define CLK_RST_CONTROLLER468_LAST_REG 0xa01000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0
#define CLK_RST_CONTROLLER469_FIRST_REG 0xa10000 // CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER469_LAST_REG 0xa10050 // CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0
#define CLK_RST_CONTROLLER470_FIRST_REG 0xa11000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER470_LAST_REG 0xa11008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER471_FIRST_REG 0xa12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER471_LAST_REG 0xa12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER472_FIRST_REG 0xa13000 // CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER472_LAST_REG 0xa13008 // CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER473_FIRST_REG 0xa18000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_CPU_0
#define CLK_RST_CONTROLLER473_LAST_REG 0xa18034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_CPU_0
#define CLK_RST_CONTROLLER474_FIRST_REG 0xa20000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0
#define CLK_RST_CONTROLLER474_LAST_REG 0xa20008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0
#define CLK_RST_CONTROLLER475_FIRST_REG 0xa21000 // CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0
#define CLK_RST_CONTROLLER475_LAST_REG 0xa21000 // CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0
#define CLK_RST_CONTROLLER476_FIRST_REG 0xa22000 // CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0
#define CLK_RST_CONTROLLER476_LAST_REG 0xa22000 // CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0
#define CLK_RST_CONTROLLER477_FIRST_REG 0xa28000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_BPMP_APB_0
#define CLK_RST_CONTROLLER477_LAST_REG 0xa28034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_BPMP_APB_0
#define CLK_RST_CONTROLLER478_FIRST_REG 0xa30000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0
#define CLK_RST_CONTROLLER478_LAST_REG 0xa30008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0
#define CLK_RST_CONTROLLER479_FIRST_REG 0xa31000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0
#define CLK_RST_CONTROLLER479_LAST_REG 0xa31000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0
#define CLK_RST_CONTROLLER480_FIRST_REG 0xa32000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0
#define CLK_RST_CONTROLLER480_LAST_REG 0xa32000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0
#define CLK_RST_CONTROLLER481_FIRST_REG 0xa40000 // CLK_RST_CONTROLLER_RST_DEV_ACTMON_0
#define CLK_RST_CONTROLLER481_LAST_REG 0xa40008 // CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0
#define CLK_RST_CONTROLLER482_FIRST_REG 0xa41000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0
#define CLK_RST_CONTROLLER482_LAST_REG 0xa41008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0
#define CLK_RST_CONTROLLER483_FIRST_REG 0xa42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0
#define CLK_RST_CONTROLLER483_LAST_REG 0xa42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0
#define CLK_RST_CONTROLLER484_FIRST_REG 0xa43000 // CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0
#define CLK_RST_CONTROLLER484_LAST_REG 0xa43000 // CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0
#define CLK_RST_CONTROLLER485_FIRST_REG 0xa50000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0
#define CLK_RST_CONTROLLER485_LAST_REG 0xa50008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0
#define CLK_RST_CONTROLLER486_FIRST_REG 0xa51000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0
#define CLK_RST_CONTROLLER486_LAST_REG 0xa51000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0
#define CLK_RST_CONTROLLER487_FIRST_REG 0xa52000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0
#define CLK_RST_CONTROLLER487_LAST_REG 0xa52000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0
#define CLK_RST_CONTROLLER488_FIRST_REG 0xa60000 // CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER488_LAST_REG 0xa600a0 // CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER489_FIRST_REG 0xa70000 // CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER489_LAST_REG 0xa70024 // CLK_RST_CONTROLLER_BPMP_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER490_FIRST_REG 0xa70040 // CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER490_LAST_REG 0xa7005c // CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER491_FIRST_REG 0xa7006c // CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER491_LAST_REG 0xa70074 // CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER492_FIRST_REG 0xa7007c // CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER492_LAST_REG 0xa7007c // CLK_RST_CONTROLLER_BPMP_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER493_FIRST_REG 0xa80000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0
#define CLK_RST_CONTROLLER493_LAST_REG 0xa80008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0
#define CLK_RST_CONTROLLER494_FIRST_REG 0xa81000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0
#define CLK_RST_CONTROLLER494_LAST_REG 0xa81000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0
#define CLK_RST_CONTROLLER495_FIRST_REG 0xa82000 // CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0
#define CLK_RST_CONTROLLER495_LAST_REG 0xa82000 // CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0
#define CLK_RST_CONTROLLER496_FIRST_REG 0xae0000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0
#define CLK_RST_CONTROLLER496_LAST_REG 0xae0000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SHARED_0
#define CLK_RST_CONTROLLER497_FIRST_REG 0xae1000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0
#define CLK_RST_CONTROLLER497_LAST_REG 0xae1000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_PRIVATE_0
#define CLK_RST_CONTROLLER498_FIRST_REG 0xae2000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0
#define CLK_RST_CONTROLLER498_LAST_REG 0xae2000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_THERM_0
#define CLK_RST_CONTROLLER499_FIRST_REG 0xae3000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0
#define CLK_RST_CONTROLLER499_LAST_REG 0xae3000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_DVFS_0
#define CLK_RST_CONTROLLER500_FIRST_REG 0xae4000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0
#define CLK_RST_CONTROLLER500_LAST_REG 0xae4000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_SIMON_0
#define CLK_RST_CONTROLLER501_FIRST_REG 0xae5000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0
#define CLK_RST_CONTROLLER501_LAST_REG 0xae5000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_CPU_FMON_0
#define CLK_RST_CONTROLLER502_FIRST_REG 0xae6000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0
#define CLK_RST_CONTROLLER502_LAST_REG 0xae6000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_BPMP_APB_FMON_0
#define CLK_RST_CONTROLLER503_FIRST_REG 0xaef000 // CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER503_LAST_REG 0xaef018 // CLK_RST_CONTROLLER_BPMP_APB_SCR_FMON_0
#define CLK_RST_CONTROLLER504_FIRST_REG 0xb00000 // CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER504_LAST_REG 0xb00068 // CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0
#define CLK_RST_CONTROLLER505_FIRST_REG 0xb01000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER505_LAST_REG 0xb01008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER506_FIRST_REG 0xb02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER506_LAST_REG 0xb02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER507_FIRST_REG 0xb03000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER507_LAST_REG 0xb0300c // CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER508_FIRST_REG 0xb08000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_CPU_0
#define CLK_RST_CONTROLLER508_LAST_REG 0xb08034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_CPU_0
#define CLK_RST_CONTROLLER509_FIRST_REG 0xb10000 // CLK_RST_CONTROLLER_RST_DEV_CAN1_0
#define CLK_RST_CONTROLLER509_LAST_REG 0xb10008 // CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0
#define CLK_RST_CONTROLLER510_FIRST_REG 0xb11000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0
#define CLK_RST_CONTROLLER510_LAST_REG 0xb11008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0
#define CLK_RST_CONTROLLER511_FIRST_REG 0xb12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0
#define CLK_RST_CONTROLLER511_LAST_REG 0xb12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0
#define CLK_RST_CONTROLLER512_FIRST_REG 0xb13000 // CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0
#define CLK_RST_CONTROLLER512_LAST_REG 0xb13004 // CLK_RST_CONTROLLER_CAN1_CORE_RATE_0
#define CLK_RST_CONTROLLER513_FIRST_REG 0xb18000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN1_0
#define CLK_RST_CONTROLLER513_LAST_REG 0xb18034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN1_0
#define CLK_RST_CONTROLLER514_FIRST_REG 0xb20000 // CLK_RST_CONTROLLER_RST_DEV_CAN2_0
#define CLK_RST_CONTROLLER514_LAST_REG 0xb20008 // CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0
#define CLK_RST_CONTROLLER515_FIRST_REG 0xb21000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0
#define CLK_RST_CONTROLLER515_LAST_REG 0xb21008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0
#define CLK_RST_CONTROLLER516_FIRST_REG 0xb22000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0
#define CLK_RST_CONTROLLER516_LAST_REG 0xb22000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0
#define CLK_RST_CONTROLLER517_FIRST_REG 0xb23000 // CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0
#define CLK_RST_CONTROLLER517_LAST_REG 0xb23004 // CLK_RST_CONTROLLER_CAN2_CORE_RATE_0
#define CLK_RST_CONTROLLER518_FIRST_REG 0xb28000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CAN2_0
#define CLK_RST_CONTROLLER518_LAST_REG 0xb28034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CAN2_0
#define CLK_RST_CONTROLLER519_FIRST_REG 0xb30000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0
#define CLK_RST_CONTROLLER519_LAST_REG 0xb30008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0
#define CLK_RST_CONTROLLER520_FIRST_REG 0xb31000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0
#define CLK_RST_CONTROLLER520_LAST_REG 0xb31000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0
#define CLK_RST_CONTROLLER521_FIRST_REG 0xb32000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0
#define CLK_RST_CONTROLLER521_LAST_REG 0xb32000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0
#define CLK_RST_CONTROLLER522_FIRST_REG 0xb38000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_APB_0
#define CLK_RST_CONTROLLER522_LAST_REG 0xb38034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_APB_0
#define CLK_RST_CONTROLLER523_FIRST_REG 0xb40000 // CLK_RST_CONTROLLER_RST_DEV_UARTC_0
#define CLK_RST_CONTROLLER523_LAST_REG 0xb40008 // CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0
#define CLK_RST_CONTROLLER524_FIRST_REG 0xb41000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0
#define CLK_RST_CONTROLLER524_LAST_REG 0xb41008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0
#define CLK_RST_CONTROLLER525_FIRST_REG 0xb42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0
#define CLK_RST_CONTROLLER525_LAST_REG 0xb42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0
#define CLK_RST_CONTROLLER526_FIRST_REG 0xb43000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
#define CLK_RST_CONTROLLER526_LAST_REG 0xb43000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
#define CLK_RST_CONTROLLER527_FIRST_REG 0xb50000 // CLK_RST_CONTROLLER_RST_DEV_UARTG_0
#define CLK_RST_CONTROLLER527_LAST_REG 0xb50008 // CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0
#define CLK_RST_CONTROLLER528_FIRST_REG 0xb51000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0
#define CLK_RST_CONTROLLER528_LAST_REG 0xb51008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0
#define CLK_RST_CONTROLLER529_FIRST_REG 0xb52000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0
#define CLK_RST_CONTROLLER529_LAST_REG 0xb52000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0
#define CLK_RST_CONTROLLER530_FIRST_REG 0xb53000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0
#define CLK_RST_CONTROLLER530_LAST_REG 0xb53000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0
#define CLK_RST_CONTROLLER531_FIRST_REG 0xb60000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER531_LAST_REG 0xb60008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER532_FIRST_REG 0xb61000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER532_LAST_REG 0xb61000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER533_FIRST_REG 0xb62000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER533_LAST_REG 0xb62000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER534_FIRST_REG 0xb70000 // CLK_RST_CONTROLLER_RST_DEV_I2C2_0
#define CLK_RST_CONTROLLER534_LAST_REG 0xb70008 // CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0
#define CLK_RST_CONTROLLER535_FIRST_REG 0xb71000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0
#define CLK_RST_CONTROLLER535_LAST_REG 0xb71008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0
#define CLK_RST_CONTROLLER536_FIRST_REG 0xb72000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0
#define CLK_RST_CONTROLLER536_LAST_REG 0xb72000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0
#define CLK_RST_CONTROLLER537_FIRST_REG 0xb73000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0
#define CLK_RST_CONTROLLER537_LAST_REG 0xb73000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0
#define CLK_RST_CONTROLLER538_FIRST_REG 0xb78000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C2_0
#define CLK_RST_CONTROLLER538_LAST_REG 0xb78034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C2_0
#define CLK_RST_CONTROLLER539_FIRST_REG 0xb80000 // CLK_RST_CONTROLLER_RST_DEV_I2C8_0
#define CLK_RST_CONTROLLER539_LAST_REG 0xb80008 // CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0
#define CLK_RST_CONTROLLER540_FIRST_REG 0xb81000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0
#define CLK_RST_CONTROLLER540_LAST_REG 0xb81008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0
#define CLK_RST_CONTROLLER541_FIRST_REG 0xb82000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0
#define CLK_RST_CONTROLLER541_LAST_REG 0xb82000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0
#define CLK_RST_CONTROLLER542_FIRST_REG 0xb83000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0
#define CLK_RST_CONTROLLER542_LAST_REG 0xb83000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0
#define CLK_RST_CONTROLLER543_FIRST_REG 0xb88000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C8_0
#define CLK_RST_CONTROLLER543_LAST_REG 0xb88034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C8_0
#define CLK_RST_CONTROLLER544_FIRST_REG 0xb90000 // CLK_RST_CONTROLLER_RST_DEV_I2C10_0
#define CLK_RST_CONTROLLER544_LAST_REG 0xb90008 // CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0
#define CLK_RST_CONTROLLER545_FIRST_REG 0xb91000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0
#define CLK_RST_CONTROLLER545_LAST_REG 0xb91008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0
#define CLK_RST_CONTROLLER546_FIRST_REG 0xb92000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0
#define CLK_RST_CONTROLLER546_LAST_REG 0xb92000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0
#define CLK_RST_CONTROLLER547_FIRST_REG 0xb93000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0
#define CLK_RST_CONTROLLER547_LAST_REG 0xb93000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0
#define CLK_RST_CONTROLLER548_FIRST_REG 0xb98000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_I2C10_0
#define CLK_RST_CONTROLLER548_LAST_REG 0xb98034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_I2C10_0
#define CLK_RST_CONTROLLER549_FIRST_REG 0xba0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER549_LAST_REG 0xba0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0
#define CLK_RST_CONTROLLER550_FIRST_REG 0xba1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER550_LAST_REG 0xba1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER551_FIRST_REG 0xba2000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER551_LAST_REG 0xba2000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER552_FIRST_REG 0xba8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER552_LAST_REG 0xba8034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER553_FIRST_REG 0xbb0000 // CLK_RST_CONTROLLER_RST_DEV_SPI2_0
#define CLK_RST_CONTROLLER553_LAST_REG 0xbb0008 // CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0
#define CLK_RST_CONTROLLER554_FIRST_REG 0xbb1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0
#define CLK_RST_CONTROLLER554_LAST_REG 0xbb1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0
#define CLK_RST_CONTROLLER555_FIRST_REG 0xbb2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0
#define CLK_RST_CONTROLLER555_LAST_REG 0xbb2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0
#define CLK_RST_CONTROLLER556_FIRST_REG 0xbb3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0
#define CLK_RST_CONTROLLER556_LAST_REG 0xbb3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0
#define CLK_RST_CONTROLLER557_FIRST_REG 0xbc0000 // CLK_RST_CONTROLLER_RST_DEV_DMIC5_0
#define CLK_RST_CONTROLLER557_LAST_REG 0xbc0008 // CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0
#define CLK_RST_CONTROLLER558_FIRST_REG 0xbc1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0
#define CLK_RST_CONTROLLER558_LAST_REG 0xbc1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0
#define CLK_RST_CONTROLLER559_FIRST_REG 0xbc2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0
#define CLK_RST_CONTROLLER559_LAST_REG 0xbc2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0
#define CLK_RST_CONTROLLER560_FIRST_REG 0xbc3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0
#define CLK_RST_CONTROLLER560_LAST_REG 0xbc3004 // CLK_RST_CONTROLLER_CTRL_DMIC5_0
#define CLK_RST_CONTROLLER561_FIRST_REG 0xbd0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0
#define CLK_RST_CONTROLLER561_LAST_REG 0xbd0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0
#define CLK_RST_CONTROLLER562_FIRST_REG 0xbd1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0
#define CLK_RST_CONTROLLER562_LAST_REG 0xbd1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0
#define CLK_RST_CONTROLLER563_FIRST_REG 0xbd2000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0
#define CLK_RST_CONTROLLER563_LAST_REG 0xbd2000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0
#define CLK_RST_CONTROLLER564_FIRST_REG 0xbe0000 // CLK_RST_CONTROLLER_PLLAON_BASE_0
#define CLK_RST_CONTROLLER564_LAST_REG 0xbe0014 // CLK_RST_CONTROLLER_PLLAON_MISC_4_0
#define CLK_RST_CONTROLLER565_FIRST_REG 0xbf0000 // CLK_RST_CONTROLLER_OSC_CTRL_0
#define CLK_RST_CONTROLLER565_LAST_REG 0xbf0018 // CLK_RST_CONTROLLER_PWR_SEQ_0
#define CLK_RST_CONTROLLER566_FIRST_REG 0xc00000 // CLK_RST_CONTROLLER_RST_DEV_PWM4_0
#define CLK_RST_CONTROLLER566_LAST_REG 0xc00008 // CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0
#define CLK_RST_CONTROLLER567_FIRST_REG 0xc01000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0
#define CLK_RST_CONTROLLER567_LAST_REG 0xc01008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0
#define CLK_RST_CONTROLLER568_FIRST_REG 0xc02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0
#define CLK_RST_CONTROLLER568_LAST_REG 0xc02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0
#define CLK_RST_CONTROLLER569_FIRST_REG 0xc03000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0
#define CLK_RST_CONTROLLER569_LAST_REG 0xc03000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0
#define CLK_RST_CONTROLLER570_FIRST_REG 0xc10000 // CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0
#define CLK_RST_CONTROLLER570_LAST_REG 0xc10020 // CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0
#define CLK_RST_CONTROLLER571_FIRST_REG 0xc11000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0
#define CLK_RST_CONTROLLER571_LAST_REG 0xc11008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0
#define CLK_RST_CONTROLLER572_FIRST_REG 0xc12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0
#define CLK_RST_CONTROLLER572_LAST_REG 0xc12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0
#define CLK_RST_CONTROLLER573_FIRST_REG 0xc13000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0
#define CLK_RST_CONTROLLER573_LAST_REG 0xc1300c // CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0
#define CLK_RST_CONTROLLER574_FIRST_REG 0xc18000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_TSC_REF_0
#define CLK_RST_CONTROLLER574_LAST_REG 0xc18034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_TSC_REF_0
#define CLK_RST_CONTROLLER575_FIRST_REG 0xc20000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER575_LAST_REG 0xc20008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0
#define CLK_RST_CONTROLLER576_FIRST_REG 0xc21000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER576_LAST_REG 0xc21000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER577_FIRST_REG 0xc22000 // CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER577_LAST_REG 0xc22000 // CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER578_FIRST_REG 0xc28000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER578_LAST_REG 0xc28034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER579_FIRST_REG 0xc30000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER579_LAST_REG 0xc300e8 // CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER580_FIRST_REG 0xc50000 // CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0
#define CLK_RST_CONTROLLER580_LAST_REG 0xc50000 // CLK_RST_CONTROLLER_VSOC_VMON_CTRL_0
#define CLK_RST_CONTROLLER581_FIRST_REG 0xcb0000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0
#define CLK_RST_CONTROLLER581_LAST_REG 0xcb0000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_SHARED_0
#define CLK_RST_CONTROLLER582_FIRST_REG 0xcb1000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0
#define CLK_RST_CONTROLLER582_LAST_REG 0xcb1000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_PRIVATE_0
#define CLK_RST_CONTROLLER583_FIRST_REG 0xcb2000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER583_LAST_REG 0xcb2000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER584_FIRST_REG 0xcb3000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0
#define CLK_RST_CONTROLLER584_LAST_REG 0xcb3000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_DMIC5_0
#define CLK_RST_CONTROLLER585_FIRST_REG 0xcb4000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0
#define CLK_RST_CONTROLLER585_LAST_REG 0xcb4000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN_0
#define CLK_RST_CONTROLLER586_FIRST_REG 0xcb5000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0
#define CLK_RST_CONTROLLER586_LAST_REG 0xcb5000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_GPIO_0
#define CLK_RST_CONTROLLER587_FIRST_REG 0xcb6000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0
#define CLK_RST_CONTROLLER587_LAST_REG 0xcb6000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_HSP_0
#define CLK_RST_CONTROLLER588_FIRST_REG 0xcb7000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0
#define CLK_RST_CONTROLLER588_LAST_REG 0xcb7000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_0
#define CLK_RST_CONTROLLER589_FIRST_REG 0xcb8000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0
#define CLK_RST_CONTROLLER589_LAST_REG 0xcb8000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_0
#define CLK_RST_CONTROLLER590_FIRST_REG 0xcb9000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0
#define CLK_RST_CONTROLLER590_LAST_REG 0xcb9000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_0
#define CLK_RST_CONTROLLER591_FIRST_REG 0xcba000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER591_LAST_REG 0xcba000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER592_FIRST_REG 0xcbb000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0
#define CLK_RST_CONTROLLER592_LAST_REG 0xcbb000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_OSC_0
#define CLK_RST_CONTROLLER593_FIRST_REG 0xcbc000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0
#define CLK_RST_CONTROLLER593_LAST_REG 0xcbc000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_PLLAON_0
#define CLK_RST_CONTROLLER594_FIRST_REG 0xcbd000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0
#define CLK_RST_CONTROLLER594_LAST_REG 0xcbd000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_PWM4_0
#define CLK_RST_CONTROLLER595_FIRST_REG 0xcbe000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0
#define CLK_RST_CONTROLLER595_LAST_REG 0xcbe000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_SPI2_0
#define CLK_RST_CONTROLLER596_FIRST_REG 0xcbf000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0
#define CLK_RST_CONTROLLER596_LAST_REG 0xcbf000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_0
#define CLK_RST_CONTROLLER597_FIRST_REG 0xcc0000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0
#define CLK_RST_CONTROLLER597_LAST_REG 0xcc0000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTC_0
#define CLK_RST_CONTROLLER598_FIRST_REG 0xcc1000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0
#define CLK_RST_CONTROLLER598_LAST_REG 0xcc1000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_UARTG_0
#define CLK_RST_CONTROLLER599_FIRST_REG 0xcc2000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER599_LAST_REG 0xcc2000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER600_FIRST_REG 0xcc3000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0
#define CLK_RST_CONTROLLER600_LAST_REG 0xcc3000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_UFS_0
#define CLK_RST_CONTROLLER601_FIRST_REG 0xcc4000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0
#define CLK_RST_CONTROLLER601_LAST_REG 0xcc4000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_TOUCH_0
#define CLK_RST_CONTROLLER602_FIRST_REG 0xcc5000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0
#define CLK_RST_CONTROLLER602_LAST_REG 0xcc5000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_APB_FMON_0
#define CLK_RST_CONTROLLER603_FIRST_REG 0xcc6000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0
#define CLK_RST_CONTROLLER603_LAST_REG 0xcc6000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN1_FMON_0
#define CLK_RST_CONTROLLER604_FIRST_REG 0xcc7000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER604_LAST_REG 0xcc7000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C_SLOW_SCR_FMON_0
#define CLK_RST_CONTROLLER605_FIRST_REG 0xcc8000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0
#define CLK_RST_CONTROLLER605_LAST_REG 0xcc8000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_CAN2_FMON_0
#define CLK_RST_CONTROLLER606_FIRST_REG 0xcc9000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0
#define CLK_RST_CONTROLLER606_LAST_REG 0xcc9000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C2_FMON_0
#define CLK_RST_CONTROLLER607_FIRST_REG 0xcca000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0
#define CLK_RST_CONTROLLER607_LAST_REG 0xcca000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C8_FMON_0
#define CLK_RST_CONTROLLER608_FIRST_REG 0xccb000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0
#define CLK_RST_CONTROLLER608_LAST_REG 0xccb000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_I2C10_FMON_0
#define CLK_RST_CONTROLLER609_FIRST_REG 0xccc000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0
#define CLK_RST_CONTROLLER609_LAST_REG 0xccc000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_AON_CPU_FMON_0
#define CLK_RST_CONTROLLER610_FIRST_REG 0xccd000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0
#define CLK_RST_CONTROLLER610_LAST_REG 0xccd000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_TSC_REF_FMON_0
#define CLK_RST_CONTROLLER611_FIRST_REG 0xcce000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0
#define CLK_RST_CONTROLLER611_LAST_REG 0xcce000 // CLK_RST_CONTROLLER_CLK_SPARE_AON_MSS_ENCRYPT_FMON_0
#define CLK_RST_CONTROLLER612_FIRST_REG 0xcdf000 // CLK_RST_CONTROLLER_AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER612_LAST_REG 0xcdf078 // CLK_RST_CONTROLLER_MSS_ENCRYPT_SCR_FMON_0
#define CLK_RST_CONTROLLER613_FIRST_REG 0xce0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VREFRO_0
#define CLK_RST_CONTROLLER613_LAST_REG 0xce0028 // CLK_RST_CONTROLLER_VREFRO_DFT_BYPASS_0
#define CLK_RST_CONTROLLER614_FIRST_REG 0xce1000 // CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0
#define CLK_RST_CONTROLLER614_LAST_REG 0xce1000 // CLK_RST_CONTROLLER_VREFRO_BYPASS_CLK_DIVISOR_0
#define CLK_RST_CONTROLLER615_FIRST_REG 0xce2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0
#define CLK_RST_CONTROLLER615_LAST_REG 0xce2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VREFRO_0
#define CLK_RST_CONTROLLER616_FIRST_REG 0xcef000 // CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER616_LAST_REG 0xcef000 // CLK_RST_CONTROLLER_VREFRO_SYS_SCR_SHARED_0
#define CLK_RST_CONTROLLER617_FIRST_REG 0xd00000 // CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER617_LAST_REG 0xd0005c // CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0
#define CLK_RST_CONTROLLER618_FIRST_REG 0xd01000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER618_LAST_REG 0xd01008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER619_FIRST_REG 0xd02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER619_LAST_REG 0xd02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER620_FIRST_REG 0xd03000 // CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER620_LAST_REG 0xd03008 // CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER621_FIRST_REG 0xd08000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_SCE_CPU_0
#define CLK_RST_CONTROLLER621_LAST_REG 0xd08034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_SCE_CPU_0
#define CLK_RST_CONTROLLER622_FIRST_REG 0xd20000 // CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER622_LAST_REG 0xd200a0 // CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER623_FIRST_REG 0xd30000 // CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER623_LAST_REG 0xd30024 // CLK_RST_CONTROLLER_SCE_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER624_FIRST_REG 0xd30040 // CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER624_LAST_REG 0xd3005c // CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER625_FIRST_REG 0xd3006c // CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER625_LAST_REG 0xd30074 // CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER626_FIRST_REG 0xd3007c // CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER626_LAST_REG 0xd3007c // CLK_RST_CONTROLLER_SCE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER627_FIRST_REG 0xde0000 // CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0
#define CLK_RST_CONTROLLER627_LAST_REG 0xde0000 // CLK_RST_CONTROLLER_CLK_SPARE_SCE_SHARED_0
#define CLK_RST_CONTROLLER628_FIRST_REG 0xde1000 // CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0
#define CLK_RST_CONTROLLER628_LAST_REG 0xde1000 // CLK_RST_CONTROLLER_CLK_SPARE_SCE_PRIVATE_0
#define CLK_RST_CONTROLLER629_FIRST_REG 0xde2000 // CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0
#define CLK_RST_CONTROLLER629_LAST_REG 0xde2000 // CLK_RST_CONTROLLER_CLK_SPARE_SCE_DVFS_0
#define CLK_RST_CONTROLLER630_FIRST_REG 0xde3000 // CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0
#define CLK_RST_CONTROLLER630_LAST_REG 0xde3000 // CLK_RST_CONTROLLER_CLK_SPARE_SCE_FMON_0
#define CLK_RST_CONTROLLER631_FIRST_REG 0xdef000 // CLK_RST_CONTROLLER_SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER631_LAST_REG 0xdef00c // CLK_RST_CONTROLLER_SCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER632_FIRST_REG 0xe10000 // CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER632_LAST_REG 0xe10024 // CLK_RST_CONTROLLER_NVDEC_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER633_FIRST_REG 0xe10040 // CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER633_LAST_REG 0xe1005c // CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER634_FIRST_REG 0xe1006c // CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER634_LAST_REG 0xe10074 // CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER635_FIRST_REG 0xe1007c // CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER635_LAST_REG 0xe1007c // CLK_RST_CONTROLLER_NVDEC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER636_FIRST_REG 0xe20000 // CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER636_LAST_REG 0xe20024 // CLK_RST_CONTROLLER_NVJPG_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER637_FIRST_REG 0xe20040 // CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER637_LAST_REG 0xe2005c // CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER638_FIRST_REG 0xe2006c // CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER638_LAST_REG 0xe20074 // CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER639_FIRST_REG 0xe2007c // CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER639_LAST_REG 0xe2007c // CLK_RST_CONTROLLER_NVJPG_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER640_FIRST_REG 0xe30000 // CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER640_LAST_REG 0xe30024 // CLK_RST_CONTROLLER_TSEC_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER641_FIRST_REG 0xe30040 // CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER641_LAST_REG 0xe3005c // CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER642_FIRST_REG 0xe3006c // CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER642_LAST_REG 0xe30074 // CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER643_FIRST_REG 0xe3007c // CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER643_LAST_REG 0xe3007c // CLK_RST_CONTROLLER_TSEC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER644_FIRST_REG 0xe40000 // CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER644_LAST_REG 0xe40024 // CLK_RST_CONTROLLER_TSECB_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER645_FIRST_REG 0xe40040 // CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER645_LAST_REG 0xe4005c // CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER646_FIRST_REG 0xe4006c // CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER646_LAST_REG 0xe40074 // CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER647_FIRST_REG 0xe4007c // CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER647_LAST_REG 0xe4007c // CLK_RST_CONTROLLER_TSECB_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER648_FIRST_REG 0xe50000 // CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER648_LAST_REG 0xe50024 // CLK_RST_CONTROLLER_VI_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER649_FIRST_REG 0xe50040 // CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER649_LAST_REG 0xe5005c // CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER650_FIRST_REG 0xe5006c // CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER650_LAST_REG 0xe50074 // CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER651_FIRST_REG 0xe5007c // CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER651_LAST_REG 0xe5007c // CLK_RST_CONTROLLER_VI_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER652_FIRST_REG 0xe60000 // CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER652_LAST_REG 0xe60024 // CLK_RST_CONTROLLER_SE_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER653_FIRST_REG 0xe60040 // CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER653_LAST_REG 0xe6005c // CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER654_FIRST_REG 0xe6006c // CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER654_LAST_REG 0xe60074 // CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER655_FIRST_REG 0xe6007c // CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER655_LAST_REG 0xe6007c // CLK_RST_CONTROLLER_SE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER656_FIRST_REG 0xe70000 // CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER656_LAST_REG 0xe70024 // CLK_RST_CONTROLLER_NVENC_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER657_FIRST_REG 0xe70040 // CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER657_LAST_REG 0xe7005c // CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER658_FIRST_REG 0xe7006c // CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER658_LAST_REG 0xe70074 // CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER659_FIRST_REG 0xe7007c // CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER659_LAST_REG 0xe7007c // CLK_RST_CONTROLLER_NVENC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER660_FIRST_REG 0xe80000 // CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER660_LAST_REG 0xe80024 // CLK_RST_CONTROLLER_ISP_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER661_FIRST_REG 0xe80040 // CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER661_LAST_REG 0xe8005c // CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER662_FIRST_REG 0xe8006c // CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER662_LAST_REG 0xe80074 // CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER663_FIRST_REG 0xe8007c // CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER663_LAST_REG 0xe8007c // CLK_RST_CONTROLLER_ISP_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER664_FIRST_REG 0xe90000 // CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER664_LAST_REG 0xe90024 // CLK_RST_CONTROLLER_VIC_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER665_FIRST_REG 0xe90040 // CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER665_LAST_REG 0xe9005c // CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER666_FIRST_REG 0xe9006c // CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER666_LAST_REG 0xe90074 // CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER667_FIRST_REG 0xe9007c // CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER667_LAST_REG 0xe9007c // CLK_RST_CONTROLLER_VIC_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER668_FIRST_REG 0xec0000 // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER668_LAST_REG 0xec0024 // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER669_FIRST_REG 0xec0040 // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER669_LAST_REG 0xec005c // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER670_FIRST_REG 0xec006c // CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER670_LAST_REG 0xec0074 // CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER671_FIRST_REG 0xec007c // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER671_LAST_REG 0xec007c // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER672_FIRST_REG 0xed0000 // CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER672_LAST_REG 0xed0024 // CLK_RST_CONTROLLER_AXICBB_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER673_FIRST_REG 0xed0040 // CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER673_LAST_REG 0xed005c // CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER674_FIRST_REG 0xed006c // CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER674_LAST_REG 0xed0074 // CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER675_FIRST_REG 0xed007c // CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER675_LAST_REG 0xed007c // CLK_RST_CONTROLLER_AXICBB_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER676_FIRST_REG 0xfc0000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0
#define CLK_RST_CONTROLLER676_LAST_REG 0xfc0008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0
#define CLK_RST_CONTROLLER677_FIRST_REG 0xfc1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0
#define CLK_RST_CONTROLLER677_LAST_REG 0xfc1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0
#define CLK_RST_CONTROLLER678_FIRST_REG 0xfc2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0
#define CLK_RST_CONTROLLER678_LAST_REG 0xfc2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0
#define CLK_RST_CONTROLLER679_FIRST_REG 0xfc3000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0
#define CLK_RST_CONTROLLER679_LAST_REG 0xfc3000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0
#define CLK_RST_CONTROLLER680_FIRST_REG 0xff0090 // CLK_RST_CONTROLLER_SOC_ADC_CTRL_0
#define CLK_RST_CONTROLLER680_LAST_REG 0xff00ac // CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0
#define CLK_RST_CONTROLLER681_FIRST_REG 0x1100000 // CLK_RST_CONTROLLER_CLK_M_DIVIDE_0
#define CLK_RST_CONTROLLER681_LAST_REG 0x1100000 // CLK_RST_CONTROLLER_CLK_M_DIVIDE_0
#define CLK_RST_CONTROLLER682_FIRST_REG 0x1110000 // CLK_RST_CONTROLLER_RST_DEV_QSPI1_0
#define CLK_RST_CONTROLLER682_LAST_REG 0x1110008 // CLK_RST_CONTROLLER_RST_DEV_QSPI1_CLR_0
#define CLK_RST_CONTROLLER683_FIRST_REG 0x1111000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_0
#define CLK_RST_CONTROLLER683_LAST_REG 0x1111008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI1_CLR_0
#define CLK_RST_CONTROLLER684_FIRST_REG 0x1112000 // CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0
#define CLK_RST_CONTROLLER684_LAST_REG 0x1112000 // CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI1_0
#define CLK_RST_CONTROLLER685_FIRST_REG 0x1113000 // CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0
#define CLK_RST_CONTROLLER685_LAST_REG 0x1113000 // CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1_0
#define CLK_RST_CONTROLLER686_FIRST_REG 0x1130000 // CLK_RST_CONTROLLER_RST_DEV_DLA0_0
#define CLK_RST_CONTROLLER686_LAST_REG 0x1130008 // CLK_RST_CONTROLLER_RST_DEV_DLA0_CLR_0
#define CLK_RST_CONTROLLER687_FIRST_REG 0x1131000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_0
#define CLK_RST_CONTROLLER687_LAST_REG 0x1131008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA0_CLR_0
#define CLK_RST_CONTROLLER688_FIRST_REG 0x1132000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0
#define CLK_RST_CONTROLLER688_LAST_REG 0x1132000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DLA0_0
#define CLK_RST_CONTROLLER689_FIRST_REG 0x1133000 // CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_FALCON_0
#define CLK_RST_CONTROLLER689_LAST_REG 0x1133004 // CLK_RST_CONTROLLER_DLA0_FALCON_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER690_FIRST_REG 0x1134000 // CLK_RST_CONTROLLER_CLK_SOURCE_DLA0_CORE_0
#define CLK_RST_CONTROLLER690_LAST_REG 0x1134004 // CLK_RST_CONTROLLER_DLA0_CORE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER691_FIRST_REG 0x1138000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA0_CORE_0
#define CLK_RST_CONTROLLER691_LAST_REG 0x113806c // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA0_FALCON_0
#define CLK_RST_CONTROLLER692_FIRST_REG 0x1139000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0
#define CLK_RST_CONTROLLER692_LAST_REG 0x1139000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FUNC_0
#define CLK_RST_CONTROLLER693_FIRST_REG 0x113a000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER693_LAST_REG 0x113a000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA0_CORE_FMON_0
#define CLK_RST_CONTROLLER694_FIRST_REG 0x113b000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER694_LAST_REG 0x113b000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER695_FIRST_REG 0x113f000 // CLK_RST_CONTROLLER_DLA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER695_LAST_REG 0x113f008 // CLK_RST_CONTROLLER_DLA0_SCR_DLA0_FALCON_FMON_0
#define CLK_RST_CONTROLLER696_FIRST_REG 0x1140000 // CLK_RST_CONTROLLER_RST_DEV_DLA1_0
#define CLK_RST_CONTROLLER696_LAST_REG 0x1140008 // CLK_RST_CONTROLLER_RST_DEV_DLA1_CLR_0
#define CLK_RST_CONTROLLER697_FIRST_REG 0x1141000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_0
#define CLK_RST_CONTROLLER697_LAST_REG 0x1141008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DLA1_CLR_0
#define CLK_RST_CONTROLLER698_FIRST_REG 0x1142000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0
#define CLK_RST_CONTROLLER698_LAST_REG 0x1142000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DLA1_0
#define CLK_RST_CONTROLLER699_FIRST_REG 0x1143000 // CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_FALCON_0
#define CLK_RST_CONTROLLER699_LAST_REG 0x1143004 // CLK_RST_CONTROLLER_DLA1_FALCON_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER700_FIRST_REG 0x1144000 // CLK_RST_CONTROLLER_CLK_SOURCE_DLA1_CORE_0
#define CLK_RST_CONTROLLER700_LAST_REG 0x1144004 // CLK_RST_CONTROLLER_DLA1_CORE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER701_FIRST_REG 0x1148000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_DLA1_CORE_0
#define CLK_RST_CONTROLLER701_LAST_REG 0x114806c // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_DLA1_FALCON_0
#define CLK_RST_CONTROLLER702_FIRST_REG 0x1149000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0
#define CLK_RST_CONTROLLER702_LAST_REG 0x1149000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FUNC_0
#define CLK_RST_CONTROLLER703_FIRST_REG 0x114a000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER703_LAST_REG 0x114a000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA1_CORE_FMON_0
#define CLK_RST_CONTROLLER704_FIRST_REG 0x114b000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER704_LAST_REG 0x114b000 // CLK_RST_CONTROLLER_CLK_SPARE_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER705_FIRST_REG 0x114f000 // CLK_RST_CONTROLLER_DLA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER705_LAST_REG 0x114f008 // CLK_RST_CONTROLLER_DLA1_SCR_DLA1_FALCON_FMON_0
#define CLK_RST_CONTROLLER706_FIRST_REG 0xee0000 // CLK_RST_CONTROLLER_DLA_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER706_LAST_REG 0xee0024 // CLK_RST_CONTROLLER_DLA_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER707_FIRST_REG 0xee0040 // CLK_RST_CONTROLLER_DLA_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER707_LAST_REG 0xee005c // CLK_RST_CONTROLLER_DLA_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER708_FIRST_REG 0xee006c // CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER708_LAST_REG 0xee0074 // CLK_RST_CONTROLLER_DLA_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER709_FIRST_REG 0xee007c // CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER709_LAST_REG 0xee007c // CLK_RST_CONTROLLER_DLA_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER710_FIRST_REG 0xef0000 // CLK_RST_CONTROLLER_PVA_CORE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER710_LAST_REG 0xef0024 // CLK_RST_CONTROLLER_PVA_CORE_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER711_FIRST_REG 0xef0040 // CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER711_LAST_REG 0xef005c // CLK_RST_CONTROLLER_PVA_CORE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER712_FIRST_REG 0xef006c // CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER712_LAST_REG 0xef0074 // CLK_RST_CONTROLLER_PVA_CORE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER713_FIRST_REG 0xef007c // CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER713_LAST_REG 0xef007c // CLK_RST_CONTROLLER_PVA_CORE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER714_FIRST_REG 0xf00000 // CLK_RST_CONTROLLER_PVA_VPS_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER714_LAST_REG 0xf00024 // CLK_RST_CONTROLLER_PVA_VPS_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER715_FIRST_REG 0xf00040 // CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER715_LAST_REG 0xf0005c // CLK_RST_CONTROLLER_PVA_VPS_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER716_FIRST_REG 0xf0006c // CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER716_LAST_REG 0xf00074 // CLK_RST_CONTROLLER_PVA_VPS_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER717_FIRST_REG 0xf0007c // CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER717_LAST_REG 0xf0007c // CLK_RST_CONTROLLER_PVA_VPS_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER718_FIRST_REG 0x1150000 // CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER718_LAST_REG 0x115015c // CLK_RST_CONTROLLER_RST_DEV_PVA0_GTE_CLR_0
#define CLK_RST_CONTROLLER719_FIRST_REG 0x1158000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA0_CPU_AXI_0
#define CLK_RST_CONTROLLER719_LAST_REG 0x115806c // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA0_VPS_0
#define CLK_RST_CONTROLLER720_FIRST_REG 0x1159000 // CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FMON_0
#define CLK_RST_CONTROLLER720_LAST_REG 0x1159004 // CLK_RST_CONTROLLER_CLK_SPARE_PVA0_VPS_FMON_0
#define CLK_RST_CONTROLLER721_FIRST_REG 0x115a000 // CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0
#define CLK_RST_CONTROLLER721_LAST_REG 0x115a000 // CLK_RST_CONTROLLER_CLK_SPARE_PVA0_FUNC_0
#define CLK_RST_CONTROLLER722_FIRST_REG 0x115f000 // CLK_RST_CONTROLLER_PVA0_SCR_FUNC_0
#define CLK_RST_CONTROLLER722_LAST_REG 0x115f008 // CLK_RST_CONTROLLER_PVA0_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER723_FIRST_REG 0x1160000 // CLK_RST_CONTROLLER_CLK_SOURCE_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER723_LAST_REG 0x116015c // CLK_RST_CONTROLLER_RST_DEV_PVA1_GTE_CLR_0
#define CLK_RST_CONTROLLER724_FIRST_REG 0x1168000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PVA1_CPU_AXI_0
#define CLK_RST_CONTROLLER724_LAST_REG 0x116806c // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PVA1_VPS_0
#define CLK_RST_CONTROLLER725_FIRST_REG 0x1169000 // CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FMON_0
#define CLK_RST_CONTROLLER725_LAST_REG 0x1169004 // CLK_RST_CONTROLLER_CLK_SPARE_PVA1_VPS_FMON_0
#define CLK_RST_CONTROLLER726_FIRST_REG 0x116a000 // CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0
#define CLK_RST_CONTROLLER726_LAST_REG 0x116a000 // CLK_RST_CONTROLLER_CLK_SPARE_PVA1_FUNC_0
#define CLK_RST_CONTROLLER727_FIRST_REG 0x116f000 // CLK_RST_CONTROLLER_PVA1_SCR_FUNC_0
#define CLK_RST_CONTROLLER727_LAST_REG 0x116f008 // CLK_RST_CONTROLLER_PVA1_VPS_SCR_FMON_0
#define CLK_RST_CONTROLLER728_FIRST_REG 0x1170000 // CLK_RST_CONTROLLER_RST_DEV_CVNAS_0
#define CLK_RST_CONTROLLER728_LAST_REG 0x117002c // CLK_RST_CONTROLLER_RST_DEV_PVA_CLR_0
#define CLK_RST_CONTROLLER729_FIRST_REG 0x1171000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CVNAS_0
#define CLK_RST_CONTROLLER729_LAST_REG 0x117100c // CLK_RST_CONTROLLER_BOND_OUT_IP_CVNAS_0
#define CLK_RST_CONTROLLER730_FIRST_REG 0x1172000 // CLK_RST_CONTROLLER_CLK_SOURCE_CVNAS_0
#define CLK_RST_CONTROLLER730_LAST_REG 0x1172004 // CLK_RST_CONTROLLER_CVNAS_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER731_FIRST_REG 0x1178000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_CVNAS_0
#define CLK_RST_CONTROLLER731_LAST_REG 0x1178034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_CVNAS_0
#define CLK_RST_CONTROLLER732_FIRST_REG 0x117f000 // CLK_RST_CONTROLLER_CVNAS_SCR_FUNC_0
#define CLK_RST_CONTROLLER732_LAST_REG 0x117f004 // CLK_RST_CONTROLLER_CVNAS_SCR_CVNAS_FMON_0
#define CLK_RST_CONTROLLER733_FIRST_REG 0xf10000 // CLK_RST_CONTROLLER_CVNAS_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER733_LAST_REG 0xf10024 // CLK_RST_CONTROLLER_CVNAS_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER734_FIRST_REG 0xf10040 // CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER734_LAST_REG 0xf1005c // CLK_RST_CONTROLLER_CVNAS_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER735_FIRST_REG 0xf1006c // CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER735_LAST_REG 0xf10074 // CLK_RST_CONTROLLER_CVNAS_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER736_FIRST_REG 0xf1007c // CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER736_LAST_REG 0xf1007c // CLK_RST_CONTROLLER_CVNAS_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER737_FIRST_REG 0x1180090 // CLK_RST_CONTROLLER_CV_ADC_CTRL_0
#define CLK_RST_CONTROLLER737_LAST_REG 0x11800ac // CLK_RST_CONTROLLER_CV_ADC_REF_CLK_CFG_0
#define CLK_RST_CONTROLLER738_FIRST_REG 0x1181000 // CLK_RST_CONTROLLER_CV_ADC_OBS_CTRL_0
#define CLK_RST_CONTROLLER738_LAST_REG 0x1181018 // CLK_RST_CONTROLLER_CV_ADC_OBS_TSTAMP_CURRENT1_0
#define CLK_RST_CONTROLLER739_FIRST_REG 0x1000000 // CLK_RST_CONTROLLER_RST_DEV_RCE_CPU_NIC_0
#define CLK_RST_CONTROLLER739_LAST_REG 0x100005c // CLK_RST_CONTROLLER_RST_DEV_RCE_CFG_CLR_0
#define CLK_RST_CONTROLLER740_FIRST_REG 0x1001000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_0
#define CLK_RST_CONTROLLER740_LAST_REG 0x1001008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_RCE_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER741_FIRST_REG 0x1002000 // CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0
#define CLK_RST_CONTROLLER741_LAST_REG 0x1002000 // CLK_RST_CONTROLLER_BOND_OUT_IP_RCE_CPU_NIC_0
#define CLK_RST_CONTROLLER742_FIRST_REG 0x1003000 // CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_0
#define CLK_RST_CONTROLLER742_LAST_REG 0x1003008 // CLK_RST_CONTROLLER_RCE_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER743_FIRST_REG 0x1008000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_RCE_CPU_0
#define CLK_RST_CONTROLLER743_LAST_REG 0x1008034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_RCE_CPU_0
#define CLK_RST_CONTROLLER744_FIRST_REG 0x1020000 // CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER744_LAST_REG 0x10200a0 // CLK_RST_CONTROLLER_RCE_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER745_FIRST_REG 0x1030000 // CLK_RST_CONTROLLER_RCE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER745_LAST_REG 0x1030024 // CLK_RST_CONTROLLER_RCE_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER746_FIRST_REG 0x1030040 // CLK_RST_CONTROLLER_RCE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER746_LAST_REG 0x103005c // CLK_RST_CONTROLLER_RCE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER747_FIRST_REG 0x103006c // CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER747_LAST_REG 0x1030074 // CLK_RST_CONTROLLER_RCE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER748_FIRST_REG 0x103007c // CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER748_LAST_REG 0x103007c // CLK_RST_CONTROLLER_RCE_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER749_FIRST_REG 0x1040000 // CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0
#define CLK_RST_CONTROLLER749_LAST_REG 0x1040000 // CLK_RST_CONTROLLER_CLK_SPARE_RCE_SHARED_0
#define CLK_RST_CONTROLLER750_FIRST_REG 0x1041000 // CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0
#define CLK_RST_CONTROLLER750_LAST_REG 0x1041000 // CLK_RST_CONTROLLER_CLK_SPARE_RCE_PRIVATE_0
#define CLK_RST_CONTROLLER751_FIRST_REG 0x1042000 // CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0
#define CLK_RST_CONTROLLER751_LAST_REG 0x1042000 // CLK_RST_CONTROLLER_CLK_SPARE_RCE_DVFS_0
#define CLK_RST_CONTROLLER752_FIRST_REG 0x1043000 // CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0
#define CLK_RST_CONTROLLER752_LAST_REG 0x1043000 // CLK_RST_CONTROLLER_CLK_SPARE_RCE_FMON_0
#define CLK_RST_CONTROLLER753_FIRST_REG 0x10ef000 // CLK_RST_CONTROLLER_RCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER753_LAST_REG 0x10ef00c // CLK_RST_CONTROLLER_RCE_CPU_SCR_FMON_0
#define CLK_RST_CONTROLLER754_FIRST_REG 0xf30000 // CLK_RST_CONTROLLER_NVENC1_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER754_LAST_REG 0xf30024 // CLK_RST_CONTROLLER_NVENC1_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER755_FIRST_REG 0xf30040 // CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER755_LAST_REG 0xf3005c // CLK_RST_CONTROLLER_NVENC1_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER756_FIRST_REG 0xf3006c // CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER756_LAST_REG 0xf30074 // CLK_RST_CONTROLLER_NVENC1_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER757_FIRST_REG 0xf3007c // CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER757_LAST_REG 0xf3007c // CLK_RST_CONTROLLER_NVENC1_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER758_FIRST_REG 0x1120000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_0
#define CLK_RST_CONTROLLER758_LAST_REG 0x1120008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_IST_CLR_0
#define CLK_RST_CONTROLLER759_FIRST_REG 0x1121000 // CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0
#define CLK_RST_CONTROLLER759_LAST_REG 0x1121000 // CLK_RST_CONTROLLER_BOND_OUT_IP_IST_0
#define CLK_RST_CONTROLLER760_FIRST_REG 0x1122000 // CLK_RST_CONTROLLER_CLK_SOURCE_IST_0
#define CLK_RST_CONTROLLER760_LAST_REG 0x1122000 // CLK_RST_CONTROLLER_CLK_SOURCE_IST_0
#define CLK_RST_CONTROLLER761_FIRST_REG 0x2f0000 // CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_0
#define CLK_RST_CONTROLLER761_LAST_REG 0x2f0008 // CLK_RST_CONTROLLER_RST_DEV_NVHS_RAIL_CLR_0
#define CLK_RST_CONTROLLER762_FIRST_REG 0x1260000 // CLK_RST_CONTROLLER_RST_DEV_NVLINK_0
#define CLK_RST_CONTROLLER762_LAST_REG 0x1260008 // CLK_RST_CONTROLLER_RST_DEV_NVLINK_CLR_0
#define CLK_RST_CONTROLLER763_FIRST_REG 0x1261000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_0
#define CLK_RST_CONTROLLER763_LAST_REG 0x1261008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_CLR_0
#define CLK_RST_CONTROLLER764_FIRST_REG 0x1262000 // CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0
#define CLK_RST_CONTROLLER764_LAST_REG 0x1262000 // CLK_RST_CONTROLLER_NVLINK_CLK_CTRL_0
#define CLK_RST_CONTROLLER765_FIRST_REG 0x1263000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_0
#define CLK_RST_CONTROLLER765_LAST_REG 0x1263008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVLINK_SYSCLK_CLR_0
#define CLK_RST_CONTROLLER766_FIRST_REG 0x1264000 // CLK_RST_CONTROLLER_CLOCK_SOURCE_NVLINK_SYSCLK_0
#define CLK_RST_CONTROLLER766_LAST_REG 0x1264004 // CLK_RST_CONTROLLER_NVLINK_TX_DIV_CLK_DIVISOR_0
#define CLK_RST_CONTROLLER767_FIRST_REG 0x1265000 // CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0
#define CLK_RST_CONTROLLER767_LAST_REG 0x1265000 // CLK_RST_CONTROLLER_CLK_SPARE_NVLINK_CORE_0
#define CLK_RST_CONTROLLER768_FIRST_REG 0x1266000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVLINK_SYS_0
#define CLK_RST_CONTROLLER768_LAST_REG 0x12660a4 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_LINK_0_RXLINK_0
#define CLK_RST_CONTROLLER769_FIRST_REG 0x126f000 // CLK_RST_CONTROLLER_NVLINK_SCR_FUNC_0
#define CLK_RST_CONTROLLER769_LAST_REG 0x126f00c // CLK_RST_CONTROLLER_LINK_0_RXLINK_SCR_FMON_0
#define CLK_RST_CONTROLLER770_FIRST_REG 0x11b0000 // CLK_RST_CONTROLLER_RST_DEV_NVHS_UPHY_0
#define CLK_RST_CONTROLLER770_LAST_REG 0x11b0040 // CLK_RST_CONTROLLER_NVHS_UPHY_SLVS_CLK_CTRL_0
#define CLK_RST_CONTROLLER771_FIRST_REG 0x11c0000 // CLK_RST_CONTROLLER_HSIO_UPHY_PLL0_CFG0_0
#define CLK_RST_CONTROLLER771_LAST_REG 0x11c007c // CLK_RST_CONTROLLER_HSIO_UPHY_IST1_CLK_CTRL_0
#define CLK_RST_CONTROLLER772_FIRST_REG 0x11d0000 // CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_0
#define CLK_RST_CONTROLLER772_LAST_REG 0x11d0008 // CLK_RST_CONTROLLER_RST_DEV_PEX0_CORE_CLR_0
#define CLK_RST_CONTROLLER773_FIRST_REG 0x11d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_0
#define CLK_RST_CONTROLLER773_LAST_REG 0x11d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX0_CORE_CLR_0
#define CLK_RST_CONTROLLER774_FIRST_REG 0x11d2000 // CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0
#define CLK_RST_CONTROLLER774_LAST_REG 0x11d2000 // CLK_RST_CONTROLLER_PEX0_P2U_CLK_CTRL_0
#define CLK_RST_CONTROLLER775_FIRST_REG 0x11d3000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX0_CORE_0_0
#define CLK_RST_CONTROLLER775_LAST_REG 0x11d3114 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX0_CORE_4_0
#define CLK_RST_CONTROLLER776_FIRST_REG 0x11df000 // CLK_RST_CONTROLLER_PEX0_SCR_FUNC_0
#define CLK_RST_CONTROLLER776_LAST_REG 0x11df004 // CLK_RST_CONTROLLER_PEX0_SCR_FMON_0
#define CLK_RST_CONTROLLER777_FIRST_REG 0x11e0000 // CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_0
#define CLK_RST_CONTROLLER777_LAST_REG 0x11e0008 // CLK_RST_CONTROLLER_RST_DEV_PEX1_CORE_CLR_0
#define CLK_RST_CONTROLLER778_FIRST_REG 0x11e1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_0
#define CLK_RST_CONTROLLER778_LAST_REG 0x11e1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PEX1_CORE_CLR_0
#define CLK_RST_CONTROLLER779_FIRST_REG 0x11e2000 // CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0
#define CLK_RST_CONTROLLER779_LAST_REG 0x11e2000 // CLK_RST_CONTROLLER_PEX1_P2U_CLK_CTRL_0
#define CLK_RST_CONTROLLER780_FIRST_REG 0x11e3000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER780_LAST_REG 0x11e3034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_PEX1_CORE_5_0
#define CLK_RST_CONTROLLER781_FIRST_REG 0x11ef000 // CLK_RST_CONTROLLER_PEX1_SCR_FUNC_0
#define CLK_RST_CONTROLLER781_LAST_REG 0x11ef004 // CLK_RST_CONTROLLER_PEX1_SCR_FMON_0
#define CLK_RST_CONTROLLER782_FIRST_REG 0x11f0000 // CLK_RST_CONTROLLER_PLLNVHS_SS_CNTL_0
#define CLK_RST_CONTROLLER782_LAST_REG 0x11f0020 // CLK_RST_CONTROLLER_PLLNVHS_AUX1_0
#define CLK_RST_CONTROLLER783_FIRST_REG 0x790000 // CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER783_LAST_REG 0x790000 // CLK_RST_CONTROLLER_AXI2APB_6_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER784_FIRST_REG 0x1270000 // CLK_RST_CONTROLLER_RST_DEV_NVENC1_0
#define CLK_RST_CONTROLLER784_LAST_REG 0x1270008 // CLK_RST_CONTROLLER_RST_DEV_NVENC1_CLR_0
#define CLK_RST_CONTROLLER785_FIRST_REG 0x1271000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_0
#define CLK_RST_CONTROLLER785_LAST_REG 0x1271008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC1_CLR_0
#define CLK_RST_CONTROLLER786_FIRST_REG 0x1272000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0
#define CLK_RST_CONTROLLER786_LAST_REG 0x1272000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC1_0
#define CLK_RST_CONTROLLER787_FIRST_REG 0x1273000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVENC1_0
#define CLK_RST_CONTROLLER787_LAST_REG 0x1273004 // CLK_RST_CONTROLLER_NVENC1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER788_FIRST_REG 0x1274000 // CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0
#define CLK_RST_CONTROLLER788_LAST_REG 0x1274000 // CLK_RST_CONTROLLER_CLK_SPARE_NVENC1_0
#define CLK_RST_CONTROLLER789_FIRST_REG 0x1278000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_NVENC1_0
#define CLK_RST_CONTROLLER789_LAST_REG 0x1278034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_NVENC1_0
#define CLK_RST_CONTROLLER790_FIRST_REG 0x127f000 // CLK_RST_CONTROLLER_NVENC1_SCR_FUNC_0
#define CLK_RST_CONTROLLER790_LAST_REG 0x127f004 // CLK_RST_CONTROLLER_NVENC1_SCR_FMON_0
#define CLK_RST_CONTROLLER791_FIRST_REG 0x11a0000 // CLK_RST_CONTROLLER_RST_DEV_TPIU_0
#define CLK_RST_CONTROLLER791_LAST_REG 0x11a0008 // CLK_RST_CONTROLLER_RST_DEV_TPIU_CLR_0
#define CLK_RST_CONTROLLER792_FIRST_REG 0x11a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_0
#define CLK_RST_CONTROLLER792_LAST_REG 0x11a100c // CLK_RST_CONTROLLER_BOND_OUT_IP_TPIU_0
#define CLK_RST_CONTROLLER793_FIRST_REG 0x11a2000 // CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0
#define CLK_RST_CONTROLLER793_LAST_REG 0x11a2000 // CLK_RST_CONTROLLER_CLK_SOURCE_TPIU_0
#define CLK_RST_CONTROLLER794_FIRST_REG 0x1290000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TPIU_PAD_0
#define CLK_RST_CONTROLLER794_LAST_REG 0x1290014 // CLK_RST_CONTROLLER_CTRL_TPIU_0
#define CLK_RST_CONTROLLER795_FIRST_REG 0x1280000 // CLK_RST_CONTROLLER_RST_DEV_UARTH_0
#define CLK_RST_CONTROLLER795_LAST_REG 0x1280008 // CLK_RST_CONTROLLER_RST_DEV_UARTH_CLR_0
#define CLK_RST_CONTROLLER796_FIRST_REG 0x1281000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0
#define CLK_RST_CONTROLLER796_LAST_REG 0x1281008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_CLR_0
#define CLK_RST_CONTROLLER797_FIRST_REG 0x1282000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0
#define CLK_RST_CONTROLLER797_LAST_REG 0x1282000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTH_0
#define CLK_RST_CONTROLLER798_FIRST_REG 0x1283000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0
#define CLK_RST_CONTROLLER798_LAST_REG 0x1283000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0
#define CLK_RST_CONTROLLER799_FIRST_REG 0x210000 // CLK_RST_CONTROLLER_RST_DEV_MSSNVL_0
#define CLK_RST_CONTROLLER799_LAST_REG 0x210014 // CLK_RST_CONTROLLER_RST_DEV_HSH_MSSNVL_CLR_0
#define CLK_RST_CONTROLLER800_FIRST_REG 0x211000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCHUB_0
#define CLK_RST_CONTROLLER800_LAST_REG 0x21100c // CLK_RST_CONTROLLER_BOND_OUT_IP_EMCHUB_0
#define CLK_RST_CONTROLLER801_FIRST_REG 0x212000 // CLK_RST_CONTROLLER_EMC_MISC_0
#define CLK_RST_CONTROLLER801_LAST_REG 0x212000 // CLK_RST_CONTROLLER_EMC_MISC_0
#define CLK_RST_CONTROLLER802_FIRST_REG 0x1230000 // CLK_RST_CONTROLLER_RST_DEV_SLVSEC_0
#define CLK_RST_CONTROLLER802_LAST_REG 0x1230008 // CLK_RST_CONTROLLER_RST_DEV_SLVSEC_CLR_0
#define CLK_RST_CONTROLLER803_FIRST_REG 0x1231000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_0
#define CLK_RST_CONTROLLER803_LAST_REG 0x1231008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SLVSEC_CLR_0
#define CLK_RST_CONTROLLER804_FIRST_REG 0x1232000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0
#define CLK_RST_CONTROLLER804_LAST_REG 0x1232000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SLVSEC_0
#define CLK_RST_CONTROLLER805_FIRST_REG 0x1233000 // CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0
#define CLK_RST_CONTROLLER805_LAST_REG 0x1233000 // CLK_RST_CONTROLLER_CLK_SOURCE_SLVSEC_PADCTRL_0
#define CLK_RST_CONTROLLER806_FIRST_REG 0x1233008 // CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0
#define CLK_RST_CONTROLLER806_LAST_REG 0x1233008 // CLK_RST_CONTROLLER_CLK_SOURCE_SLVSCIL_IOBIST_0
#define CLK_RST_CONTROLLER807_FIRST_REG 0xf40000 // CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER807_LAST_REG 0xf40024 // CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER808_FIRST_REG 0xf40040 // CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER808_LAST_REG 0xf4005c // CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER809_FIRST_REG 0xf4006c // CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER809_LAST_REG 0xf40074 // CLK_RST_CONTROLLER_DLA_FALCON_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER810_FIRST_REG 0xf4007c // CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER810_LAST_REG 0xf4007c // CLK_RST_CONTROLLER_DLA_FALCON_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER811_FIRST_REG 0x1190000 // CLK_RST_CONTROLLER_RST_DEV_CV_0
#define CLK_RST_CONTROLLER811_LAST_REG 0x1190014 // CLK_RST_CONTROLLER_RST_DEV_CV_HOST1X_CLR_0
#define CLK_RST_CONTROLLER812_FIRST_REG 0x4f0000 // CLK_RST_CONTROLLER_RST_DEV_NVDEC1_0
#define CLK_RST_CONTROLLER812_LAST_REG 0x4f0008 // CLK_RST_CONTROLLER_RST_DEV_NVDEC1_CLR_0
#define CLK_RST_CONTROLLER813_FIRST_REG 0x4f1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_0
#define CLK_RST_CONTROLLER813_LAST_REG 0x4f1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC1_CLR_0
#define CLK_RST_CONTROLLER814_FIRST_REG 0x4f2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0
#define CLK_RST_CONTROLLER814_LAST_REG 0x4f2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC1_0
#define CLK_RST_CONTROLLER815_FIRST_REG 0x4f3000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC1_0
#define CLK_RST_CONTROLLER815_LAST_REG 0x4f3004 // CLK_RST_CONTROLLER_NVDEC1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER816_FIRST_REG 0x4f4000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0
#define CLK_RST_CONTROLLER816_LAST_REG 0x4f4000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDEC1_0
#define CLK_RST_CONTROLLER817_FIRST_REG 0xf50000 // CLK_RST_CONTROLLER_NVDEC1_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER817_LAST_REG 0xf50024 // CLK_RST_CONTROLLER_NVDEC1_NAFLL_DVCO_SLOW_0
#define CLK_RST_CONTROLLER818_FIRST_REG 0xf50040 // CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER818_LAST_REG 0xf5005c // CLK_RST_CONTROLLER_NVDEC1_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER819_FIRST_REG 0xf5006c // CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER819_LAST_REG 0xf50074 // CLK_RST_CONTROLLER_NVDEC1_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER820_FIRST_REG 0xf5007c // CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER820_LAST_REG 0xf5007c // CLK_RST_CONTROLLER_NVDEC1_NAFLL_PTO_CTRL1_0
#define CLK_RST_CONTROLLER821_FIRST_REG 0x20000 // CLK_RST_CONTROLLER_PLLMSC_BASE_0
#define CLK_RST_CONTROLLER821_LAST_REG 0x20028 // CLK_RST_CONTROLLER_PLLMSCB_SS_CTRL2_0
#define CLK_RST_CONTROLLER822_FIRST_REG 0xfd0000 // CLK_RST_CONTROLLER_RST_DEV_EMCSC_0
#define CLK_RST_CONTROLLER822_LAST_REG 0xfd0008 // CLK_RST_CONTROLLER_RST_DEV_EMCSC_CLR_0
#define CLK_RST_CONTROLLER823_FIRST_REG 0xfd1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_0
#define CLK_RST_CONTROLLER823_LAST_REG 0xfd1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSC_CLR_0
#define CLK_RST_CONTROLLER824_FIRST_REG 0xfd2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0
#define CLK_RST_CONTROLLER824_LAST_REG 0xfd2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSC_0
#define CLK_RST_CONTROLLER825_FIRST_REG 0xfd3000 // CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_0
#define CLK_RST_CONTROLLER825_LAST_REG 0xfd3014 // CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC_SAFE_0
#define CLK_RST_CONTROLLER826_FIRST_REG 0xfd4000 // CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0
#define CLK_RST_CONTROLLER826_LAST_REG 0xfd4000 // CLK_RST_CONTROLLER_CLK_SPARE_EMCC_0
#define CLK_RST_CONTROLLER827_FIRST_REG 0xfd8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSC_CDB_0
#define CLK_RST_CONTROLLER827_LAST_REG 0xfd8034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSC_CDB_0
#define CLK_RST_CONTROLLER828_FIRST_REG 0xfdf000 // CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FUNC_0
#define CLK_RST_CONTROLLER828_LAST_REG 0xfdf008 // CLK_RST_CONTROLLER_EMCSC_SCR_EMCSC_CDB_FMON_0
#define CLK_RST_CONTROLLER829_FIRST_REG 0x30000 // CLK_RST_CONTROLLER_PLLMSD_BASE_0
#define CLK_RST_CONTROLLER829_LAST_REG 0x30028 // CLK_RST_CONTROLLER_PLLMSDB_SS_CTRL2_0
#define CLK_RST_CONTROLLER830_FIRST_REG 0xfe0000 // CLK_RST_CONTROLLER_RST_DEV_EMCSD_0
#define CLK_RST_CONTROLLER830_LAST_REG 0xfe0008 // CLK_RST_CONTROLLER_RST_DEV_EMCSD_CLR_0
#define CLK_RST_CONTROLLER831_FIRST_REG 0xfe1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_0
#define CLK_RST_CONTROLLER831_LAST_REG 0xfe1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSD_CLR_0
#define CLK_RST_CONTROLLER832_FIRST_REG 0xfe2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0
#define CLK_RST_CONTROLLER832_LAST_REG 0xfe2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSD_0
#define CLK_RST_CONTROLLER833_FIRST_REG 0xfe3000 // CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_0
#define CLK_RST_CONTROLLER833_LAST_REG 0xfe3014 // CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD_SAFE_0
#define CLK_RST_CONTROLLER834_FIRST_REG 0xfe4000 // CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0
#define CLK_RST_CONTROLLER834_LAST_REG 0xfe4000 // CLK_RST_CONTROLLER_CLK_SPARE_EMCD_0
#define CLK_RST_CONTROLLER835_FIRST_REG 0xfe8000 // CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_EMCSD_CDB_0
#define CLK_RST_CONTROLLER835_LAST_REG 0xfe8034 // CLK_RST_CONTROLLER_FMON_DEBUG_CONFIG_EMCSD_CDB_0
#define CLK_RST_CONTROLLER836_FIRST_REG 0xfef000 // CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FUNC_0
#define CLK_RST_CONTROLLER836_LAST_REG 0xfef008 // CLK_RST_CONTROLLER_EMCSD_SCR_EMCSD_CDB_FMON_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_270_FIRST_REG 0x19b0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_27_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_270_LAST_REG 0x19b001c // CLK_RST_CONTROLLER_ERR_COLLATOR_27_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_271_FIRST_REG 0x19b0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_271_LAST_REG 0x19b0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_272_FIRST_REG 0x19b0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_272_LAST_REG 0x19b0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_27_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR0_FIRST_REG 0x19bf000 // CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR0_LAST_REG 0x19bf000 // CLK_RST_CONTROLLER_ERR_COLLATOR_27_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_340_FIRST_REG 0x1a20000 // CLK_RST_CONTROLLER_ERR_COLLATOR_34_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_340_LAST_REG 0x1a2001c // CLK_RST_CONTROLLER_ERR_COLLATOR_34_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_341_FIRST_REG 0x1a20030 // CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_341_LAST_REG 0x1a20048 // CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_342_FIRST_REG 0x1a20050 // CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_342_LAST_REG 0x1a20050 // CLK_RST_CONTROLLER_ERR_COLLATOR_34_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR0_FIRST_REG 0x1a2f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR0_LAST_REG 0x1a2f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_34_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_320_FIRST_REG 0x1a00000 // CLK_RST_CONTROLLER_ERR_COLLATOR_32_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_320_LAST_REG 0x1a0001c // CLK_RST_CONTROLLER_ERR_COLLATOR_32_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_321_FIRST_REG 0x1a00030 // CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_321_LAST_REG 0x1a00048 // CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_322_FIRST_REG 0x1a00050 // CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_322_LAST_REG 0x1a00050 // CLK_RST_CONTROLLER_ERR_COLLATOR_32_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR0_FIRST_REG 0x1a0f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR0_LAST_REG 0x1a0f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_32_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_140_FIRST_REG 0x18e0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_14_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_140_LAST_REG 0x18e001c // CLK_RST_CONTROLLER_ERR_COLLATOR_14_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_141_FIRST_REG 0x18e0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_141_LAST_REG 0x18e0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_142_FIRST_REG 0x18e0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_142_LAST_REG 0x18e0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_14_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR0_FIRST_REG 0x18ef000 // CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR0_LAST_REG 0x18ef000 // CLK_RST_CONTROLLER_ERR_COLLATOR_14_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_120_FIRST_REG 0x18c0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_12_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_120_LAST_REG 0x18c001c // CLK_RST_CONTROLLER_ERR_COLLATOR_12_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_121_FIRST_REG 0x18c0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_121_LAST_REG 0x18c0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_122_FIRST_REG 0x18c0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_122_LAST_REG 0x18c0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_12_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR0_FIRST_REG 0x18cf000 // CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR0_LAST_REG 0x18cf000 // CLK_RST_CONTROLLER_ERR_COLLATOR_12_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_200_FIRST_REG 0x1940000 // CLK_RST_CONTROLLER_ERR_COLLATOR_20_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_200_LAST_REG 0x194001c // CLK_RST_CONTROLLER_ERR_COLLATOR_20_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_201_FIRST_REG 0x1940030 // CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_201_LAST_REG 0x1940048 // CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_202_FIRST_REG 0x1940050 // CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_202_LAST_REG 0x1940050 // CLK_RST_CONTROLLER_ERR_COLLATOR_20_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR0_FIRST_REG 0x194f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR0_LAST_REG 0x194f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_20_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_50_FIRST_REG 0x1850000 // CLK_RST_CONTROLLER_ERR_COLLATOR_5_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_50_LAST_REG 0x185000c // CLK_RST_CONTROLLER_ERR_COLLATOR_5_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_51_FIRST_REG 0x1850014 // CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_51_LAST_REG 0x185001c // CLK_RST_CONTROLLER_ERR_COLLATOR_5_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_52_FIRST_REG 0x1850030 // CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_52_LAST_REG 0x1850048 // CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_53_FIRST_REG 0x1850050 // CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_53_LAST_REG 0x1850050 // CLK_RST_CONTROLLER_ERR_COLLATOR_5_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR0_FIRST_REG 0x185f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR0_LAST_REG 0x185f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_5_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_60_FIRST_REG 0x1860000 // CLK_RST_CONTROLLER_ERR_COLLATOR_6_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_60_LAST_REG 0x186001c // CLK_RST_CONTROLLER_ERR_COLLATOR_6_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_61_FIRST_REG 0x1860030 // CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_61_LAST_REG 0x1860048 // CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_62_FIRST_REG 0x1860050 // CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_62_LAST_REG 0x1860050 // CLK_RST_CONTROLLER_ERR_COLLATOR_6_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR0_FIRST_REG 0x186f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR0_LAST_REG 0x186f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_6_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_100_FIRST_REG 0x18a0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_10_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_100_LAST_REG 0x18a000c // CLK_RST_CONTROLLER_ERR_COLLATOR_10_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_101_FIRST_REG 0x18a0014 // CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_101_LAST_REG 0x18a001c // CLK_RST_CONTROLLER_ERR_COLLATOR_10_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_102_FIRST_REG 0x18a0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_102_LAST_REG 0x18a0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_103_FIRST_REG 0x18a0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_103_LAST_REG 0x18a0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_10_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR0_FIRST_REG 0x18af000 // CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR0_LAST_REG 0x18af000 // CLK_RST_CONTROLLER_ERR_COLLATOR_10_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_250_FIRST_REG 0x1990000 // CLK_RST_CONTROLLER_ERR_COLLATOR_25_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_250_LAST_REG 0x199001c // CLK_RST_CONTROLLER_ERR_COLLATOR_25_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_251_FIRST_REG 0x1990030 // CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_251_LAST_REG 0x1990048 // CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_252_FIRST_REG 0x1990050 // CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_252_LAST_REG 0x1990050 // CLK_RST_CONTROLLER_ERR_COLLATOR_25_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR0_FIRST_REG 0x199f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR0_LAST_REG 0x199f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_25_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_240_FIRST_REG 0x1980000 // CLK_RST_CONTROLLER_ERR_COLLATOR_24_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_240_LAST_REG 0x198000c // CLK_RST_CONTROLLER_ERR_COLLATOR_24_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_241_FIRST_REG 0x1980014 // CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_241_LAST_REG 0x198001c // CLK_RST_CONTROLLER_ERR_COLLATOR_24_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_242_FIRST_REG 0x1980030 // CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_242_LAST_REG 0x1980048 // CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_243_FIRST_REG 0x1980050 // CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_243_LAST_REG 0x1980050 // CLK_RST_CONTROLLER_ERR_COLLATOR_24_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR0_FIRST_REG 0x198f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR0_LAST_REG 0x198f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_24_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_160_FIRST_REG 0x1900000 // CLK_RST_CONTROLLER_ERR_COLLATOR_16_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_160_LAST_REG 0x190001c // CLK_RST_CONTROLLER_ERR_COLLATOR_16_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_161_FIRST_REG 0x1900030 // CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_161_LAST_REG 0x1900048 // CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_162_FIRST_REG 0x1900050 // CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_162_LAST_REG 0x1900050 // CLK_RST_CONTROLLER_ERR_COLLATOR_16_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR0_FIRST_REG 0x190f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR0_LAST_REG 0x190f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_16_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_230_FIRST_REG 0x1970000 // CLK_RST_CONTROLLER_ERR_COLLATOR_23_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_230_LAST_REG 0x197000c // CLK_RST_CONTROLLER_ERR_COLLATOR_23_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_231_FIRST_REG 0x1970014 // CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_231_LAST_REG 0x197001c // CLK_RST_CONTROLLER_ERR_COLLATOR_23_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_232_FIRST_REG 0x1970030 // CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_232_LAST_REG 0x1970048 // CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_233_FIRST_REG 0x1970050 // CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_233_LAST_REG 0x1970050 // CLK_RST_CONTROLLER_ERR_COLLATOR_23_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR0_FIRST_REG 0x197f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR0_LAST_REG 0x197f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_23_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_90_FIRST_REG 0x1890000 // CLK_RST_CONTROLLER_ERR_COLLATOR_9_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_90_LAST_REG 0x189001c // CLK_RST_CONTROLLER_ERR_COLLATOR_9_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_91_FIRST_REG 0x1890030 // CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_91_LAST_REG 0x1890048 // CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_92_FIRST_REG 0x1890050 // CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_92_LAST_REG 0x1890050 // CLK_RST_CONTROLLER_ERR_COLLATOR_9_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR0_FIRST_REG 0x189f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR0_LAST_REG 0x189f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_9_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_330_FIRST_REG 0x1a10000 // CLK_RST_CONTROLLER_ERR_COLLATOR_33_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_330_LAST_REG 0x1a1001c // CLK_RST_CONTROLLER_ERR_COLLATOR_33_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_331_FIRST_REG 0x1a10030 // CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_331_LAST_REG 0x1a10048 // CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_332_FIRST_REG 0x1a10050 // CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_332_LAST_REG 0x1a10050 // CLK_RST_CONTROLLER_ERR_COLLATOR_33_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR0_FIRST_REG 0x1a1f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR0_LAST_REG 0x1a1f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_33_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_260_FIRST_REG 0x19a0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_26_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_260_LAST_REG 0x19a001c // CLK_RST_CONTROLLER_ERR_COLLATOR_26_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_261_FIRST_REG 0x19a0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_261_LAST_REG 0x19a0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_262_FIRST_REG 0x19a0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_262_LAST_REG 0x19a0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_26_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR0_FIRST_REG 0x19af000 // CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR0_LAST_REG 0x19af000 // CLK_RST_CONTROLLER_ERR_COLLATOR_26_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_280_FIRST_REG 0x19c0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_28_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_280_LAST_REG 0x19c001c // CLK_RST_CONTROLLER_ERR_COLLATOR_28_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_281_FIRST_REG 0x19c0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_281_LAST_REG 0x19c0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_282_FIRST_REG 0x19c0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_282_LAST_REG 0x19c0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_28_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR0_FIRST_REG 0x19cf000 // CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR0_LAST_REG 0x19cf000 // CLK_RST_CONTROLLER_ERR_COLLATOR_28_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_400_FIRST_REG 0x1a80000 // CLK_RST_CONTROLLER_ERR_COLLATOR_40_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_400_LAST_REG 0x1a8001c // CLK_RST_CONTROLLER_ERR_COLLATOR_40_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_401_FIRST_REG 0x1a80030 // CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_401_LAST_REG 0x1a80048 // CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_402_FIRST_REG 0x1a80050 // CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_402_LAST_REG 0x1a80050 // CLK_RST_CONTROLLER_ERR_COLLATOR_40_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR0_FIRST_REG 0x1a8f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR0_LAST_REG 0x1a8f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_40_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_FIRST_REG 0x1840000 // CLK_RST_CONTROLLER_ERR_COLLATOR_4_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_40_LAST_REG 0x184001c // CLK_RST_CONTROLLER_ERR_COLLATOR_4_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_41_FIRST_REG 0x1840030 // CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_41_LAST_REG 0x1840048 // CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_42_FIRST_REG 0x1840050 // CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_42_LAST_REG 0x1840050 // CLK_RST_CONTROLLER_ERR_COLLATOR_4_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR0_FIRST_REG 0x184f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR0_LAST_REG 0x184f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_4_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_290_FIRST_REG 0x19d0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_29_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_290_LAST_REG 0x19d001c // CLK_RST_CONTROLLER_ERR_COLLATOR_29_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_291_FIRST_REG 0x19d0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_291_LAST_REG 0x19d0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_292_FIRST_REG 0x19d0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_292_LAST_REG 0x19d0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_29_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR0_FIRST_REG 0x19df000 // CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR0_LAST_REG 0x19df000 // CLK_RST_CONTROLLER_ERR_COLLATOR_29_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP0_FIRST_REG 0xaf0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP0_LAST_REG 0xaf001c // CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP1_FIRST_REG 0xaf0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP1_LAST_REG 0xaf0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP2_FIRST_REG 0xaf0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP2_LAST_REG 0xaf0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR0_FIRST_REG 0xaff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR0_LAST_REG 0xaff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_BPMP_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_130_FIRST_REG 0x18d0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_13_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_130_LAST_REG 0x18d001c // CLK_RST_CONTROLLER_ERR_COLLATOR_13_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_131_FIRST_REG 0x18d0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_131_LAST_REG 0x18d0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_132_FIRST_REG 0x18d0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_132_LAST_REG 0x18d0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_13_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR0_FIRST_REG 0x18df000 // CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR0_LAST_REG 0x18df000 // CLK_RST_CONTROLLER_ERR_COLLATOR_13_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_70_FIRST_REG 0x1870000 // CLK_RST_CONTROLLER_ERR_COLLATOR_7_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_70_LAST_REG 0x187001c // CLK_RST_CONTROLLER_ERR_COLLATOR_7_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_71_FIRST_REG 0x1870030 // CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_71_LAST_REG 0x1870048 // CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_72_FIRST_REG 0x1870050 // CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_72_LAST_REG 0x1870050 // CLK_RST_CONTROLLER_ERR_COLLATOR_7_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR0_FIRST_REG 0x187f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR0_LAST_REG 0x187f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_7_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON0_FIRST_REG 0xcf0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_AON_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON0_LAST_REG 0xcf001c // CLK_RST_CONTROLLER_ERR_COLLATOR_AON_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON1_FIRST_REG 0xcf0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON1_LAST_REG 0xcf0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON2_FIRST_REG 0xcf0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON2_LAST_REG 0xcf0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_AON_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR0_FIRST_REG 0xcff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR0_LAST_REG 0xcff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_AON_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_300_FIRST_REG 0x19e0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_30_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_300_LAST_REG 0x19e001c // CLK_RST_CONTROLLER_ERR_COLLATOR_30_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_301_FIRST_REG 0x19e0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_301_LAST_REG 0x19e0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_302_FIRST_REG 0x19e0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_302_LAST_REG 0x19e0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_30_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR0_FIRST_REG 0x19ef000 // CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR0_LAST_REG 0x19ef000 // CLK_RST_CONTROLLER_ERR_COLLATOR_30_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_150_FIRST_REG 0x18f0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_15_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_150_LAST_REG 0x18f001c // CLK_RST_CONTROLLER_ERR_COLLATOR_15_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_151_FIRST_REG 0x18f0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_151_LAST_REG 0x18f0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_152_FIRST_REG 0x18f0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_152_LAST_REG 0x18f0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_15_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR0_FIRST_REG 0x18ff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR0_LAST_REG 0x18ff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_15_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_310_FIRST_REG 0x19f0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_31_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_310_LAST_REG 0x19f001c // CLK_RST_CONTROLLER_ERR_COLLATOR_31_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_311_FIRST_REG 0x19f0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_311_LAST_REG 0x19f0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_312_FIRST_REG 0x19f0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_312_LAST_REG 0x19f0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_31_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR0_FIRST_REG 0x19ff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR0_LAST_REG 0x19ff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_31_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_190_FIRST_REG 0x1930000 // CLK_RST_CONTROLLER_ERR_COLLATOR_19_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_190_LAST_REG 0x193001c // CLK_RST_CONTROLLER_ERR_COLLATOR_19_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_191_FIRST_REG 0x1930030 // CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_191_LAST_REG 0x1930048 // CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_192_FIRST_REG 0x1930050 // CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_192_LAST_REG 0x1930050 // CLK_RST_CONTROLLER_ERR_COLLATOR_19_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR0_FIRST_REG 0x193f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR0_LAST_REG 0x193f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_19_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_110_FIRST_REG 0x18b0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_11_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_110_LAST_REG 0x18b001c // CLK_RST_CONTROLLER_ERR_COLLATOR_11_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_111_FIRST_REG 0x18b0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_111_LAST_REG 0x18b0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_112_FIRST_REG 0x18b0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_112_LAST_REG 0x18b0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_11_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR0_FIRST_REG 0x18bf000 // CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR0_LAST_REG 0x18bf000 // CLK_RST_CONTROLLER_ERR_COLLATOR_11_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE0_FIRST_REG 0x10f0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE0_LAST_REG 0x10f001c // CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE1_FIRST_REG 0x10f0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE1_LAST_REG 0x10f0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE2_FIRST_REG 0x10f0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE2_LAST_REG 0x10f0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR0_FIRST_REG 0x10ff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR0_LAST_REG 0x10ff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_RCE_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_80_FIRST_REG 0x1880000 // CLK_RST_CONTROLLER_ERR_COLLATOR_8_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_80_LAST_REG 0x188001c // CLK_RST_CONTROLLER_ERR_COLLATOR_8_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_81_FIRST_REG 0x1880030 // CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_81_LAST_REG 0x1880048 // CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_82_FIRST_REG 0x1880050 // CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_82_LAST_REG 0x1880050 // CLK_RST_CONTROLLER_ERR_COLLATOR_8_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR0_FIRST_REG 0x188f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR0_LAST_REG 0x188f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_8_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_350_FIRST_REG 0x1a30000 // CLK_RST_CONTROLLER_ERR_COLLATOR_35_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_350_LAST_REG 0x1a3001c // CLK_RST_CONTROLLER_ERR_COLLATOR_35_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_351_FIRST_REG 0x1a30030 // CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_351_LAST_REG 0x1a30048 // CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_352_FIRST_REG 0x1a30050 // CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_352_LAST_REG 0x1a30050 // CLK_RST_CONTROLLER_ERR_COLLATOR_35_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR0_FIRST_REG 0x1a3f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR0_LAST_REG 0x1a3f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_35_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE0_FIRST_REG 0xdf0000 // CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE0_LAST_REG 0xdf001c // CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE1_FIRST_REG 0xdf0030 // CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE1_LAST_REG 0xdf0048 // CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE2_FIRST_REG 0xdf0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE2_LAST_REG 0xdf0050 // CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR0_FIRST_REG 0xdff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR0_LAST_REG 0xdff000 // CLK_RST_CONTROLLER_ERR_COLLATOR_SCE_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_210_FIRST_REG 0x1950000 // CLK_RST_CONTROLLER_ERR_COLLATOR_21_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_210_LAST_REG 0x195000c // CLK_RST_CONTROLLER_ERR_COLLATOR_21_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_211_FIRST_REG 0x1950014 // CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_211_LAST_REG 0x195001c // CLK_RST_CONTROLLER_ERR_COLLATOR_21_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_212_FIRST_REG 0x1950030 // CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_212_LAST_REG 0x1950048 // CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_213_FIRST_REG 0x1950050 // CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_213_LAST_REG 0x1950050 // CLK_RST_CONTROLLER_ERR_COLLATOR_21_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR0_FIRST_REG 0x195f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR0_LAST_REG 0x195f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_21_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_220_FIRST_REG 0x1960000 // CLK_RST_CONTROLLER_ERR_COLLATOR_22_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_220_LAST_REG 0x196000c // CLK_RST_CONTROLLER_ERR_COLLATOR_22_CURRENT_COUNTER_VALUE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_221_FIRST_REG 0x1960014 // CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INDEX_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_221_LAST_REG 0x196001c // CLK_RST_CONTROLLER_ERR_COLLATOR_22_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_222_FIRST_REG 0x1960030 // CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_222_LAST_REG 0x1960048 // CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_223_FIRST_REG 0x1960050 // CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_223_LAST_REG 0x1960050 // CLK_RST_CONTROLLER_ERR_COLLATOR_22_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR0_FIRST_REG 0x196f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR0_LAST_REG 0x196f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_22_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_180_FIRST_REG 0x1920000 // CLK_RST_CONTROLLER_ERR_COLLATOR_18_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_180_LAST_REG 0x192001c // CLK_RST_CONTROLLER_ERR_COLLATOR_18_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_181_FIRST_REG 0x1920030 // CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_181_LAST_REG 0x1920048 // CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_182_FIRST_REG 0x1920050 // CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_182_LAST_REG 0x1920050 // CLK_RST_CONTROLLER_ERR_COLLATOR_18_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR0_FIRST_REG 0x192f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR0_LAST_REG 0x192f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_18_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_170_FIRST_REG 0x1910000 // CLK_RST_CONTROLLER_ERR_COLLATOR_17_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_170_LAST_REG 0x191001c // CLK_RST_CONTROLLER_ERR_COLLATOR_17_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_171_FIRST_REG 0x1910030 // CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_171_LAST_REG 0x1910048 // CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_172_FIRST_REG 0x1910050 // CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_172_LAST_REG 0x1910050 // CLK_RST_CONTROLLER_ERR_COLLATOR_17_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR0_FIRST_REG 0x191f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR0_LAST_REG 0x191f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_17_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_390_FIRST_REG 0x1a70000 // CLK_RST_CONTROLLER_ERR_COLLATOR_39_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_390_LAST_REG 0x1a7001c // CLK_RST_CONTROLLER_ERR_COLLATOR_39_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_391_FIRST_REG 0x1a70030 // CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_391_LAST_REG 0x1a70048 // CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_392_FIRST_REG 0x1a70050 // CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_392_LAST_REG 0x1a70050 // CLK_RST_CONTROLLER_ERR_COLLATOR_39_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR0_FIRST_REG 0x1a7f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR0_LAST_REG 0x1a7f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_39_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_380_FIRST_REG 0x1a60000 // CLK_RST_CONTROLLER_ERR_COLLATOR_38_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_380_LAST_REG 0x1a6001c // CLK_RST_CONTROLLER_ERR_COLLATOR_38_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_381_FIRST_REG 0x1a60030 // CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_381_LAST_REG 0x1a60048 // CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_382_FIRST_REG 0x1a60050 // CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_382_LAST_REG 0x1a60050 // CLK_RST_CONTROLLER_ERR_COLLATOR_38_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR0_FIRST_REG 0x1a6f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR0_LAST_REG 0x1a6f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_38_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_370_FIRST_REG 0x1a50000 // CLK_RST_CONTROLLER_ERR_COLLATOR_37_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_370_LAST_REG 0x1a5001c // CLK_RST_CONTROLLER_ERR_COLLATOR_37_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_371_FIRST_REG 0x1a50030 // CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_371_LAST_REG 0x1a50048 // CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_372_FIRST_REG 0x1a50050 // CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_372_LAST_REG 0x1a50050 // CLK_RST_CONTROLLER_ERR_COLLATOR_37_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR0_FIRST_REG 0x1a5f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR0_LAST_REG 0x1a5f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_37_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_360_FIRST_REG 0x1a40000 // CLK_RST_CONTROLLER_ERR_COLLATOR_36_FEATURE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_360_LAST_REG 0x1a4001c // CLK_RST_CONTROLLER_ERR_COLLATOR_36_MISSIONERR_INJECT_UNLOCK_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_361_FIRST_REG 0x1a40030 // CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_MISSIONERR_ENABLE_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_361_LAST_REG 0x1a40048 // CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_LATENTERR_STATUS_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_362_FIRST_REG 0x1a40050 // CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_362_LAST_REG 0x1a40050 // CLK_RST_CONTROLLER_ERR_COLLATOR_36_ERRSLICE0_COUNTER_RELOAD_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR0_FIRST_REG 0x1a4f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0
#define CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR0_LAST_REG 0x1a4f000 // CLK_RST_CONTROLLER_ERR_COLLATOR_36_SCR_EC_SCR_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif

#endif // ifndef ARCLK_RST_H_INC
